rcar_gen3: drivers: qos: M3W: Fix checkpatch issues

Fix checkpatch issues, clean up macro indentation. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ifd397962c40d174c3af31cb440241cc8bd9335d3

diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
index 0dfd991003f733f64c322d982d30e0d3b2963ab6..f3d0d841fcd93526b6bc2b732ac7a9b980b470e6 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
@@ -12,28 +12,34 @@
 #include "../qos_reg.h"
 #include "qos_init_m3_v11.h"
 
-#define        RCAR_QOS_VERSION                "rev.0.19"
+#define        RCAR_QOS_VERSION                        "rev.0.19"
 
-#define QOSWT_TIME_BANK0                               (20000000U)     /* unit:ns */
+#define QOSWT_TIME_BANK0                       20000000U       /* unit:ns */
 
-#define        QOSWT_WTEN_ENABLE                               (0x1U)
+#define        QOSWT_WTEN_ENABLE                       0x1U
 
 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11     (SL_INIT_SSLOTCLK_M3_11 - 0x5U)
 
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT  (3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT  (9U)
-#define QOSWT_WTREF_SLOT0_EN                   ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN                   ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-
-#define QOSWT_WTSET0_REQ_SSLOT0                        (5U)
-#define WT_BASE_SUB_SLOT_NUM0                  (12U)
-#define QOSWT_WTSET0_PERIOD0_M3_11             ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
-#define QOSWT_WTSET0_SSLOT0                            (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0                 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#define QOSWT_WTSET1_PERIOD1_M3_11             ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
-#define QOSWT_WTSET1_SSLOT1                            (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET1_SLOTSLOT1                 (WT_BASE_SUB_SLOT_NUM0 -1U)
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT          3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT          9U
+#define QOSWT_WTREF_SLOT0_EN                           \
+       ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |      \
+       (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN                           \
+       ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |      \
+       (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0                        5U
+#define WT_BASE_SUB_SLOT_NUM0                  12U
+#define QOSWT_WTSET0_PERIOD0_M3_11                     \
+       ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_11) - 1U)
+#define QOSWT_WTSET0_SSLOT0                    (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0                 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_M3_11                     \
+       ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_11) - 1U)
+#define QOSWT_WTSET1_SSLOT1                    (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET1_SLOTSLOT1                 (WT_BASE_SUB_SLOT_NUM0 - 1U)
 
 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
 

diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
index 4165a1e081ac4b9fbc33c66ec88a8ce72d496a09..7d70225bfe1341f2370cdcd882c78430d8630474 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
@@ -12,28 +12,34 @@
 #include "../qos_reg.h"
 #include "qos_init_m3_v30.h"
 
-#define        RCAR_QOS_VERSION                "rev.0.03"
+#define        RCAR_QOS_VERSION                        "rev.0.03"
 
-#define QOSWT_TIME_BANK0                               (20000000U)     //unit:ns
+#define QOSWT_TIME_BANK0                       20000000U       /* unit:ns */
 
-#define        QOSWT_WTEN_ENABLE                               (0x1U)
+#define        QOSWT_WTEN_ENABLE                       0x1U
 
 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30     (SL_INIT_SSLOTCLK_M3_30 - 0x5U)
 
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT  (3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT  (9U)
-#define QOSWT_WTREF_SLOT0_EN                   ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-#define QOSWT_WTREF_SLOT1_EN                   ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
-
-#define QOSWT_WTSET0_REQ_SSLOT0                        (5U)
-#define WT_BASE_SUB_SLOT_NUM0                  (12U)
-#define QOSWT_WTSET0_PERIOD0_M3_30             ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U)
-#define QOSWT_WTSET0_SSLOT0                            (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0                 (WT_BASE_SUB_SLOT_NUM0 -1U)
-
-#define QOSWT_WTSET1_PERIOD1_M3_30             ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U)
-#define QOSWT_WTSET1_SSLOT1                            (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET1_SLOTSLOT1                 (WT_BASE_SUB_SLOT_NUM0 -1U)
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT          3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT          9U
+#define QOSWT_WTREF_SLOT0_EN                           \
+       ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |      \
+       (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN                           \
+       ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |      \
+       (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0                        5U
+#define WT_BASE_SUB_SLOT_NUM0                  12U
+#define QOSWT_WTSET0_PERIOD0_M3_30                     \
+       ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_30) - 1U)
+#define QOSWT_WTSET0_SSLOT0                    (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0                 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_M3_30                     \
+       ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_30) - 1U)
+#define QOSWT_WTSET1_SSLOT1                    (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET1_SLOTSLOT1                 (WT_BASE_SUB_SLOT_NUM0 - 1U)
 
 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT