drm/amdkfd: Vega20 bring up on amdkfd side
authorShaoyun Liu <Shaoyun.Liu@amd.com>
Tue, 31 Oct 2017 17:32:53 +0000 (13:32 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 27 Sep 2018 02:09:18 +0000 (21:09 -0500)
Add Vega20 device IDs, device info and enable it in KFD.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
drivers/gpu/drm/amd/amdkfd/kfd_device.c
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
drivers/gpu/drm/amd/amdkfd/kfd_topology.c

index d4560f1869bd4b5b545e4e63e8db86095a5140bd..56412b0e7e1c73d79ff2a701b5da7a54affb258a 100644 (file)
@@ -647,6 +647,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
                num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);
                break;
        case CHIP_VEGA10:
+       case CHIP_VEGA20:
                pcache_info = vega10_cache_info;
                num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
                break;
index 56f2bd0a02384e40754d196b58d571188c660c17..cb96bdfc8f3e931dbc5d4962dbdf3ac32c1ccbf2 100644 (file)
@@ -236,6 +236,22 @@ static const struct kfd_device_info vega10_vf_device_info = {
        .num_sdma_queues_per_engine = 2,
 };
 
+static const struct kfd_device_info vega20_device_info = {
+       .asic_family = CHIP_VEGA20,
+       .max_pasid_bits = 16,
+       .max_no_of_hqd  = 24,
+       .doorbell_size  = 8,
+       .ih_ring_entry_size = 8 * sizeof(uint32_t),
+       .event_interrupt_class = &event_interrupt_class_v9,
+       .num_of_watch_points = 4,
+       .mqd_size_aligned = MQD_SIZE_ALIGNED,
+       .supports_cwsr = true,
+       .needs_iommu_device = false,
+       .needs_pci_atomics = true,
+       .num_sdma_engines = 2,
+       .num_sdma_queues_per_engine = 8,
+};
+
 struct kfd_deviceid {
        unsigned short did;
        const struct kfd_device_info *device_info;
@@ -323,6 +339,12 @@ static const struct kfd_deviceid supported_devices[] = {
        { 0x6868, &vega10_device_info },        /* Vega10 */
        { 0x686C, &vega10_vf_device_info },     /* Vega10  vf*/
        { 0x687F, &vega10_device_info },        /* Vega10 */
+       { 0x66a0, &vega20_device_info },        /* Vega20 */
+       { 0x66a1, &vega20_device_info },        /* Vega20 */
+       { 0x66a2, &vega20_device_info },        /* Vega20 */
+       { 0x66a3, &vega20_device_info },        /* Vega20 */
+       { 0x66a7, &vega20_device_info },        /* Vega20 */
+       { 0x66af, &vega20_device_info }         /* Vega20 */
 };
 
 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
index afa21679ac44d38bd8f6e2c710b359d6655b3075..d6af31ccf0ee16b605dbd5aed14a70dd3091df9b 100644 (file)
@@ -1733,6 +1733,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
                break;
 
        case CHIP_VEGA10:
+       case CHIP_VEGA20:
        case CHIP_RAVEN:
                device_queue_manager_init_v9(&dqm->asic_ops);
                break;
index 97d5423c5673236aa142a7c22d46dbd1d26634f2..3d66cec414affb22a8bb15441314ac27d08adc80 100644 (file)
@@ -400,6 +400,7 @@ int kfd_init_apertures(struct kfd_process *process)
                                kfd_init_apertures_vi(pdd, id);
                                break;
                        case CHIP_VEGA10:
+                       case CHIP_VEGA20:
                        case CHIP_RAVEN:
                                kfd_init_apertures_v9(pdd, id);
                                break;
index 9f84b4d9fb884825ce6791c39bb87880d6b33c35..6c31f7370193c561653a170a61c0d51657892584 100644 (file)
@@ -322,6 +322,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
                break;
 
        case CHIP_VEGA10:
+       case CHIP_VEGA20:
        case CHIP_RAVEN:
                kernel_queue_init_v9(&kq->ops_asic_specific);
                break;
index 3bc25ab84f34033c96aadbf07cec0bf8226c8c7d..e33019a7a883cc1d2df8410ea141257d71297adb 100644 (file)
@@ -39,6 +39,7 @@ struct mqd_manager *mqd_manager_init(enum KFD_MQD_TYPE type,
        case CHIP_POLARIS11:
                return mqd_manager_init_vi_tonga(type, dev);
        case CHIP_VEGA10:
+       case CHIP_VEGA20:
        case CHIP_RAVEN:
                return mqd_manager_init_v9(type, dev);
        default:
index 1092631765cb5b09ef198be0caa2007407db0c13..c6080ed3b6a771aa7a672c9da81c94bc9e9ea6c5 100644 (file)
@@ -229,6 +229,7 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
                pm->pmf = &kfd_vi_pm_funcs;
                break;
        case CHIP_VEGA10:
+       case CHIP_VEGA20:
        case CHIP_RAVEN:
                pm->pmf = &kfd_v9_pm_funcs;
                break;
index 54ff7fe03e78705638c880bcff4da15df7f949c1..e3843c5929edffdf2d0bb45969e7818302c50336 100644 (file)
@@ -1278,6 +1278,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
                        HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
                break;
        case CHIP_VEGA10:
+       case CHIP_VEGA20:
        case CHIP_RAVEN:
                dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
                        HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &