ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig

Use Kconfig to select DDR version instead of using config header.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 4878eed40508e7aa7a2baf0354c89609c7d1b7d5..052417279f06fa8fbb31d3dd5f62a703e42411c0 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -331,6 +331,7 @@ config ARCH_B4420
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006379
@@ -350,6 +351,7 @@ config ARCH_B4860
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006379
@@ -368,6 +370,7 @@ config ARCH_B4860
 config ARCH_BSC9131
        bool
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_ESDHC111
@@ -379,6 +382,7 @@ config ARCH_BSC9131
 config ARCH_BSC9132
        bool
        select FSL_LAW
+       select SYS_FSL_DDR_VER_46
        select SYS_FSL_ERRATUM_A004477
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_A005434
@@ -394,6 +398,7 @@ config ARCH_BSC9132
 config ARCH_C29X
        bool
        select FSL_LAW
+       select SYS_FSL_DDR_VER_46
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_ESDHC111
        select SYS_FSL_HAS_DDR3
@@ -646,6 +651,7 @@ config ARCH_P3041
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A004849
        select SYS_FSL_ERRATUM_A005812
@@ -667,6 +673,7 @@ config ARCH_P4080
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A004580
        select SYS_FSL_ERRATUM_A004849
@@ -699,6 +706,7 @@ config ARCH_P5020
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A006261
        select SYS_FSL_ERRATUM_DDR_A003
@@ -716,6 +724,7 @@ config ARCH_P5040
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_44
        select SYS_FSL_ERRATUM_A004510
        select SYS_FSL_ERRATUM_A004699
        select SYS_FSL_ERRATUM_A005812
@@ -736,6 +745,7 @@ config ARCH_T1023
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
@@ -750,6 +760,7 @@ config ARCH_T1024
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
@@ -764,6 +775,7 @@ config ARCH_T1040
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008044
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
@@ -779,6 +791,7 @@ config ARCH_T1042
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008044
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A009663
@@ -794,6 +807,7 @@ config ARCH_T2080
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A006379
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
@@ -809,6 +823,7 @@ config ARCH_T2081
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A006379
        select SYS_FSL_ERRATUM_A006593
        select SYS_FSL_ERRATUM_A007186
@@ -824,6 +839,7 @@ config ARCH_T4160
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004468
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006379
@@ -840,6 +856,7 @@ config ARCH_T4240
        bool
        select E500MC
        select FSL_LAW
+       select SYS_FSL_DDR_VER_47
        select SYS_FSL_ERRATUM_A004468
        select SYS_FSL_ERRATUM_A005871
        select SYS_FSL_ERRATUM_A006261

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index dbc8d7a5b15ea8a07662a961b07fc0600048d1a4..4986f38f08a773155e11902e8169a4830a0d10b5 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -156,7 +156,6 @@
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_SYS_NUM_FM1_10GEC       1
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_5
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       32
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
@@ -178,7 +177,6 @@
 #define CONFIG_SYS_NUM_FM2_DTSEC       4
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_SYS_NUM_FM2_10GEC       1
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_4
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
@@ -198,7 +196,6 @@
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_SYS_NUM_FM1_10GEC       1
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_4
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       32
@@ -221,7 +218,6 @@
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_SYS_NUM_FM2_DTSEC       5
 #define CONFIG_SYS_NUM_FM2_10GEC       1
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_4
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
@@ -234,7 +230,6 @@
 #elif defined(CONFIG_ARCH_BSC9131)
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_4
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT     0xff600000
@@ -245,7 +240,6 @@
 #elif defined(CONFIG_ARCH_BSC9132)
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_6
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 #define CONFIG_SYS_FSL_DSP_DDR_ADDR    0x40000000
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
@@ -287,7 +281,6 @@
 #define CONFIG_SYS_NUM_FMAN            2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 #define CONFIG_SYS_PME_CLK             0
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM1_CLK             3
@@ -324,7 +317,6 @@
 #define CONFIG_SYS_CPRI_CLK            3
 #define CONFIG_SYS_ULB_CLK             4
 #define CONFIG_SYS_ETVPE_CLK           1
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
@@ -369,7 +361,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 #define CONFIG_PME_PLAT_CLK_DIV                2
 #define CONFIG_SYS_PME_CLK             CONFIG_PME_PLAT_CLK_DIV
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_FM_PLAT_CLK_DIV 1
@@ -404,7 +395,6 @@
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
-#define CONFIG_SYS_FSL_DDR_VER  FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_SYS_SDHC_CLK            0/* Select SDHC CLK begining from PLL1
@@ -453,7 +443,6 @@
 #define CONFIG_SYS_SDHC_CLK            1/* Select SDHC CLK begining from PLL2
                                            per rcw field value */
 #define CONFIG_SYS_SDHC_CLK_2_PLL      /* Select SDHC CLK from 2 PLLs */
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
@@ -470,7 +459,6 @@
 #elif defined(CONFIG_ARCH_C29X)
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_TSECV2_1
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_6
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  3
 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET  0x20000