mtd: nand: pxa3xx-nand: fix random command timeouts

When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read after
an erase.

The issue is that in the interrupt handler, the status bits are cleared
after the new command is issued. There is a small temporal window where
this happens :
 - the previous command has set the command done bit
 - the ready for a command bit is set
 - the handler submits the next command
   - just then, the command completes, and the command done bit is still
     set
 - the handler clears the "previous" command done bit
 - the handler exits

In this flow, the "command done" of the next command will never trigger
a new interrupt to finish the status command, as it was cleared for both
commands.

Fix this by clearing the status bit before submitting a new command.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index faf056ba95b34fc8a0a44c92020e526949c3cd0d..51f8a58ed1a9c9a8f1d4cbf2ef92b52d8e2b8408 100644 (file)
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -678,8 +678,14 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
                is_ready = 1;
        }
 
+       /*
+        * Clear all status bit before issuing the next command, which
+        * can and will alter the status bits and will deserve a new
+        * interrupt on its own. This lets the controller exit the IRQ
+        */
+       nand_writel(info, NDSR, status);
+
        if (status & NDSR_WRCMDREQ) {
-               nand_writel(info, NDSR, NDSR_WRCMDREQ);
                status &= ~NDSR_WRCMDREQ;
                info->state = STATE_CMD_HANDLE;
 
@@ -700,8 +706,6 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
                        nand_writel(info, NDCB0, info->ndcb3);
        }
 
-       /* clear NDSR to let the controller exit the IRQ */
-       nand_writel(info, NDSR, status);
        if (is_completed)
                complete(&info->cmd_complete);
        if (is_ready)