arm, imx6, i2c: add I2C4 for MX6DL
authorHeiko Schocher <hs@denx.de>
Mon, 18 May 2015 08:56:24 +0000 (10:56 +0200)
committerStefano Babic <sbabic@denx.de>
Tue, 26 May 2015 12:16:54 +0000 (14:16 +0200)
add I2C4 modul for MX6DL based boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/imx-common/i2c-mxv7.c
arch/arm/include/asm/arch-mx6/crm_regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h
drivers/i2c/mxc_i2c.c

index 055f44e8e46c210f3bd94dba47c130185192d3be..ae9994530459f59877bec8a3da04f4e8ac47dd79 100644 (file)
@@ -140,23 +140,34 @@ int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 #endif
 
 #ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0 - 3 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
        u32 reg;
        u32 mask;
 
-       if (i2c_num > 2)
+       if (i2c_num > 3)
                return -EINVAL;
-
-       mask = MXC_CCM_CCGR_CG_MASK
-               << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
-       reg = __raw_readl(&imx_ccm->CCGR2);
-       if (enable)
-               reg |= mask;
-       else
-               reg &= ~mask;
-       __raw_writel(reg, &imx_ccm->CCGR2);
+       if (i2c_num < 3) {
+               mask = MXC_CCM_CCGR_CG_MASK
+                       << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+                       + (i2c_num << 1));
+               reg = __raw_readl(&imx_ccm->CCGR2);
+               if (enable)
+                       reg |= mask;
+               else
+                       reg &= ~mask;
+               __raw_writel(reg, &imx_ccm->CCGR2);
+       } else {
+               mask = MXC_CCM_CCGR_CG_MASK
+                       << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
+               reg = __raw_readl(&imx_ccm->CCGR1);
+               if (enable)
+                       reg |= mask;
+               else
+                       reg &= ~mask;
+               __raw_writel(reg, &imx_ccm->CCGR1);
+       }
        return 0;
 }
 #endif
index f3a5c3f3262d56dbf9f7e749aa1d757d9d9bbd9b..ff72b1a1fc8101984ae50ea39a46a5dc342a04fe 100644 (file)
@@ -67,9 +67,12 @@ static void * const i2c_bases[] = {
 #ifdef I2C3_BASE_ADDR
        (void *)I2C3_BASE_ADDR,
 #endif
+#ifdef I2C4_BASE_ADDR
+       (void *)I2C4_BASE_ADDR,
+#endif
 };
 
-/* i2c_index can be from 0 - 2 */
+/* i2c_index can be from 0 - 3 */
 int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
              struct i2c_pads_info *p)
 {
index 0592ce01714f492fa7f7893e8c638d9baf9619d4..887d04850f63f242948298dff167d41ad7b1c8be 100644 (file)
@@ -592,6 +592,8 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET               10
 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET               8
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK                 (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET                        12
 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK                  (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET          14
index 35bb005552f9a2694283b771cd929298b51e054f..0d38d450daa8a37d80dfa9490e5dd948797c7f4c 100644 (file)
 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
index 81adf6f450329d38ed6179f71d2dc92460accec3..2949e52b72a3f9bb9b9f9a937914b3f74b5d2a47 100644 (file)
@@ -517,6 +517,9 @@ static struct mxc_i2c_bus mxc_i2c_buses[] = {
        { 0, I2C1_BASE_ADDR },
        { 1, I2C2_BASE_ADDR },
        { 2, I2C3_BASE_ADDR },
+#if defined(CONFIG_MX6DL)
+       { 3, I2C4_BASE_ADDR },
+#endif
 #elif defined(CONFIG_LS102XA)
        { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
        { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },