- Migrate to new GIC interfaces.
- Remove unused bl1_init_bl2_mem_layout().
- Migrate to bl31_early_platform_setup2().
- Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE.
- Remove references to removed build options.
- Update Makefile paths.
Change-Id: I583fd893555e6535f32d87ed67bbae430b8e6afe
Tested-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <generic_delay_timer.h>
#include <gicv2.h>
#include <hi3660.h>
+#include <interrupt_props.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
*****************************************************************************/
-const unsigned int g0_interrupt_array[] = {
- IRQ_SEC_PHY_TIMER,
- IRQ_SEC_SGI_0
+static const interrupt_prop_t g0_interrupt_props[] = {
+ INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
const gicv2_driver_data_t hikey960_gic_data = {
.gicd_base = GICD_REG_BASE,
.gicc_base = GICC_REG_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
- .g0_interrupt_array = g0_interrupt_array,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};
meminfo_t *bl1_plat_sec_mem_layout(void)
return &bl1_tzram_layout;
}
-/*******************************************************************************
- * Function that takes a memory layout into which BL2 has been loaded and
- * populates a new memory layout for BL2 that ensures that BL1's data sections
- * resident in secure RAM are not visible to BL2.
- ******************************************************************************/
-void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
- meminfo_t *bl2_mem_layout)
-{
-
- assert(bl1_mem_layout != NULL);
- assert(bl2_mem_layout != NULL);
-
- /*
- * Cannot remove BL1 RW data from the scope of memory visible to BL2
- * like arm platforms because they overlap in hikey960
- */
- bl2_mem_layout->total_base = BL2_BASE;
- bl2_mem_layout->total_size = NS_BL1U_LIMIT - BL2_BASE;
-
- flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
-}
-
/*
* Perform any BL1 specific platform actions.
*/
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <cci.h>
#include <hi3660.h>
#include <hisi_ipc.h>
#include <interrupt_mgmt.h>
+#include <interrupt_props.h>
#include <platform.h>
#include <platform_def.h>
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
*****************************************************************************/
-const unsigned int g0_interrupt_array[] = {
- IRQ_SEC_PHY_TIMER,
- IRQ_SEC_SGI_0
+static const interrupt_prop_t g0_interrupt_props[] = {
+ INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
const gicv2_driver_data_t hikey960_gic_data = {
.gicd_base = GICD_REG_BASE,
.gicc_base = GICC_REG_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
- .g0_interrupt_array = g0_interrupt_array,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};
static const int cci_map[] = {
return NULL;
}
-void bl31_early_platform_setup(void *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
unsigned int id, uart_base;
+ void *from_bl2;
+
+ from_bl2 = (void *) arg0;
generic_delay_timer_init();
hikey960_read_boardid(&id);
#define __PLAT_MACROS_S__
#include <cci.h>
-#include <gic_v2.h>
+#include <gicv2.h>
#include <hi3660.h>
#include <platform_def.h>
/*
* Platform specific page table and MMU setup constants
*/
-#define ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || defined(IMAGE_BL32)
#define MAX_XLAT_TABLES 3
# SPDX-License-Identifier: BSD-3-Clause
#
-# Enable version2 of image loading
-LOAD_IMAGE_V2 := 1
-
# Non-TF Boot ROM
BL2_AT_EL3 := 1
$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
endif
-ENABLE_PLAT_COMPAT := 0
-
USE_COHERENT_MEM := 1
PLAT_INCLUDES := -Iinclude/common/tbbr \
-Iplat/hisilicon/hikey960/include
-PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
+PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
- lib/aarch64/xlat_tables.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
+ lib/xlat_tables/xlat_tables_common.c \
plat/hisilicon/hikey960/aarch64/hikey960_common.c \
plat/hisilicon/hikey960/hikey960_boardid.c
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/cortex_a73.S \
- plat/common/aarch64/plat_psci_common.c \
+ plat/common/plat_psci_common.c \
plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
plat/hisilicon/hikey960/hikey960_bl31_setup.c \
plat/hisilicon/hikey960/hikey960_pm.c \
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
-USE_TBBR_DEFS := 1
-
AUTH_SOURCES := drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \