armv8/ls2085a: Fix generic timer clock source

The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Mark Rutland <mark.rutland@arm.com>

diff --git a/README b/README
index f5a719db9d3a43e0bf7e45a20e8362fc207cd770..a70af9864676652bd127fc1cdb1dfc7739472e96 100644 (file)
--- a/README
+++ b/README
@@ -690,6 +690,14 @@ The following options need to be configured:
                exists, unlike the similar options in the Linux kernel. Do not
                set these options unless they apply!
 
+               COUNTER_FREQUENCY
+               Generic timer clock source frequency.
+
+               COUNTER_FREQUENCY_REAL
+               Generic timer clock source frequency if the real clock is
+               different from COUNTER_FREQUENCY, and can only be determined
+               at run time.
+
                NOTE: The following can be machine specific errata. These
                do have ability to provide rudimentary version and machine
                specific checks, but expect no product checks.

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 94fd1474ed839522eabe1274fcf19534c10592da..e985181e8b9f1cd7c7f0cf1ed15fb5c7a77dc67c 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -395,3 +395,27 @@ int arch_early_init_r(void)
 
        return 0;
 }
+
+int timer_init(void)
+{
+       u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+       u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#ifdef COUNTER_FREQUENCY_REAL
+       unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+       /* Update with accurate clock frequency */
+       asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+#endif
+
+       /* Enable timebase for all clusters.
+        * It is safe to do so even some clusters are not enabled.
+        */
+       out_le32(cltbenr, 0xf);
+
+       /* Enable clock for timer
+        * This is a global setting.
+        */
+       out_le32(cntcr, 0x1);
+
+       return 0;
+}

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 886576ef99486034ec7594cc47c607f0e3358c37..53bdb4487cc0d8dab5120155e649f480b1e3969b 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -224,6 +224,9 @@ ENTRY(secondary_boot_func)
        /* physical address of this cpus spin table element */
        add     x11, x1, x0
 
+       ldr     x0, =__real_cntfrq
+       ldr     x0, [x0]
+       msr     cntfrq_el0, x0  /* set with real frequency */
        str     x9, [x11, #16]  /* LPID */
        mov     x4, #1
        str     x4, [x11, #8]   /* STATUS */
@@ -275,6 +278,9 @@ ENDPROC(secondary_switch_to_el1)
 
        /* 64 bit alignment for elements accessed as data */
        .align 4
+       .global __real_cntfrq
+__real_cntfrq:
+       .quad COUNTER_FREQUENCY
        .globl __secondary_boot_code_size
        .type __secondary_boot_code_size, %object
        /* Secondary Boot Code ends here */

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
index ce9c0c1bdbeb7746b3a456a9a9c2925754e4e607..da7853a5af4043068624c1876009e58e614a62fd 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
@@ -31,6 +31,13 @@ int fsl_lsch3_wake_seconday_cores(void)
        int i, timeout = 10;
        u64 *table = get_spin_tbl_addr();
 
+#ifdef COUNTER_FREQUENCY_REAL
+       /* update for secondary cores */
+       __real_cntfrq = COUNTER_FREQUENCY_REAL;
+       flush_dcache_range((unsigned long)&__real_cntfrq,
+                          (unsigned long)&__real_cntfrq + 8);
+#endif
+
        cores = cpu_mask();
        /* Clear spin table so that secondary processors
         * observe the correct value after waking up from wfe.

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
index 66144d6101d504ca67235c175210cca97ada1c07..c985d6a6bad6ebce0d38b649000e4abffdaaf87a 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
@@ -26,6 +26,7 @@
 #define id_to_core(x)  ((x & 3) | (x >> 6))
 #ifndef __ASSEMBLY__
 extern u64 __spin_table[];
+extern u64 __real_cntfrq;
 extern u64 *secondary_boot_code;
 extern size_t __secondary_boot_code_size;
 int fsl_lsch3_wake_seconday_cores(void);

diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index e78c63ada0eb8b6681fca43acb9b86a9c766531d..bd016e90b131f7be2b26713ae6c3a625c2e9c6e8 100644 (file)
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -55,24 +55,6 @@ int dram_init(void)
        return 0;
 }
 
-int timer_init(void)
-{
-       u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
-       u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
-
-       /* Enable timebase for all clusters.
-        * It is safe to do so even some clusters are not enabled.
-        */
-       out_le32(cltbenr, 0xf);
-
-       /* Enable clock for timer
-        * This is a global setting.
-        */
-       out_le32(cntcr, 0x1);
-
-       return 0;
-}
-
 /*
  * Board specific reset that is system reset.
  */

diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 5721b18b6fae288d786f6e2c7a1bb47b1a54b03f..f6b3ed063ffe478a33731378d35e0346de6bc518 100644 (file)
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -72,7 +72,11 @@
 #define CONFIG_DP_DDR_NUM_CTRLS                1
 
 /* Generic Timer Definitions */
-#define COUNTER_FREQUENCY              12000000        /* 12MHz */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+#define COUNTER_FREQUENCY              25000000        /* 25MHz */
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2048 * 1024)