The I2C controller on Allwinner SoCs after A31 has a inverted interrupt
clear flag, which needs to be written 1 (rather than 0 on Marvell SoCs
and old Allwinner SoCs) to clear.
Add such a quirk to mi2cv driver common code.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
uint32_t reg;
reg = mmio_read_32((uintptr_t)&base->control);
+#ifndef I2C_INTERRUPT_CLEAR_INVERTED
reg &= ~(I2C_CONTROL_IFLG);
+#else
+ reg |= I2C_CONTROL_IFLG;
+#endif
mmio_write_32((uintptr_t)&base->control, reg);
/* Wait for 1 us for the clear to take effect */
udelay(1);