clk: tegra: Optimize PLLX restore on Tegra20/30

There is no need to re-configure PLLX if its configuration in unchanged
on return from suspend / cpuidle, this saves 300us if PLLX is already
enabled (common case for cpuidle).

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index cceefbd67a3bf6381c4a01f491568374cb6324c2..4d8222f5c63893ea348ca0003a7ace0b5b487ab4 100644 (file)
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -955,6 +955,7 @@ static void tegra20_cpu_clock_suspend(void)
 static void tegra20_cpu_clock_resume(void)
 {
        unsigned int reg, policy;
+       u32 misc, base;
 
        /* Is CPU complex already running on PLLX? */
        reg = readl(clk_base + CCLK_BURST_POLICY);
@@ -968,15 +969,21 @@ static void tegra20_cpu_clock_resume(void)
                BUG();
 
        if (reg != CCLK_BURST_POLICY_PLLX) {
-               /* restore PLLX settings if CPU is on different PLL */
-               writel(tegra20_cpu_clk_sctx.pllx_misc,
-                                       clk_base + PLLX_MISC);
-               writel(tegra20_cpu_clk_sctx.pllx_base,
-                                       clk_base + PLLX_BASE);
-
-               /* wait for PLL stabilization if PLLX was enabled */
-               if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
-                       udelay(300);
+               misc = readl_relaxed(clk_base + PLLX_MISC);
+               base = readl_relaxed(clk_base + PLLX_BASE);
+
+               if (misc != tegra20_cpu_clk_sctx.pllx_misc ||
+                   base != tegra20_cpu_clk_sctx.pllx_base) {
+                       /* restore PLLX settings if CPU is on different PLL */
+                       writel(tegra20_cpu_clk_sctx.pllx_misc,
+                                               clk_base + PLLX_MISC);
+                       writel(tegra20_cpu_clk_sctx.pllx_base,
+                                               clk_base + PLLX_BASE);
+
+                       /* wait for PLL stabilization if PLLX was enabled */
+                       if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
+                               udelay(300);
+               }
        }
 
        /*

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 95b0e4a16dd597cdacbb3dec7eba7d7383596c2b..c8bc18e4d7e5ac90f03d86ccdafec65fbad9f830 100644 (file)
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1163,6 +1163,7 @@ static void tegra30_cpu_clock_suspend(void)
 static void tegra30_cpu_clock_resume(void)
 {
        unsigned int reg, policy;
+       u32 misc, base;
 
        /* Is CPU complex already running on PLLX? */
        reg = readl(clk_base + CLK_RESET_CCLK_BURST);
@@ -1176,15 +1177,21 @@ static void tegra30_cpu_clock_resume(void)
                BUG();
 
        if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
-               /* restore PLLX settings if CPU is on different PLL */
-               writel(tegra30_cpu_clk_sctx.pllx_misc,
-                                       clk_base + CLK_RESET_PLLX_MISC);
-               writel(tegra30_cpu_clk_sctx.pllx_base,
-                                       clk_base + CLK_RESET_PLLX_BASE);
-
-               /* wait for PLL stabilization if PLLX was enabled */
-               if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
-                       udelay(300);
+               misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);
+               base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);
+
+               if (misc != tegra30_cpu_clk_sctx.pllx_misc ||
+                   base != tegra30_cpu_clk_sctx.pllx_base) {
+                       /* restore PLLX settings if CPU is on different PLL */
+                       writel(tegra30_cpu_clk_sctx.pllx_misc,
+                                               clk_base + CLK_RESET_PLLX_MISC);
+                       writel(tegra30_cpu_clk_sctx.pllx_base,
+                                               clk_base + CLK_RESET_PLLX_BASE);
+
+                       /* wait for PLL stabilization if PLLX was enabled */
+                       if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
+                               udelay(300);
+               }
        }
 
        /*