rcar_gen3: drivers: qos: M3N: Fix checkpatch issues

Fix checkpatch issues, clean up macro indentation. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I08c033b317685bef7537eb49de160e827b7791ad

diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
index 2d489f1f6df2ab42beaacf5e8c0e3e8f8268a271..116143ed0cfa63104db137e40d2559256e435032 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
@@ -12,27 +12,31 @@
 #include "../qos_reg.h"
 #include "qos_init_m3n_v10.h"
 
-#define        RCAR_QOS_VERSION                "rev.0.09"
+#define        RCAR_QOS_VERSION                        "rev.0.09"
 
-#define REF_ARS_ARBSTOPCYCLE_M3N       (((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
+#define REF_ARS_ARBSTOPCYCLE_M3N                       \
+       (((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
 
-#define QOSWT_TIME_BANK0                               (20000000U)     /* unit:ns */
+#define QOSWT_TIME_BANK0                       20000000U       /* unit:ns */
 
-#define        QOSWT_WTEN_ENABLE                               (0x1U)
+#define        QOSWT_WTEN_ENABLE                       0x1U
 
-#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT  (3U)
-#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT  (9U)
-#define QOSWT_WTREF_SLOT0_EN                   ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT          3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT          9U
+#define QOSWT_WTREF_SLOT0_EN                           \
+       ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) |      \
+       (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
 #define QOSWT_WTREF_SLOT1_EN                   QOSWT_WTREF_SLOT0_EN
 
-#define QOSWT_WTSET0_REQ_SSLOT0                        (5U)
-#define WT_BASE_SUB_SLOT_NUM0                  (12U)
-#define QOSWT_WTSET0_PERIOD0_M3N               ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3N)-1U)
-#define QOSWT_WTSET0_SSLOT0                            (QOSWT_WTSET0_REQ_SSLOT0 -1U)
-#define QOSWT_WTSET0_SLOTSLOT0                 (WT_BASE_SUB_SLOT_NUM0 -1U)
+#define QOSWT_WTSET0_REQ_SSLOT0                        5U
+#define WT_BASE_SUB_SLOT_NUM0                  12U
+#define QOSWT_WTSET0_PERIOD0_M3N                       \
+       ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3N) - 1U)
+#define QOSWT_WTSET0_SSLOT0                    (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0                 (WT_BASE_SUB_SLOT_NUM0 - 1U)
 
 #define QOSWT_WTSET1_PERIOD1_M3N               QOSWT_WTSET0_PERIOD0_M3N
-#define QOSWT_WTSET1_SSLOT1                            QOSWT_WTSET0_SSLOT0
+#define QOSWT_WTSET1_SSLOT1                    QOSWT_WTSET0_SSLOT0
 #define QOSWT_WTSET1_SLOTSLOT1                 QOSWT_WTSET0_SLOTSLOT0
 
 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT