[brcm63xx] use macros to generate SPI registers table and switches

SVN-Revision: 27246

diff --git a/target/linux/brcm63xx/patches-2.6.39/240-spi.patch b/target/linux/brcm63xx/patches-2.6.39/240-spi.patch
index 57149c27d1f5cfe470a560c1adb1ab48f4e073c6..fb7dd9134de29ea96bbb9b3714b7f9e5f28e72ae 100644 (file)
--- a/target/linux/brcm63xx/patches-2.6.39/240-spi.patch
+++ b/target/linux/brcm63xx/patches-2.6.39/240-spi.patch
@@ -26,13 +26,13 @@
        [IRQ_DSL]               = BCM_6358_DSL_IRQ,
 --- /dev/null
 +++ b/arch/mips/bcm63xx/dev-spi.c
-@@ -0,0 +1,131 @@
+@@ -0,0 +1,98 @@
 +/*
 + * This file is subject to the terms and conditions of the GNU General Public
 + * License.  See the file "COPYING" in the main directory of this archive
 + * for more details.
 + *
-+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
++ * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 + */
 +
@@ -49,48 +49,15 @@
 + * register offsets
 + */
 +static const unsigned long bcm96338_regs_spi[] = {
-+      [SPI_CMD]               = SPI_BCM_6338_SPI_CMD,
-+      [SPI_INT_STATUS]        = SPI_BCM_6338_SPI_INT_STATUS,
-+      [SPI_INT_MASK_ST]       = SPI_BCM_6338_SPI_MASK_INT_ST,
-+      [SPI_INT_MASK]          = SPI_BCM_6338_SPI_INT_MASK,
-+      [SPI_ST]                = SPI_BCM_6338_SPI_ST,
-+      [SPI_CLK_CFG]           = SPI_BCM_6338_SPI_CLK_CFG,
-+      [SPI_FILL_BYTE]         = SPI_BCM_6338_SPI_FILL_BYTE,
-+      [SPI_MSG_TAIL]          = SPI_BCM_6338_SPI_MSG_TAIL,
-+      [SPI_RX_TAIL]           = SPI_BCM_6338_SPI_RX_TAIL,
-+      [SPI_MSG_CTL]           = SPI_BCM_6338_SPI_MSG_CTL,
-+      [SPI_MSG_DATA]          = SPI_BCM_6338_SPI_MSG_DATA,
-+      [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
++      __GEN_SPI_REGS_TABLE(6338)
 +};
 +
 +static const unsigned long bcm96348_regs_spi[] = {
-+      [SPI_CMD]               = SPI_BCM_6348_SPI_CMD,
-+      [SPI_INT_STATUS]        = SPI_BCM_6348_SPI_INT_STATUS,
-+      [SPI_INT_MASK_ST]       = SPI_BCM_6348_SPI_MASK_INT_ST,
-+      [SPI_INT_MASK]          = SPI_BCM_6348_SPI_INT_MASK,
-+      [SPI_ST]                = SPI_BCM_6348_SPI_ST,
-+      [SPI_CLK_CFG]           = SPI_BCM_6348_SPI_CLK_CFG,
-+      [SPI_FILL_BYTE]         = SPI_BCM_6348_SPI_FILL_BYTE,
-+      [SPI_MSG_TAIL]          = SPI_BCM_6348_SPI_MSG_TAIL,
-+      [SPI_RX_TAIL]           = SPI_BCM_6348_SPI_RX_TAIL,
-+      [SPI_MSG_CTL]           = SPI_BCM_6348_SPI_MSG_CTL,
-+      [SPI_MSG_DATA]          = SPI_BCM_6348_SPI_MSG_DATA,
-+      [SPI_RX_DATA]           = SPI_BCM_6348_SPI_RX_DATA,
++      __GEN_SPI_REGS_TABLE(6348)
 +};
 +
 +static const unsigned long bcm96358_regs_spi[] = {
-+      [SPI_CMD]               = SPI_BCM_6358_SPI_CMD,
-+      [SPI_INT_STATUS]        = SPI_BCM_6358_SPI_INT_STATUS,
-+      [SPI_INT_MASK_ST]       = SPI_BCM_6358_SPI_MASK_INT_ST,
-+      [SPI_INT_MASK]          = SPI_BCM_6358_SPI_INT_MASK,
-+      [SPI_ST]                = SPI_BCM_6358_SPI_STATUS,
-+      [SPI_CLK_CFG]           = SPI_BCM_6358_SPI_CLK_CFG,
-+      [SPI_FILL_BYTE]         = SPI_BCM_6358_SPI_FILL_BYTE,
-+      [SPI_MSG_TAIL]          = SPI_BCM_6358_SPI_MSG_TAIL,
-+      [SPI_RX_TAIL]           = SPI_BCM_6358_SPI_RX_TAIL,
-+      [SPI_MSG_CTL]           = SPI_BCM_6358_MSG_CTL,
-+      [SPI_MSG_DATA]          = SPI_BCM_6358_SPI_MSG_DATA,
-+      [SPI_RX_DATA]           = SPI_BCM_6358_SPI_RX_DATA,
++      __GEN_SPI_REGS_TABLE(6358)
 +};
 +
 +const unsigned long *bcm63xx_regs_spi;
@@ -214,7 +181,7 @@
 +/* BCM 6338 SPI core */
 +#define SPI_BCM_6338_SPI_CMD          0x00    /* 16-bits register */
 +#define SPI_BCM_6338_SPI_INT_STATUS   0x02
-+#define SPI_BCM_6338_SPI_MASK_INT_ST  0x03
++#define SPI_BCM_6338_SPI_INT_MASK_ST  0x03
 +#define SPI_BCM_6338_SPI_INT_MASK     0x04
 +#define SPI_BCM_6338_SPI_ST           0x05
 +#define SPI_BCM_6338_SPI_CLK_CFG      0x06
@@ -228,7 +195,7 @@
 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
 +
 +/* BCM 6348 SPI core */
-+#define SPI_BCM_6348_SPI_MASK_INT_ST  0x00
++#define SPI_BCM_6348_SPI_INT_MASK_ST  0x00
 +#define SPI_BCM_6348_SPI_INT_STATUS   0x01
 +#define SPI_BCM_6348_SPI_CMD          0x02    /* 16-bits register */
 +#define SPI_BCM_6348_SPI_FILL_BYTE    0x04
@@ -244,7 +211,7 @@
 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
 +
 +/* BCM 6358 SPI core */
-+#define SPI_BCM_6358_MSG_CTL          0x00    /* 16-bits register */
++#define SPI_BCM_6358_SPI_MSG_CTL      0x00    /* 16-bits register */
 +
 +#define SPI_BCM_6358_SPI_MSG_DATA     0x02
 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE        0x21e
@@ -255,11 +222,11 @@
 +#define SPI_BCM_6358_SPI_CMD          0x700   /* 16-bits register */
 +
 +#define SPI_BCM_6358_SPI_INT_STATUS   0x702
-+#define SPI_BCM_6358_SPI_MASK_INT_ST  0x703
++#define SPI_BCM_6358_SPI_INT_MASK_ST  0x703
 +
 +#define SPI_BCM_6358_SPI_INT_MASK     0x704
 +
-+#define SPI_BCM_6358_SPI_STATUS               0x705
++#define SPI_BCM_6358_SPI_ST           0x705
 +
 +#define SPI_BCM_6358_SPI_CLK_CFG      0x706
 +
@@ -846,7 +813,7 @@
  spi_s3c24xx_hw-y                      := spi_s3c24xx.o
 --- /dev/null
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
-@@ -0,0 +1,126 @@
+@@ -0,0 +1,85 @@
 +#ifndef BCM63XX_DEV_SPI_H
 +#define BCM63XX_DEV_SPI_H
 +
@@ -878,6 +845,40 @@
 +        SPI_RX_DATA,
 +};
 +
++#define __GEN_SPI_RSET_BASE(__cpu, __rset)                            \
++      case SPI_## __rset:                                             \
++              return SPI_BCM_## __cpu ##_SPI_## __rset ##;
++
++#define __GEN_SPI_RSET(__cpu)                                         \
++      switch (reg) {                                                  \
++      __GEN_SPI_RSET_BASE(__cpu, CMD)                                 \
++      __GEN_SPI_RSET_BASE(__cpu, INT_STATUS)                          \
++      __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST)                         \
++      __GEN_SPI_RSET_BASE(__cpu, INT_MASK)                            \
++      __GEN_SPI_RSET_BASE(__cpu, ST)                                  \
++      __GEN_SPI_RSET_BASE(__cpu, CLK_CFG)                             \
++      __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE)                           \
++      __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL)                            \
++      __GEN_SPI_RSET_BASE(__cpu, RX_TAIL)                             \
++      __GEN_SPI_RSET_BASE(__cpu, MSG_CTL)                             \
++      __GEN_SPI_RSET_BASE(__cpu, MSG_DATA)                            \
++      __GEN_SPI_RSET_BASE(__cpu, RX_DATA)                             \
++      }
++
++#define __GEN_SPI_REGS_TABLE(__cpu)                                   \
++      [SPI_CMD]               = SPI_BCM_## __cpu ##_SPI_CMD,          \
++      [SPI_INT_STATUS]        = SPI_BCM_## __cpu ##_SPI_INT_STATUS,   \
++      [SPI_INT_MASK_ST]       = SPI_BCM_## __cpu ##_SPI_INT_MASK_ST,  \
++      [SPI_INT_MASK]          = SPI_BCM_## __cpu ##_SPI_INT_MASK,     \
++      [SPI_ST]                = SPI_BCM_## __cpu ##_SPI_ST,           \
++      [SPI_CLK_CFG]           = SPI_BCM_## __cpu ##_SPI_CLK_CFG,      \
++      [SPI_FILL_BYTE]         = SPI_BCM_## __cpu ##_SPI_FILL_BYTE,    \
++      [SPI_MSG_TAIL]          = SPI_BCM_## __cpu ##_SPI_MSG_TAIL,     \
++      [SPI_RX_TAIL]           = SPI_BCM_## __cpu ##_SPI_RX_TAIL,      \
++      [SPI_MSG_CTL]           = SPI_BCM_## __cpu ##_SPI_MSG_CTL,      \
++      [SPI_MSG_DATA]          = SPI_BCM_## __cpu ##_SPI_MSG_DATA,     \
++      [SPI_RX_DATA]           = SPI_BCM_## __cpu ##_SPI_RX_DATA,
++
 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 +{
 +#ifdef BCMCPU_RUNTIME_DETECT
@@ -885,88 +886,13 @@
 +        return bcm63xx_regs_spi[reg];
 +#else
 +#ifdef CONFIG_BCM63XX_CPU_6338
-+switch (reg) {
-+      case SPI_CMD:
-+              return SPI_BCM_6338_SPI_CMD;
-+      case SPI_INT_STATUS:
-+              return SPI_BCM_6338_SPI_INT_STATUS;
-+      case SPI_INT_MASK_ST:
-+              return SPI_BCM_6338_SPI_MASK_INT_ST;
-+      case SPI_INT_MASK:
-+              return SPI_BCM_6338_SPI_INT_MASK;
-+      case SPI_ST:
-+              return SPI_BCM_6338_SPI_ST;
-+      case SPI_CLK_CFG:
-+              return SPI_BCM_6338_SPI_CLK_CFG;
-+      case SPI_FILL_BYTE:
-+              return SPI_BCM_6338_SPI_FILL_BYTE;
-+      case SPI_MSG_TAIL:
-+              return SPI_BCM_6338_SPI_MSG_TAIL;
-+      case SPI_RX_TAIL:
-+              return SPI_BCM_6338_SPI_RX_TAIL;
-+      case SPI_MSG_CTL:
-+              return SPI_BCM_6338_SPI_MSG_CTL;
-+      case SPI_MSG_DATA:
-+              return SPI_BCM_6338_SPI_MSG_DATA;
-+      case SPI_RX_DATA:
-+              return SPI_BCM_6338_SPI_RX_DATA;
-+}
++      __GEN_SPI_RSET(6338)
 +#endif
 +#ifdef CONFIG_BCM63XX_CPU_6348
-+switch (reg) {
-+      case SPI_CMD:
-+              return SPI_BCM_6348_SPI_CMD;
-+      case SPI_INT_MASK_ST:
-+              return SPI_BCM_6348_SPI_MASK_INT_ST;
-+      case SPI_INT_MASK:
-+              return SPI_BCM_6348_SPI_INT_MASK;
-+      case SPI_INT_STATUS:
-+              return SPI_BCM_6348_SPI_INT_STATUS;
-+      case SPI_ST:
-+              return SPI_BCM_6348_SPI_ST;
-+      case SPI_CLK_CFG:
-+              return SPI_BCM_6348_SPI_CLK_CFG;
-+      case SPI_FILL_BYTE:
-+              return SPI_BCM_6348_SPI_FILL_BYTE;
-+      case SPI_MSG_TAIL:
-+              return SPI_BCM_6348_SPI_MSG_TAIL;
-+      case SPI_RX_TAIL:
-+              return SPI_BCM_6348_SPI_RX_TAIL;
-+      case SPI_MSG_CTL:
-+              return SPI_BCM_6348_SPI_MSG_CTL;
-+      case SPI_MSG_DATA:
-+              return SPI_BCM_6348_SPI_MSG_DATA;
-+      case SPI_RX_DATA:
-+              return SPI_BCM_6348_SPI_RX_DATA;
-+}
++      __GEN_SPI_RSET(6348)
 +#endif
 +#ifdef CONFIG_BCM63XX_CPU_6358
-+switch (reg) {
-+      case SPI_CMD:
-+              return SPI_BCM_6358_SPI_CMD;
-+      case SPI_INT_STATUS:
-+              return SPI_BCM_6358_SPI_INT_STATUS;
-+      case SPI_INT_MASK_ST:
-+              return SPI_BCM_6358_SPI_MASK_INT_ST;
-+      case SPI_INT_MASK:
-+              return SPI_BCM_6358_SPI_INT_MASK;
-+      case SPI_ST:
-+              return SPI_BCM_6358_SPI_STATUS;
-+      case SPI_CLK_CFG:
-+              return SPI_BCM_6358_SPI_CLK_CFG;
-+      case SPI_FILL_BYTE:
-+              return SPI_BCM_6358_SPI_FILL_BYTE;
-+      case SPI_MSG_TAIL:
-+              return SPI_BCM_6358_SPI_MSG_TAIL;
-+      case SPI_RX_TAIL:
-+              return SPI_BCM_6358_SPI_RX_TAIL;
-+      case SPI_MSG_CTL:
-+              return SPI_BCM_6358_MSG_CTL;
-+      case SPI_MSG_DATA:
-+              return SPI_BCM_6358_SPI_MSG_DATA;
-+      case SPI_RX_DATA:
-+              return SPI_BCM_6358_SPI_RX_DATA;
-+}
++      __GEN_SPI_RSET(6358)
 +#endif
 +#endif
 +      return 0;

diff --git a/target/linux/brcm63xx/patches-3.0/240-spi.patch b/target/linux/brcm63xx/patches-3.0/240-spi.patch
index 0757e336d0e4a6a92c45adca466794b3b316ac8f..40606506f394238830b17d6d602bff4d594a5ef3 100644 (file)
--- a/target/linux/brcm63xx/patches-3.0/240-spi.patch
+++ b/target/linux/brcm63xx/patches-3.0/240-spi.patch
@@ -26,13 +26,13 @@
        [IRQ_DSL]               = BCM_6358_DSL_IRQ,
 --- /dev/null
 +++ b/arch/mips/bcm63xx/dev-spi.c
-@@ -0,0 +1,131 @@
+@@ -0,0 +1,98 @@
 +/*
 + * This file is subject to the terms and conditions of the GNU General Public
 + * License.  See the file "COPYING" in the main directory of this archive
 + * for more details.
 + *
-+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
++ * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 + */
 +
@@ -49,48 +49,15 @@
 + * register offsets
 + */
 +static const unsigned long bcm96338_regs_spi[] = {
-+      [SPI_CMD]               = SPI_BCM_6338_SPI_CMD,
-+      [SPI_INT_STATUS]        = SPI_BCM_6338_SPI_INT_STATUS,
-+      [SPI_INT_MASK_ST]       = SPI_BCM_6338_SPI_MASK_INT_ST,
-+      [SPI_INT_MASK]          = SPI_BCM_6338_SPI_INT_MASK,
-+      [SPI_ST]                = SPI_BCM_6338_SPI_ST,
-+      [SPI_CLK_CFG]           = SPI_BCM_6338_SPI_CLK_CFG,
-+      [SPI_FILL_BYTE]         = SPI_BCM_6338_SPI_FILL_BYTE,
-+      [SPI_MSG_TAIL]          = SPI_BCM_6338_SPI_MSG_TAIL,
-+      [SPI_RX_TAIL]           = SPI_BCM_6338_SPI_RX_TAIL,
-+      [SPI_MSG_CTL]           = SPI_BCM_6338_SPI_MSG_CTL,
-+      [SPI_MSG_DATA]          = SPI_BCM_6338_SPI_MSG_DATA,
-+      [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
++      __GEN_SPI_REGS_TABLE(6338)
 +};
 +
 +static const unsigned long bcm96348_regs_spi[] = {
-+      [SPI_CMD]               = SPI_BCM_6348_SPI_CMD,
-+      [SPI_INT_STATUS]        = SPI_BCM_6348_SPI_INT_STATUS,
-+      [SPI_INT_MASK_ST]       = SPI_BCM_6348_SPI_MASK_INT_ST,
-+      [SPI_INT_MASK]          = SPI_BCM_6348_SPI_INT_MASK,
-+      [SPI_ST]                = SPI_BCM_6348_SPI_ST,
-+      [SPI_CLK_CFG]           = SPI_BCM_6348_SPI_CLK_CFG,
-+      [SPI_FILL_BYTE]         = SPI_BCM_6348_SPI_FILL_BYTE,
-+      [SPI_MSG_TAIL]          = SPI_BCM_6348_SPI_MSG_TAIL,
-+      [SPI_RX_TAIL]           = SPI_BCM_6348_SPI_RX_TAIL,
-+      [SPI_MSG_CTL]           = SPI_BCM_6348_SPI_MSG_CTL,
-+      [SPI_MSG_DATA]          = SPI_BCM_6348_SPI_MSG_DATA,
-+      [SPI_RX_DATA]           = SPI_BCM_6348_SPI_RX_DATA,
++      __GEN_SPI_REGS_TABLE(6348)
 +};
 +
 +static const unsigned long bcm96358_regs_spi[] = {
-+      [SPI_CMD]               = SPI_BCM_6358_SPI_CMD,
-+      [SPI_INT_STATUS]        = SPI_BCM_6358_SPI_INT_STATUS,
-+      [SPI_INT_MASK_ST]       = SPI_BCM_6358_SPI_MASK_INT_ST,
-+      [SPI_INT_MASK]          = SPI_BCM_6358_SPI_INT_MASK,
-+      [SPI_ST]                = SPI_BCM_6358_SPI_STATUS,
-+      [SPI_CLK_CFG]           = SPI_BCM_6358_SPI_CLK_CFG,
-+      [SPI_FILL_BYTE]         = SPI_BCM_6358_SPI_FILL_BYTE,
-+      [SPI_MSG_TAIL]          = SPI_BCM_6358_SPI_MSG_TAIL,
-+      [SPI_RX_TAIL]           = SPI_BCM_6358_SPI_RX_TAIL,
-+      [SPI_MSG_CTL]           = SPI_BCM_6358_MSG_CTL,
-+      [SPI_MSG_DATA]          = SPI_BCM_6358_SPI_MSG_DATA,
-+      [SPI_RX_DATA]           = SPI_BCM_6358_SPI_RX_DATA,
++      __GEN_SPI_REGS_TABLE(6358)
 +};
 +
 +const unsigned long *bcm63xx_regs_spi;
@@ -214,7 +181,7 @@
 +/* BCM 6338 SPI core */
 +#define SPI_BCM_6338_SPI_CMD          0x00    /* 16-bits register */
 +#define SPI_BCM_6338_SPI_INT_STATUS   0x02
-+#define SPI_BCM_6338_SPI_MASK_INT_ST  0x03
++#define SPI_BCM_6338_SPI_INT_MASK_ST  0x03
 +#define SPI_BCM_6338_SPI_INT_MASK     0x04
 +#define SPI_BCM_6338_SPI_ST           0x05
 +#define SPI_BCM_6338_SPI_CLK_CFG      0x06
@@ -228,7 +195,7 @@
 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
 +
 +/* BCM 6348 SPI core */
-+#define SPI_BCM_6348_SPI_MASK_INT_ST  0x00
++#define SPI_BCM_6348_SPI_INT_MASK_ST  0x00
 +#define SPI_BCM_6348_SPI_INT_STATUS   0x01
 +#define SPI_BCM_6348_SPI_CMD          0x02    /* 16-bits register */
 +#define SPI_BCM_6348_SPI_FILL_BYTE    0x04
@@ -244,7 +211,7 @@
 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
 +
 +/* BCM 6358 SPI core */
-+#define SPI_BCM_6358_MSG_CTL          0x00    /* 16-bits register */
++#define SPI_BCM_6358_SPI_MSG_CTL      0x00    /* 16-bits register */
 +
 +#define SPI_BCM_6358_SPI_MSG_DATA     0x02
 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE        0x21e
@@ -255,11 +222,11 @@
 +#define SPI_BCM_6358_SPI_CMD          0x700   /* 16-bits register */
 +
 +#define SPI_BCM_6358_SPI_INT_STATUS   0x702
-+#define SPI_BCM_6358_SPI_MASK_INT_ST  0x703
++#define SPI_BCM_6358_SPI_INT_MASK_ST  0x703
 +
 +#define SPI_BCM_6358_SPI_INT_MASK     0x704
 +
-+#define SPI_BCM_6358_SPI_STATUS               0x705
++#define SPI_BCM_6358_SPI_ST           0x705
 +
 +#define SPI_BCM_6358_SPI_CLK_CFG      0x706
 +
@@ -846,7 +813,7 @@
  spi_s3c24xx_hw-y                      := spi_s3c24xx.o
 --- /dev/null
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
-@@ -0,0 +1,126 @@
+@@ -0,0 +1,85 @@
 +#ifndef BCM63XX_DEV_SPI_H
 +#define BCM63XX_DEV_SPI_H
 +
@@ -878,6 +845,40 @@
 +        SPI_RX_DATA,
 +};
 +
++#define __GEN_SPI_RSET_BASE(__cpu, __rset)                            \
++      case SPI_## __rset:                                             \
++              return SPI_BCM_## __cpu ##_SPI_## __rset ##;
++
++#define __GEN_SPI_RSET(__cpu)                                         \
++      switch (reg) {                                                  \
++      __GEN_SPI_RSET_BASE(__cpu, CMD)                                 \
++      __GEN_SPI_RSET_BASE(__cpu, INT_STATUS)                          \
++      __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST)                         \
++      __GEN_SPI_RSET_BASE(__cpu, INT_MASK)                            \
++      __GEN_SPI_RSET_BASE(__cpu, ST)                                  \
++      __GEN_SPI_RSET_BASE(__cpu, CLK_CFG)                             \
++      __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE)                           \
++      __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL)                            \
++      __GEN_SPI_RSET_BASE(__cpu, RX_TAIL)                             \
++      __GEN_SPI_RSET_BASE(__cpu, MSG_CTL)                             \
++      __GEN_SPI_RSET_BASE(__cpu, MSG_DATA)                            \
++      __GEN_SPI_RSET_BASE(__cpu, RX_DATA)                             \
++      }
++
++#define __GEN_SPI_REGS_TABLE(__cpu)                                   \
++      [SPI_CMD]               = SPI_BCM_## __cpu ##_SPI_CMD,          \
++      [SPI_INT_STATUS]        = SPI_BCM_## __cpu ##_SPI_INT_STATUS,   \
++      [SPI_INT_MASK_ST]       = SPI_BCM_## __cpu ##_SPI_INT_MASK_ST,  \
++      [SPI_INT_MASK]          = SPI_BCM_## __cpu ##_SPI_INT_MASK,     \
++      [SPI_ST]                = SPI_BCM_## __cpu ##_SPI_ST,           \
++      [SPI_CLK_CFG]           = SPI_BCM_## __cpu ##_SPI_CLK_CFG,      \
++      [SPI_FILL_BYTE]         = SPI_BCM_## __cpu ##_SPI_FILL_BYTE,    \
++      [SPI_MSG_TAIL]          = SPI_BCM_## __cpu ##_SPI_MSG_TAIL,     \
++      [SPI_RX_TAIL]           = SPI_BCM_## __cpu ##_SPI_RX_TAIL,      \
++      [SPI_MSG_CTL]           = SPI_BCM_## __cpu ##_SPI_MSG_CTL,      \
++      [SPI_MSG_DATA]          = SPI_BCM_## __cpu ##_SPI_MSG_DATA,     \
++      [SPI_RX_DATA]           = SPI_BCM_## __cpu ##_SPI_RX_DATA,
++
 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 +{
 +#ifdef BCMCPU_RUNTIME_DETECT
@@ -885,88 +886,13 @@
 +        return bcm63xx_regs_spi[reg];
 +#else
 +#ifdef CONFIG_BCM63XX_CPU_6338
-+switch (reg) {
-+      case SPI_CMD:
-+              return SPI_BCM_6338_SPI_CMD;
-+      case SPI_INT_STATUS:
-+              return SPI_BCM_6338_SPI_INT_STATUS;
-+      case SPI_INT_MASK_ST:
-+              return SPI_BCM_6338_SPI_MASK_INT_ST;
-+      case SPI_INT_MASK:
-+              return SPI_BCM_6338_SPI_INT_MASK;
-+      case SPI_ST:
-+              return SPI_BCM_6338_SPI_ST;
-+      case SPI_CLK_CFG:
-+              return SPI_BCM_6338_SPI_CLK_CFG;
-+      case SPI_FILL_BYTE:
-+              return SPI_BCM_6338_SPI_FILL_BYTE;
-+      case SPI_MSG_TAIL:
-+              return SPI_BCM_6338_SPI_MSG_TAIL;
-+      case SPI_RX_TAIL:
-+              return SPI_BCM_6338_SPI_RX_TAIL;
-+      case SPI_MSG_CTL:
-+              return SPI_BCM_6338_SPI_MSG_CTL;
-+      case SPI_MSG_DATA:
-+              return SPI_BCM_6338_SPI_MSG_DATA;
-+      case SPI_RX_DATA:
-+              return SPI_BCM_6338_SPI_RX_DATA;
-+}
++      __GEN_SPI_RSET(6338)
 +#endif
 +#ifdef CONFIG_BCM63XX_CPU_6348
-+switch (reg) {
-+      case SPI_CMD:
-+              return SPI_BCM_6348_SPI_CMD;
-+      case SPI_INT_MASK_ST:
-+              return SPI_BCM_6348_SPI_MASK_INT_ST;
-+      case SPI_INT_MASK:
-+              return SPI_BCM_6348_SPI_INT_MASK;
-+      case SPI_INT_STATUS:
-+              return SPI_BCM_6348_SPI_INT_STATUS;
-+      case SPI_ST:
-+              return SPI_BCM_6348_SPI_ST;
-+      case SPI_CLK_CFG:
-+              return SPI_BCM_6348_SPI_CLK_CFG;
-+      case SPI_FILL_BYTE:
-+              return SPI_BCM_6348_SPI_FILL_BYTE;
-+      case SPI_MSG_TAIL:
-+              return SPI_BCM_6348_SPI_MSG_TAIL;
-+      case SPI_RX_TAIL:
-+              return SPI_BCM_6348_SPI_RX_TAIL;
-+      case SPI_MSG_CTL:
-+              return SPI_BCM_6348_SPI_MSG_CTL;
-+      case SPI_MSG_DATA:
-+              return SPI_BCM_6348_SPI_MSG_DATA;
-+      case SPI_RX_DATA:
-+              return SPI_BCM_6348_SPI_RX_DATA;
-+}
++      __GEN_SPI_RSET(6348)
 +#endif
 +#ifdef CONFIG_BCM63XX_CPU_6358
-+switch (reg) {
-+      case SPI_CMD:
-+              return SPI_BCM_6358_SPI_CMD;
-+      case SPI_INT_STATUS:
-+              return SPI_BCM_6358_SPI_INT_STATUS;
-+      case SPI_INT_MASK_ST:
-+              return SPI_BCM_6358_SPI_MASK_INT_ST;
-+      case SPI_INT_MASK:
-+              return SPI_BCM_6358_SPI_INT_MASK;
-+      case SPI_ST:
-+              return SPI_BCM_6358_SPI_STATUS;
-+      case SPI_CLK_CFG:
-+              return SPI_BCM_6358_SPI_CLK_CFG;
-+      case SPI_FILL_BYTE:
-+              return SPI_BCM_6358_SPI_FILL_BYTE;
-+      case SPI_MSG_TAIL:
-+              return SPI_BCM_6358_SPI_MSG_TAIL;
-+      case SPI_RX_TAIL:
-+              return SPI_BCM_6358_SPI_RX_TAIL;
-+      case SPI_MSG_CTL:
-+              return SPI_BCM_6358_MSG_CTL;
-+      case SPI_MSG_DATA:
-+              return SPI_BCM_6358_SPI_MSG_DATA;
-+      case SPI_RX_DATA:
-+              return SPI_BCM_6358_SPI_RX_DATA;
-+}
++      __GEN_SPI_RSET(6358)
 +#endif
 +#endif
 +      return 0;