drm/i915/gtt: enable GTT cache by default

For some platforms the GTT cache is by default not enabled, and
currently where we explicitly enable it, we make it conditional on 2M GTT
page support, since the BSpec states that we must disable it if we
enable 2M/1G pages. To make this more consistent opt for blanket
enabling the GTT cache for all relevant gens in a single place, while
still keeping the same behaviour of checking for 2M support.

BSpec: 9314
BSpec: 423
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190809193456.3836-1-matthew.auld@intel.com

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 83a02e773c5876c661a9ccb466ceb3e18b32d352..72a227c43e35d71b6a573dbfb922fd081f9b4fb4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2035,6 +2035,27 @@ static void gtt_write_workarounds(struct intel_gt *gt)
                                 GEN8_GAMW_ECO_DEV_RW_IA,
                                 0,
                                 GAMW_ECO_ENABLE_64K_IPS_FIELD);
+
+       if (IS_GEN_RANGE(i915, 8, 11)) {
+               bool can_use_gtt_cache = true;
+
+               /*
+                * According to the BSpec if we use 2M/1G pages then we also
+                * need to disable the GTT cache. At least on BDW we can see
+                * visual corruption when using 2M pages, and not disabling the
+                * GTT cache.
+                */
+               if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_2M))
+                       can_use_gtt_cache = false;
+
+               /* WaGttCachingOffByDefault */
+               intel_uncore_write(uncore,
+                                  HSW_GTT_CACHE_EN,
+                                  can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
+               WARN_ON_ONCE(can_use_gtt_cache &&
+                            intel_uncore_read(uncore,
+                                              HSW_GTT_CACHE_EN) == 0);
+       }
 }
 
 int i915_ppgtt_init_hw(struct intel_gt *gt)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 780df8db2eba71bdbcc9a529336f9a5d40b25c80..aca676e79948621e3ece0d7292d761ac679fce8d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9169,9 +9169,6 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
 
 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       /* The GTT cache must be disabled if the system is using 2M pages. */
-       bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
-                                                I915_GTT_PAGE_SIZE_2M);
        enum pipe pipe;
 
        /* WaSwitchSolVfFArbitrationPriority:bdw */
@@ -9204,9 +9201,6 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
        /* WaProgramL3SqcReg1Default:bdw */
        gen8_set_l3sqc_credits(dev_priv, 30, 2);
 
-       /* WaGttCachingOffByDefault:bdw */
-       I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
-
        /* WaKVMNotificationOnConfigChange:bdw */
        I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
                   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
@@ -9471,12 +9465,6 @@ static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
         * LSQC Setting Recommendations.
         */
        gen8_set_l3sqc_credits(dev_priv, 38, 2);
-
-       /*
-        * GTT cache may not work with big pages, so if those
-        * are ever enabled GTT cache may need to be disabled.
-        */
-       I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
 }
 
 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)