#address-cells = <1>;
#size-cells = <1>;
- sysc: sysc@0 {
- compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc", "syscon";
+ sysc: syscon@0 {
+ compatible = "ralink,mt7620-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
timer: timer@100 {
compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
reg = <0x100 0x20>;
+ clocks = <&sysc 5>;
+
interrupt-parent = <&intc>;
interrupts = <1>;
};
compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- resets = <&rstctrl 8>;
+ clocks = <&sysc 6>;
+
+ resets = <&sysc 8>;
reset-names = "wdt";
interrupt-parent = <&intc>;
compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
reg = <0x200 0x100>;
- resets = <&rstctrl 19>;
+ resets = <&sysc 19>;
reset-names = "intc";
interrupt-controller;
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
- resets = <&rstctrl 20>;
+ resets = <&sysc 20>;
reset-names = "mc";
interrupt-parent = <&intc>;
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
- resets = <&rstctrl 12>;
- reset-names = "uart";
+ clocks = <&sysc 7>;
+
+ resets = <&sysc 12>;
interrupt-parent = <&intc>;
interrupts = <5>;
compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
reg = <0x600 0x34>;
- resets = <&rstctrl 13>;
+ resets = <&sysc 13>;
reset-names = "pio";
interrupt-parent = <&intc>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- resets = <&rstctrl 16>;
+ clocks = <&sysc 8>;
+
+ resets = <&sysc 16>;
reset-names = "i2c";
#address-cells = <1>;
compatible = "mediatek,mt7620-i2s";
reg = <0xa00 0x100>;
- resets = <&rstctrl 17>;
+ clocks = <&sysc 9>;
+
+ resets = <&sysc 17>;
reset-names = "i2s";
interrupt-parent = <&intc>;
compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
reg = <0xb00 0x40>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 10>;
+
+ resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
compatible = "ralink,rt2880-spi";
reg = <0xb40 0x60>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 11>;
+
+ resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- resets = <&rstctrl 19>;
- reset-names = "uartl";
+ clocks = <&sysc 12>;
+
+ resets = <&sysc 19>;
interrupt-parent = <&intc>;
interrupts = <12>;
compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
reg = <0xd00 0x10>;
- resets = <&rstctrl 28>;
+ resets = <&sysc 28>;
reset-names = "intc";
interrupt-parent = <&cpuintc>;
compatible = "ralink,mt7620a-pcm";
reg = <0x2000 0x800>;
- resets = <&rstctrl 11>;
+ resets = <&sysc 11>;
reset-names = "pcm";
interrupt-parent = <&intc>;
compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
- resets = <&rstctrl 14>;
+ resets = <&sysc 14>;
reset-names = "dma";
interrupt-parent = <&intc>;
};
};
- rstctrl: rstctrl {
- compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
usbphy: usbphy {
compatible = "mediatek,mt7620-usbphy";
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
- resets = <&rstctrl 22 &rstctrl 25>;
+ /* usb phy reset is only controled by RSTCTRL bit 25 */
+ resets = <&sysc 25>, <&sysc 22>;
reset-names = "host", "device";
-
- clocks = <&clkctrl 22 &clkctrl 25>;
- clock-names = "host", "device";
};
ethernet: ethernet@10100000 {
interrupt-parent = <&cpuintc>;
interrupts = <5>;
- resets = <&rstctrl 21 &rstctrl 23>;
+ resets = <&sysc 21>, <&sysc 23>;
reset-names = "fe", "esw";
mediatek,switch = <&gsw>;
compatible = "mediatek,mt7620-gsw";
reg = <0x10110000 0x8000>;
- resets = <&rstctrl 23>;
+ resets = <&sysc 23>;
reset-names = "esw";
interrupt-parent = <&intc>;
#address-cells = <3>;
#size-cells = <2>;
- resets = <&rstctrl 26>;
+ resets = <&sysc 26>;
reset-names = "pcie0";
- clocks = <&clkctrl 26>;
- clock-names = "pcie0";
-
interrupt-parent = <&cpuintc>;
interrupts = <4>;
compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
reg = <0x10180000 0x40000>;
+ clocks = <&sysc 13>;
+
interrupt-parent = <&cpuintc>;
interrupts = <6>;
#address-cells = <1>;
#size-cells = <1>;
- sysc: sysc@0 {
- compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc", "syscon";
+ sysc: syscon@0 {
+ compatible = "ralink,mt7620-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
timer: timer@100 {
compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
reg = <0x100 0x20>;
+ clocks = <&sysc 5>;
+
interrupt-parent = <&intc>;
interrupts = <1>;
};
compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- resets = <&rstctrl 8>;
+ clocks = <&sysc 6>;
+
+ resets = <&sysc 8>;
reset-names = "wdt";
interrupt-parent = <&intc>;
compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
reg = <0x200 0x100>;
- resets = <&rstctrl 19>;
+ resets = <&sysc 19>;
reset-names = "intc";
interrupt-controller;
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
- resets = <&rstctrl 20>;
+ resets = <&sysc 20>;
reset-names = "mc";
interrupt-parent = <&intc>;
compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
reg = <0x600 0x34>;
- resets = <&rstctrl 13>;
+ resets = <&sysc 13>;
reset-names = "pio";
interrupt-parent = <&intc>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- resets = <&rstctrl 16>;
+ clocks = <&sysc 8>;
+
+ resets = <&sysc 16>;
reset-names = "i2c";
#address-cells = <1>;
compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
reg = <0xb00 0x40>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 10>;
+
+ resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
compatible = "ralink,rt2880-spi";
reg = <0xb40 0x60>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 11>;
+
+ resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- resets = <&rstctrl 19>;
- reset-names = "uartl";
+ clocks = <&sysc 12>;
+
+ resets = <&sysc 19>;
interrupt-parent = <&intc>;
interrupts = <12>;
compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
reg = <0xd00 0x10>;
- resets = <&rstctrl 28>;
+ resets = <&sysc 28>;
reset-names = "intc";
interrupt-parent = <&cpuintc>;
};
};
- rstctrl: rstctrl {
- compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
usbphy: usbphy {
compatible = "mediatek,mt7620-usbphy";
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
- resets = <&rstctrl 22 &rstctrl 25>;
+ /* usb phy reset is only controled by RSTCTRL bit 25 */
+ resets = <&sysc 25>, <&sysc 22>;
reset-names = "host", "device";
-
- clocks = <&clkctrl 22 &clkctrl 25>;
- clock-names = "host", "device";
};
ethernet: ethernet@10100000 {
interrupt-parent = <&cpuintc>;
interrupts = <5>;
- resets = <&rstctrl 21 &rstctrl 23>;
+ resets = <&sysc 21>, <&sysc 23>;
reset-names = "fe", "esw";
mediatek,switch = <&gsw>;
compatible = "mediatek,mt7620-gsw";
reg = <0x10110000 0x8000>;
- resets = <&rstctrl 23>;
+ resets = <&sysc 23>;
reset-names = "esw";
interrupt-parent = <&intc>;
compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
reg = <0x10180000 0x40000>;
+ clocks = <&sysc 13>;
+
interrupt-parent = <&cpuintc>;
interrupts = <6>;
#address-cells = <1>;
#size-cells = <1>;
- sysc: sysc@0 {
- compatible = "ralink,mt7620a-sysc", "syscon";
+ sysc: syscon@0 {
+ compatible = "ralink,mt7628-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
watchdog: watchdog@100 {
compatible = "ralink,mt7628an-wdt", "mediatek,mt7621-wdt";
reg = <0x100 0x30>;
- resets = <&rstctrl 8>;
+ clocks = <&sysc 6>;
+
+ resets = <&sysc 8>;
reset-names = "wdt";
interrupt-parent = <&intc>;
compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
reg = <0x200 0x100>;
- resets = <&rstctrl 9>;
+ resets = <&sysc 9>;
reset-names = "intc";
interrupt-controller;
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
- resets = <&rstctrl 10>;
+ resets = <&sysc 10>;
reset-names = "mc";
interrupt-parent = <&intc>;
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
- resets = <&rstctrl 16>;
+ clocks = <&sysc 7>;
+ clock-names = "i2c";
+
+ resets = <&sysc 16>;
reset-names = "i2c";
#address-cells = <1>;
compatible = "mediatek,mt7628-i2s";
reg = <0xa00 0x100>;
- resets = <&rstctrl 17>;
+ clocks = <&sysc 8>;
+
+ resets = <&sysc 17>;
reset-names = "i2s";
interrupt-parent = <&intc>;
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 9>;
+ clock-names = "spi";
+
+ resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
status = "disabled";
};
- uartlite: uartlite@c00 {
+ uartlite: uart0@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
reg-io-width = <4>;
no-loopback-test;
- clock-frequency = <40000000>;
+ clocks = <&sysc 11>;
- resets = <&rstctrl 12>;
- reset-names = "uartl";
+ resets = <&sysc 12>;
interrupt-parent = <&intc>;
interrupts = <20>;
reg-io-width = <4>;
no-loopback-test;
- clock-frequency = <40000000>;
+ clocks = <&sysc 12>;
- resets = <&rstctrl 19>;
- reset-names = "uart1";
+ resets = <&sysc 19>;
interrupt-parent = <&intc>;
interrupts = <21>;
reg-io-width = <4>;
no-loopback-test;
- clock-frequency = <40000000>;
+ clocks = <&sysc 13>;
- resets = <&rstctrl 20>;
- reset-names = "uart2";
+ resets = <&sysc 20>;
interrupt-parent = <&intc>;
interrupts = <22>;
reg = <0x5000 0x1000>;
#pwm-cells = <2>;
- resets = <&rstctrl 31>;
+ resets = <&sysc 31>;
reset-names = "pwm";
pinctrl-names = "default";
compatible = "ralink,mt7620a-pcm";
reg = <0x2000 0x800>;
- resets = <&rstctrl 11>;
+ resets = <&sysc 11>;
reset-names = "pcm";
interrupt-parent = <&intc>;
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
- resets = <&rstctrl 14>;
+ resets = <&sysc 14>;
reset-names = "dma";
interrupt-parent = <&intc>;
};
};
- rstctrl: rstctrl {
- compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
usbphy: usbphy@10120000 {
compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy";
reg = <0x10120000 0x1000>;
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
- resets = <&rstctrl 22 &rstctrl 25>;
+ /* usb phy reset is only controled by RSTCTRL bit 22 */
+ resets = <&sysc 22>, <&sysc 25>;
reset-names = "host", "device";
- clocks = <&clkctrl 22 &clkctrl 25>;
- clock-names = "host", "device";
};
sdhci: sdhci@10130000 {
interrupt-parent = <&cpuintc>;
interrupts = <5>;
- resets = <&rstctrl 21>;
+ resets = <&sysc 21>;
reset-names = "fe";
mediatek,switch = <&esw>;
compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw";
reg = <0x10110000 0x8000>;
- resets = <&rstctrl 23 &rstctrl 24>;
+ resets = <&sysc 23>, <&sysc 24>;
reset-names = "esw", "ephy";
interrupt-parent = <&intc>;
interrupt-parent = <&cpuintc>;
interrupts = <4>;
- resets = <&rstctrl 26 &rstctrl 27>;
- reset-names = "pcie0", "pcie1";
- clocks = <&clkctrl 26 &clkctrl 27>;
- clock-names = "pcie0", "pcie1";
+ resets = <&sysc 26>;
+ reset-names = "pcie0";
status = "disabled";
compatible = "mediatek,mt7628-wmac";
reg = <0x10300000 0x100000>;
+ clocks = <&sysc 14>;
+
interrupt-parent = <&cpuintc>;
interrupts = <6>;
#address-cells = <1>;
#size-cells = <1>;
- sysc: sysc@0 {
- compatible = "ralink,rt2880-sysc";
- reg = <0x000 0x100>;
+ sysc: syscon@0 {
+ compatible = "ralink,rt2880-sysc", "syscon";
+ reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
timer: timer@100 {
compatible = "ralink,rt2880-timer";
reg = <0x100 0x20>;
+ clocks = <&sysc 3>;
+
interrupt-parent = <&intc>;
interrupts = <1>;
watchdog: watchdog@120 {
compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>;
+
+ clocks = <&sysc 4>;
};
intc: intc@200 {
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- resets = <&rstctrl 9>;
+ clocks = <&sysc 6>;
+
+ resets = <&sysc 9>;
reset-names = "i2c";
#address-cells = <1>;
compatible = "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
+ clocks = <&sysc 7>;
+
interrupt-parent = <&intc>;
interrupts = <8>;
};
};
- rstctrl: rstctrl {
- compatible = "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
pci: pci@440000 {
compatible = "ralink,rt288x-pci";
reg = <0x00440000 0x20000>;
#address-cells = <1>;
#size-cells = <0>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 8>;
+
+ resets = <&sysc 18>;
reset-names = "fe";
interrupt-parent = <&cpuintc>;
compatible = "ralink,rt2880-wmac";
reg = <0x480000 0x40000>;
+ clocks = <&sysc 9>;
+
interrupt-parent = <&cpuintc>;
interrupts = <6>;
#address-cells = <1>;
#size-cells = <1>;
- sysc: sysc@0 {
+ sysc: syscon@0 {
compatible = "ralink,rt3050-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
timer: timer@100 {
compatible = "ralink,rt3050-timer", "ralink,rt2880-timer";
reg = <0x100 0x20>;
+ clocks = <&sysc 3>;
+
interrupt-parent = <&intc>;
interrupts = <1>;
};
compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- resets = <&rstctrl 8>;
+ clocks = <&sysc 4>;
+
+ resets = <&sysc 8>;
reset-names = "wdt";
interrupt-parent = <&intc>;
compatible = "ralink,rt3050-intc", "ralink,rt2880-intc";
reg = <0x200 0x100>;
- resets = <&rstctrl 19>;
+ resets = <&sysc 19>;
reset-names = "intc";
interrupt-controller;
compatible = "ralink,rt3050-memc";
reg = <0x300 0x100>;
- resets = <&rstctrl 20>;
+ resets = <&sysc 20>;
reset-names = "mc";
interrupt-parent = <&intc>;
compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
- resets = <&rstctrl 12>;
- reset-names = "uart";
+ clocks = <&sysc 5>;
+
+ resets = <&sysc 12>;
interrupt-parent = <&intc>;
interrupts = <5>;
20 24 28 2c
30 34 ];
- resets = <&rstctrl 13>;
+ resets = <&sysc 13>;
reset-names = "pio";
interrupt-parent = <&intc>;
compatible = "ralink,rt305x-gdma";
reg = <0x700 0x100>;
- resets = <&rstctrl 14>;
+ resets = <&sysc 14>;
reset-names = "dma";
interrupt-parent = <&intc>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- resets = <&rstctrl 16>;
+ clocks = <&sysc 6>;
+
+ resets = <&sysc 16>;
reset-names = "i2c";
#address-cells = <1>;
compatible = "ralink,rt3050-i2s";
reg = <0xa00 0x100>;
- resets = <&rstctrl 17>;
+ clocks = <&sysc 7>;
+
+ resets = <&sysc 17>;
reset-names = "i2s";
interrupt-parent = <&intc>;
compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
reg = <0xb00 0x100>;
- resets = <&rstctrl 18>;
+ resets = <&sysc 18>;
reset-names = "spi";
+ clocks = <&sysc 8>;
+
#address-cells = <1>;
#size-cells = <0>;
compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- resets = <&rstctrl 19>;
- reset-names = "uartl";
+ clocks = <&sysc 10>;
+
+ resets = <&sysc 19>;
interrupt-parent = <&intc>;
interrupts = <12>;
};
};
- rstctrl: rstctrl {
- compatible = "ralink,rt3050-reset", "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
usbphy: usbphy {
compatible = "ralink,rt3050-usbphy";
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
- resets = <&rstctrl 22>;
+ resets = <&sysc 22>;
reset-names = "host";
- clocks = <&clkctrl 18>;
- clock-names = "host";
};
ethernet: ethernet@10100000 {
compatible = "ralink,rt3050-eth";
reg = <0x10100000 0x10000>;
- resets = <&rstctrl 21>;
+ clocks = <&sysc 11>;
+
+ resets = <&sysc 21>;
reset-names = "fe";
interrupt-parent = <&cpuintc>;
compatible = "ralink,rt3050-esw";
reg = <0x10110000 0x8000>;
- resets = <&rstctrl 23 &rstctrl 24>;
+ resets = <&sysc 23>, <&sysc 24>;
reset-names = "esw", "ephy";
interrupt-parent = <&intc>;
compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
reg = <0x10180000 0x40000>;
+ clocks = <&sysc 12>;
+
interrupt-parent = <&cpuintc>;
interrupts = <6>;
interrupt-parent = <&intc>;
interrupts = <18>;
- resets = <&rstctrl 22>;
+ resets = <&sysc 22>;
reset-names = "otg";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
- sysc: sysc@0 {
- compatible = "ralink,rt3352-sysc", "ralink,rt3050-sysc", "syscon";
+ sysc: syscon@0 {
+ compatible = "ralink,rt3352-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
timer: timer@100 {
compatible = "ralink,rt3352-timer", "ralink,rt2880-timer";
reg = <0x100 0x20>;
+ clocks = <&sysc 4>;
+
interrupt-parent = <&intc>;
interrupts = <1>;
};
compatible = "ralink,rt3352-wdt", "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- resets = <&rstctrl 8>;
+ clocks = <&sysc 5>;
+
+ resets = <&sysc 8>;
reset-names = "wdt";
interrupt-parent = <&intc>;
compatible = "ralink,rt3352-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
- resets = <&rstctrl 20>;
+ resets = <&sysc 20>;
reset-names = "mc";
interrupt-parent = <&intc>;
compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
- resets = <&rstctrl 12>;
- reset-names = "uart";
+ clocks = <&sysc 6>;
+
+ resets = <&sysc 12>;
interrupt-parent = <&intc>;
interrupts = <5>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
- resets = <&rstctrl 13>;
+ resets = <&sysc 13>;
reset-names = "pio";
interrupt-parent = <&intc>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- resets = <&rstctrl 16>;
+ clocks = <&sysc 7>;
+
+ resets = <&sysc 16>;
reset-names = "i2c";
#address-cells = <1>;
compatible = "ralink,rt3352-i2s";
reg = <0xa00 0x100>;
- resets = <&rstctrl 17>;
+ clocks = <&sysc 8>;
+
+ resets = <&sysc 17>;
reset-names = "i2s";
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <0>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 9>;
+
+ resets = <&sysc 18>;
reset-names = "spi";
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
- resets = <&rstctrl 18>;
+ resets = <&sysc 18>;
reset-names = "spi";
pinctrl-names = "default";
compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- resets = <&rstctrl 19>;
- reset-names = "uartl";
+ clocks = <&sysc 11>;
+
+ resets = <&sysc 19>;
interrupt-parent = <&intc>;
interrupts = <12>;
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
- resets = <&rstctrl 14>;
+ resets = <&sysc 14>;
reset-names = "dma";
interrupt-parent = <&intc>;
};
};
- rstctrl: rstctrl {
- compatible = "ralink,rt3352-reset", "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
ethernet: ethernet@10100000 {
compatible = "ralink,rt3352-eth", "ralink,rt3050-eth";
reg = <0x10100000 0x10000>;
- resets = <&rstctrl 21>;
+ clocks = <&sysc 12>;
+
+ resets = <&sysc 21>;
reset-names = "fe";
interrupt-parent = <&cpuintc>;
compatible = "ralink,rt3352-esw", "ralink,rt3050-esw";
reg = <0x10110000 0x8000>;
- resets = <&rstctrl 23 &rstctrl 24>;
+ resets = <&sysc 23>, <&sysc 24>;
reset-names = "esw", "ephy";
interrupt-parent = <&intc>;
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
- resets = <&rstctrl 22 &rstctrl 25>;
+ resets = <&sysc 22>, <&sysc 25>;
reset-names = "host", "device";
- clocks = <&clkctrl 18 &clkctrl 20>;
- clock-names = "host", "device";
};
wmac: wmac@10180000 {
compatible = "ralink,rt3352-wmac", "ralink,rt2880-wmac";
reg = <0x10180000 0x40000>;
+ clocks = <&sysc 13>;
+
interrupt-parent = <&cpuintc>;
interrupts = <6>;
#address-cells = <1>;
#size-cells = <1>;
- sysc: sysc@0 {
- compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc", "syscon";
+ sysc: syscon@0 {
+ compatible = "ralink,rt3883-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
timer: timer@100 {
compatible = "ralink,rt3883-timer", "ralink,rt2880-timer";
reg = <0x100 0x20>;
+ clocks = <&sysc 3>;
+
interrupt-parent = <&intc>;
interrupts = <1>;
};
compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- resets = <&rstctrl 8>;
+ clocks = <&sysc 4>;
+
+ resets = <&sysc 8>;
reset-names = "wdt";
interrupt-parent = <&intc>;
compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
reg = <0x200 0x100>;
- resets = <&rstctrl 19>;
+ resets = <&sysc 19>;
reset-names = "intc";
interrupt-controller;
compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
- resets = <&rstctrl 20>;
+ resets = <&sysc 20>;
reset-names = "mc";
interrupt-parent = <&intc>;
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
- resets = <&rstctrl 12>;
- reset-names = "uart";
+ clocks = <&sysc 5>;
+
+ resets = <&sysc 12>;
interrupt-parent = <&intc>;
interrupts = <5>;
compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
reg = <0x600 0x34>;
- resets = <&rstctrl 13>;
+ resets = <&sysc 13>;
reset-names = "pio";
interrupt-parent = <&intc>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- resets = <&rstctrl 16>;
+ clocks = <&sysc 6>;
+
+ resets = <&sysc 16>;
reset-names = "i2c";
#address-cells = <1>;
compatible = "ralink,rt3883-i2s";
reg = <0xa00 0x100>;
- resets = <&rstctrl 17>;
+ clocks = <&sysc 7>;
+
+ resets = <&sysc 17>;
reset-names = "i2s";
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <0>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 8>;
+
+ resets = <&sysc 18>;
reset-names = "spi";
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 9>;
+
+ resets = <&sysc 18>;
reset-names = "spi";
pinctrl-names = "default";
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- resets = <&rstctrl 19>;
- reset-names = "uartl";
+ clocks = <&sysc 10>;
+
+ resets = <&sysc 19>;
interrupt-parent = <&intc>;
interrupts = <12>;
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
- resets = <&rstctrl 14>;
+ resets = <&sysc 14>;
reset-names = "dma";
interrupt-parent = <&intc>;
#size-cells = <0>;
reg = <0x10100000 0x10000>;
- resets = <&rstctrl 21>;
+ clocks = <&sysc 11>;
+
+ resets = <&sysc 21>;
reset-names = "fe";
interrupt-parent = <&cpuintc>;
};
};
- rstctrl: rstctrl {
- compatible = "ralink,rt3883-reset", "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
pci: pci@10140000 {
compatible = "ralink,rt3883-pci";
reg = <0x10140000 0x20000>;
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
- resets = <&rstctrl 22 &rstctrl 25>;
+ resets = <&sysc 22>, <&sysc 25>;
reset-names = "host", "device";
- clocks = <&clkctrl 22 &clkctrl 25>;
- clock-names = "host", "device";
};
wmac: wmac@10180000 {
compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac";
reg = <0x10180000 0x40000>;
+ clocks = <&sysc 12>;
+
interrupt-parent = <&cpuintc>;
interrupts = <6>;
#address-cells = <1>;
#size-cells = <1>;
- sysc: sysc@0 {
- compatible = "ralink,rt5350-sysc", "ralink,rt3050-sysc", "syscon";
+ sysc: syscon@0 {
+ compatible = "ralink,rt5350-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
timer: timer@100 {
compatible = "ralink,rt5350-timer", "ralink,rt2880-timer";
reg = <0x100 0x20>;
+ clocks = <&sysc 4>;
+
interrupt-parent = <&intc>;
interrupts = <1>;
};
compatible = "ralink,rt5350-wdt", "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- resets = <&rstctrl 8>;
+ clocks = <&sysc 5>;
+
+ resets = <&sysc 8>;
reset-names = "wdt";
interrupt-parent = <&intc>;
compatible = "ralink,rt5350-intc", "ralink,rt2880-intc";
reg = <0x200 0x100>;
- resets = <&rstctrl 19>;
+ resets = <&sysc 19>;
reset-names = "intc";
interrupt-controller;
compatible = "ralink,rt5350-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
- resets = <&rstctrl 20>;
+ resets = <&sysc 20>;
reset-names = "mc";
interrupt-parent = <&intc>;
compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
- resets = <&rstctrl 12>;
- reset-names = "uart";
+ clocks = <&sysc 6>;
+
+ resets = <&sysc 12>;
interrupt-parent = <&intc>;
interrupts = <5>;
compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
reg = <0x600 0x34>;
- resets = <&rstctrl 13>;
+ resets = <&sysc 13>;
reset-names = "pio";
interrupt-parent = <&intc>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- resets = <&rstctrl 16>;
+ clocks = <&sysc 7>;
+
+ resets = <&sysc 16>;
reset-names = "i2c";
#address-cells = <1>;
compatible = "ralink,rt3352-i2s";
reg = <0xa00 0x100>;
- resets = <&rstctrl 17>;
+ clocks = <&sysc 8>;
+
+ resets = <&sysc 17>;
reset-names = "i2s";
interrupt-parent = <&intc>;
compatible = "ralink,rt5350-spi", "ralink,rt2880-spi";
reg = <0xb00 0x40>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 9>;
+
+ resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
compatible = "ralink,rt5350-spi", "ralink,rt2880-spi";
reg = <0xb40 0x60>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 10>;
+
+ resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- resets = <&rstctrl 19>;
- reset-names = "uartl";
+ clocks = <&sysc 11>;
+
+ resets = <&sysc 19>;
interrupt-parent = <&intc>;
interrupts = <12>;
compatible = "ralink,rt5350-pcm";
reg = <0x2000 0x800>;
- resets = <&rstctrl 11>;
+ resets = <&sysc 11>;
reset-names = "pcm";
interrupt-parent = <&intc>;
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
- resets = <&rstctrl 14>;
+ resets = <&sysc 14>;
reset-names = "dma";
interrupt-parent = <&intc>;
};
};
- rstctrl: rstctrl {
- compatible = "ralink,rt5350-reset", "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
usbphy: usbphy {
compatible = "ralink,rt3352-usbphy";
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
- resets = <&rstctrl 22 &rstctrl 25>;
+ resets = <&sysc 22>, <&sysc 25>;
reset-names = "host", "device";
- clocks = <&clkctrl 18>;
- clock-names = "host";
};
ethernet: ethernet@10100000 {
compatible = "ralink,rt5350-eth";
reg = <0x10100000 0x10000>;
- resets = <&rstctrl 21>;
+ clocks = <&sysc 12>;
+
+ resets = <&sysc 21>;
reset-names = "fe";
interrupt-parent = <&cpuintc>;
compatible = "ralink,rt5350-esw", "ralink,rt3050-esw";
reg = <0x10110000 0x8000>;
- resets = <&rstctrl 23 &rstctrl 24>;
+ resets = <&sysc 23>, <&sysc 24>;
reset-names = "esw", "ephy";
interrupt-parent = <&intc>;
compatible = "ralink,rt5350-wmac", "ralink,rt2880-wmac";
reg = <0x10180000 0x40000>;
+ clocks = <&sysc 13>;
+
interrupt-parent = <&cpuintc>;
interrupts = <6>;
CONFIG_CEVT_SYSTICK_QUIRK=y
CONFIG_CLKEVT_RT3352=y
CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_MTMIPS=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_BOOL=y
CONFIG_CEVT_SYSTICK_QUIRK=y
CONFIG_CLKEVT_RT3352=y
CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_MTMIPS=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_BOOL=y
--- /dev/null
+From 612616e6381929e7f9e303f8b8ad3655cc101516 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:33 +0200
+Subject: [PATCH 1/9] dt-bindings: clock: add mtmips SoCs system controller
+
+Adds device tree binding documentation for system controller node present
+in Mediatek MIPS and Ralink SOCs. This node is a clock and reset provider
+for the rest of the world. This covers RT2880, RT3050, RT3052, RT3350,
+RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ .../bindings/clock/mediatek,mtmips-sysc.yaml | 64 ++++++++++++++++++++++
+ 1 file changed, 64 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
+@@ -0,0 +1,64 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MTMIPS SoCs System Controller
++
++maintainers:
++ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
++
++description: |
++ MediaTek MIPS and Ralink SoCs provides a system controller to allow
++ to access to system control registers. These registers include clock
++ and reset related ones so this node is both clock and reset provider
++ for the rest of the world.
++
++ These SoCs have an XTAL from where the cpu clock is
++ provided as well as derived clocks for the bus and the peripherals.
++
++properties:
++ compatible:
++ items:
++ - enum:
++ - ralink,mt7620-sysc
++ - ralink,mt7628-sysc
++ - ralink,mt7688-sysc
++ - ralink,rt2880-sysc
++ - ralink,rt3050-sysc
++ - ralink,rt3052-sysc
++ - ralink,rt3352-sysc
++ - ralink,rt3883-sysc
++ - ralink,rt5350-sysc
++ - const: syscon
++
++ reg:
++ maxItems: 1
++
++ '#clock-cells':
++ description:
++ The first cell indicates the clock number.
++ const: 1
++
++ '#reset-cells':
++ description:
++ The first cell indicates the reset bit within the register.
++ const: 1
++
++required:
++ - compatible
++ - reg
++ - '#clock-cells'
++ - '#reset-cells'
++
++additionalProperties: false
++
++examples:
++ - |
++ syscon@0 {
++ compatible = "ralink,rt5350-sysc", "syscon";
++ reg = <0x0 0x100>;
++ #clock-cells = <1>;
++ #reset-cells = <1>;
++ };
--- /dev/null
+From 6f3b15586eef736831abe6a14f2a6906bc0dc074 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:34 +0200
+Subject: [PATCH 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs
+
+Until now, clock related code for old ralink SoCs was based in fixed clocks
+using 'clk_register_fixed_rate' and 'clkdev_create' directly doing in code
+and not using device tree at all for their definition. Including this driver
+is an effort to be able to define proper clocks using device tree and also
+cleaning all the clock and reset related code from 'arch/mips/ralink' dir.
+This clock and reset driver covers all the ralink SoCs but MT7621 which is
+the newest and provides gating and some differences that make it different
+from its predecesors. It has its own driver since some time ago. The ralink
+SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883,
+RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver has
+been extracted from 'arch/mips/ralink' and cleanly put using kernel clock
+driver APIs. The clock plans for this SoCs only talks about relation between
+CPU frequency and BUS frequency. This relation is different depending on the
+particular SoC. CPU clock is derived from XTAL frequencies.
+
+Depending on the SoC we have the following frequencies:
+* RT2880 SoC:
+ - XTAL: 40 MHz.
+ - CPU: 250, 266, 280 or 300 MHz.
+ - BUS: CPU / 2 MHz.
+* RT3050, RT3052, RT3350:
+ - XTAL: 40 MHz.
+ - CPU: 320 or 384 MHz.
+ - BUS: CPU / 3 MHz.
+* RT3352:
+ - XTAL: 40 MHz.
+ - CPU: 384 or 400 MHz.
+ - BUS: CPU / 3 MHz.
+ - PERIPH: 40 MHz.
+* RT3383:
+ - XTAL: 40 MHz.
+ - CPU: 250, 384, 480 or 500 MHz.
+ - BUS: Depends on RAM Type and CPU:
+ + RAM DDR2: 125. ELSE 83 MHz.
+ + RAM DDR2: 128. ELSE 96 MHz.
+ + RAM DDR2: 160. ELSE 120 MHz.
+ + RAM DDR2: 166. ELSE 125 MHz.
+* RT5350:
+ - XTAL: 40 MHz.
+ - CPU: 300, 320 or 360 MHz.
+ - BUS: CPU / 3, CPU / 4, CPU / 3 MHz.
+ - PERIPH: 40 MHz.
+* MT7628 and MT7688:
+ - XTAL: 20 MHz or 40 MHz.
+ - CPU: 575 or 580 MHz.
+ - BUS: CPU / 3.
+ - PCMI2S: 480 MHz.
+ - PERIPH: 40 MHz.
+* MT7620:
+ - XTAL: 20 MHz or 40 MHz.
+ - PLL: XTAL, 480, 600 MHz.
+ - CPU: depends on PLL and some mult and dividers.
+ - BUS: depends on PLL and some mult and dividers.
+ - PERIPH: 40 or XTAL MHz.
+
+MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of
+register reads and predividers. To derive CPU and BUS frequencies in the
+MT7620 SoC 'mt7620_calc_rate()' helper is used.
+
+In the case XTAL can have different frequencies and we need a different
+clock frequency for peripherals 'periph' clock in introduced.
+
+The rest of the peripherals present in the SoC just follow their parent
+frequencies.
+
+With this information the clk driver will provide all the clock and reset
+functionality from a set of hardcoded clocks allowing to define a nice
+device tree without fixed clocks.
+
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ drivers/clk/ralink/Kconfig | 7 +
+ drivers/clk/ralink/Makefile | 1 +
+ drivers/clk/ralink/clk-mtmips.c | 1115 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 1123 insertions(+)
+ create mode 100644 drivers/clk/ralink/clk-mtmips.c
+
+--- a/drivers/clk/ralink/Kconfig
++++ b/drivers/clk/ralink/Kconfig
+@@ -9,3 +9,10 @@ config CLK_MT7621
+ select MFD_SYSCON
+ help
+ This driver supports MediaTek MT7621 basic clocks.
++
++config CLK_MTMIPS
++ bool "Clock driver for MTMIPS SoCs"
++ depends on SOC_RT305X || SOC_RT288X || SOC_RT3883 || SOC_MT7620 || COMPILE_TEST
++ select MFD_SYSCON
++ help
++ This driver supports MTMIPS basic clocks.
+--- a/drivers/clk/ralink/Makefile
++++ b/drivers/clk/ralink/Makefile
+@@ -1,2 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
++obj-$(CONFIG_CLK_MTMIPS) += clk-mtmips.o
+--- /dev/null
++++ b/drivers/clk/ralink/clk-mtmips.c
+@@ -0,0 +1,1115 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * MTMIPS SoCs Clock Driver
++ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
++ */
++
++#include <linux/bitops.h>
++#include <linux/clk-provider.h>
++#include <linux/mfd/syscon.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/reset-controller.h>
++#include <linux/slab.h>
++
++/* Configuration registers */
++#define SYSC_REG_SYSTEM_CONFIG 0x10
++#define SYSC_REG_CLKCFG0 0x2c
++#define SYSC_REG_RESET_CTRL 0x34
++#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
++#define SYSC_REG_CPLL_CONFIG0 0x54
++#define SYSC_REG_CPLL_CONFIG1 0x58
++
++/* RT2880 SoC */
++#define RT2880_CONFIG_CPUCLK_SHIFT 20
++#define RT2880_CONFIG_CPUCLK_MASK 0x3
++#define RT2880_CONFIG_CPUCLK_250 0x0
++#define RT2880_CONFIG_CPUCLK_266 0x1
++#define RT2880_CONFIG_CPUCLK_280 0x2
++#define RT2880_CONFIG_CPUCLK_300 0x3
++
++/* RT305X SoC */
++#define RT305X_SYSCFG_CPUCLK_SHIFT 18
++#define RT305X_SYSCFG_CPUCLK_MASK 0x1
++#define RT305X_SYSCFG_CPUCLK_LOW 0x0
++#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
++
++/* RT3352 SoC */
++#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
++#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
++#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
++#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
++
++/* RT3383 SoC */
++#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
++#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
++#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
++#define RT3883_SYSCFG0_CPUCLK_250 0x0
++#define RT3883_SYSCFG0_CPUCLK_384 0x1
++#define RT3883_SYSCFG0_CPUCLK_480 0x2
++#define RT3883_SYSCFG0_CPUCLK_500 0x3
++
++/* RT5350 SoC */
++#define RT5350_CLKCFG0_XTAL_SEL BIT(20)
++#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
++#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
++#define RT5350_SYSCFG0_CPUCLK_360 0x0
++#define RT5350_SYSCFG0_CPUCLK_320 0x2
++#define RT5350_SYSCFG0_CPUCLK_300 0x3
++
++/* MT7620 and MT76x8 SoCs */
++#define MT7620_XTAL_FREQ_SEL BIT(6)
++#define CPLL_CFG0_SW_CFG BIT(31)
++#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
++#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
++#define CPLL_CFG0_LC_CURFCK BIT(15)
++#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
++#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
++#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
++#define CPLL_CFG1_CPU_AUX1 BIT(25)
++#define CPLL_CFG1_CPU_AUX0 BIT(24)
++#define CLKCFG0_PERI_CLK_SEL BIT(4)
++#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
++#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
++#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
++#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
++#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
++#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
++#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
++#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
++#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
++#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
++#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
++#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
++#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
++#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
++#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
++
++/* clock scaling */
++#define CLKCFG_FDIV_MASK 0x1f00
++#define CLKCFG_FDIV_USB_VAL 0x0300
++#define CLKCFG_FFRAC_MASK 0x001f
++#define CLKCFG_FFRAC_USB_VAL 0x0003
++
++struct mtmips_clk;
++struct mtmips_clk_fixed;
++struct mtmips_clk_factor;
++
++struct mtmips_clk_data {
++ struct mtmips_clk *clk_base;
++ size_t num_clk_base;
++ struct mtmips_clk_fixed *clk_fixed;
++ size_t num_clk_fixed;
++ struct mtmips_clk_factor *clk_factor;
++ size_t num_clk_factor;
++ struct mtmips_clk *clk_periph;
++ size_t num_clk_periph;
++};
++
++struct mtmips_clk_priv {
++ struct regmap *sysc;
++ const struct mtmips_clk_data *data;
++};
++
++struct mtmips_clk {
++ struct clk_hw hw;
++ struct mtmips_clk_priv *priv;
++};
++
++struct mtmips_clk_fixed {
++ const char *name;
++ const char *parent;
++ unsigned long rate;
++ struct clk_hw *hw;
++};
++
++struct mtmips_clk_factor {
++ const char *name;
++ const char *parent;
++ int mult;
++ int div;
++ unsigned long flags;
++ struct clk_hw *hw;
++};
++
++static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ return parent_rate;
++}
++
++static const struct clk_ops mtmips_periph_clk_ops = {
++ .recalc_rate = mtmips_pherip_clk_rate,
++};
++
++#define CLK_PERIPH(_name, _parent) { \
++ .init = &(const struct clk_init_data) { \
++ .name = _name, \
++ .ops = &mtmips_periph_clk_ops, \
++ .parent_data = &(const struct clk_parent_data) {\
++ .name = _parent, \
++ .fw_name = _parent \
++ }, \
++ .num_parents = 1, \
++ /* \
++ * There are drivers for these SoCs that are \
++ * older than clock driver and are not prepared \
++ * for the clock. We don't want the kernel to \
++ * disable anything so we add CLK_IS_CRITICAL \
++ * flag here. \
++ */ \
++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL \
++ }, \
++}
++
++static struct mtmips_clk rt2880_pherip_clks[] = {
++ { CLK_PERIPH("300100.timer", "bus") },
++ { CLK_PERIPH("300120.watchdog", "bus") },
++ { CLK_PERIPH("300500.uart", "bus") },
++ { CLK_PERIPH("300900.i2c", "bus") },
++ { CLK_PERIPH("300c00.uartlite", "bus") },
++ { CLK_PERIPH("400000.ethernet", "bus") },
++ { CLK_PERIPH("480000.wmac", "xtal") }
++};
++
++static struct mtmips_clk rt305x_pherip_clks[] = {
++ { CLK_PERIPH("10000100.timer", "bus") },
++ { CLK_PERIPH("10000120.watchdog", "bus") },
++ { CLK_PERIPH("10000500.uart", "bus") },
++ { CLK_PERIPH("10000900.i2c", "bus") },
++ { CLK_PERIPH("10000a00.i2s", "bus") },
++ { CLK_PERIPH("10000b00.spi", "bus") },
++ { CLK_PERIPH("10000b40.spi", "bus") },
++ { CLK_PERIPH("10000c00.uartlite", "bus") },
++ { CLK_PERIPH("10100000.ethernet", "bus") },
++ { CLK_PERIPH("10180000.wmac", "xtal") }
++};
++
++static struct mtmips_clk rt5350_pherip_clks[] = {
++ { CLK_PERIPH("10000100.timer", "bus") },
++ { CLK_PERIPH("10000120.watchdog", "bus") },
++ { CLK_PERIPH("10000500.uart", "periph") },
++ { CLK_PERIPH("10000900.i2c", "periph") },
++ { CLK_PERIPH("10000a00.i2s", "periph") },
++ { CLK_PERIPH("10000b00.spi", "bus") },
++ { CLK_PERIPH("10000b40.spi", "bus") },
++ { CLK_PERIPH("10000c00.uartlite", "periph") },
++ { CLK_PERIPH("10100000.ethernet", "bus") },
++ { CLK_PERIPH("10180000.wmac", "xtal") }
++};
++
++static struct mtmips_clk mt7620_pherip_clks[] = {
++ { CLK_PERIPH("10000100.timer", "periph") },
++ { CLK_PERIPH("10000120.watchdog", "periph") },
++ { CLK_PERIPH("10000500.uart", "periph") },
++ { CLK_PERIPH("10000900.i2c", "periph") },
++ { CLK_PERIPH("10000a00.i2s", "periph") },
++ { CLK_PERIPH("10000b00.spi", "bus") },
++ { CLK_PERIPH("10000b40.spi", "bus") },
++ { CLK_PERIPH("10000c00.uartlite", "periph") },
++ { CLK_PERIPH("10180000.wmac", "xtal") }
++};
++
++static struct mtmips_clk mt76x8_pherip_clks[] = {
++ { CLK_PERIPH("10000100.timer", "periph") },
++ { CLK_PERIPH("10000120.watchdog", "periph") },
++ { CLK_PERIPH("10000900.i2c", "periph") },
++ { CLK_PERIPH("10000a00.i2s", "pcmi2s") },
++ { CLK_PERIPH("10000b00.spi", "bus") },
++ { CLK_PERIPH("10000b40.spi", "bus") },
++ { CLK_PERIPH("10000c00.uart0", "periph") },
++ { CLK_PERIPH("10000d00.uart1", "periph") },
++ { CLK_PERIPH("10000e00.uart2", "periph") },
++ { CLK_PERIPH("10300000.wmac", "xtal") }
++};
++
++static int mtmips_register_pherip_clocks(struct device_node *np,
++ struct clk_hw_onecell_data *clk_data,
++ struct mtmips_clk_priv *priv)
++{
++ struct clk_hw **hws = clk_data->hws;
++ struct mtmips_clk *sclk;
++ size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed +
++ priv->data->num_clk_factor;
++ int ret, i;
++
++ for (i = 0; i < priv->data->num_clk_periph; i++) {
++ int idx = idx_start + i;
++
++ sclk = &priv->data->clk_periph[i];
++ ret = of_clk_hw_register(np, &sclk->hw);
++ if (ret) {
++ pr_err("Couldn't register peripheral clock %d\n", idx);
++ goto err_clk_unreg;
++ }
++
++ hws[idx] = &sclk->hw;
++ }
++
++ return 0;
++
++err_clk_unreg:
++ while (--i >= 0) {
++ sclk = &priv->data->clk_periph[i];
++ clk_hw_unregister(&sclk->hw);
++ }
++ return ret;
++}
++
++#define CLK_FIXED(_name, _parent, _rate) \
++ { \
++ .name = _name, \
++ .parent = _parent, \
++ .rate = _rate \
++ }
++
++static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
++ CLK_FIXED("xtal", NULL, 40000000)
++};
++
++static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
++ CLK_FIXED("periph", "xtal", 40000000)
++};
++
++static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
++ CLK_FIXED("pcmi2s", "xtal", 480000000),
++ CLK_FIXED("periph", "xtal", 40000000)
++};
++
++static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data,
++ struct mtmips_clk_priv *priv)
++{
++ struct clk_hw **hws = clk_data->hws;
++ struct mtmips_clk_fixed *sclk;
++ size_t idx_start = priv->data->num_clk_base;
++ int ret, i;
++
++ for (i = 0; i < priv->data->num_clk_fixed; i++) {
++ int idx = idx_start + i;
++
++ sclk = &priv->data->clk_fixed[i];
++ sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name,
++ sclk->parent, 0,
++ sclk->rate);
++ if (IS_ERR(sclk->hw)) {
++ pr_err("Couldn't register fixed clock %d\n", idx);
++ goto err_clk_unreg;
++ }
++
++ hws[idx] = sclk->hw;
++ }
++
++ return 0;
++
++err_clk_unreg:
++ while (--i >= 0) {
++ sclk = &priv->data->clk_fixed[i];
++ clk_hw_unregister_fixed_rate(sclk->hw);
++ }
++ return ret;
++}
++
++#define CLK_FACTOR(_name, _parent, _mult, _div) \
++ { \
++ .name = _name, \
++ .parent = _parent, \
++ .mult = _mult, \
++ .div = _div, \
++ .flags = CLK_SET_RATE_PARENT \
++ }
++
++static struct mtmips_clk_factor rt2880_factor_clocks[] = {
++ CLK_FACTOR("bus", "cpu", 1, 2)
++};
++
++static struct mtmips_clk_factor rt305x_factor_clocks[] = {
++ CLK_FACTOR("bus", "cpu", 1, 3)
++};
++
++static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
++ struct mtmips_clk_priv *priv)
++{
++ struct clk_hw **hws = clk_data->hws;
++ struct mtmips_clk_factor *sclk;
++ size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed;
++ int ret, i;
++
++ for (i = 0; i < priv->data->num_clk_factor; i++) {
++ int idx = idx_start + i;
++
++ sclk = &priv->data->clk_factor[i];
++ sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name,
++ sclk->parent, sclk->flags,
++ sclk->mult, sclk->div);
++ if (IS_ERR(sclk->hw)) {
++ pr_err("Couldn't register factor clock %d\n", idx);
++ goto err_clk_unreg;
++ }
++
++ hws[idx] = sclk->hw;
++ }
++
++ return 0;
++
++err_clk_unreg:
++ while (--i >= 0) {
++ sclk = &priv->data->clk_factor[i];
++ clk_hw_unregister_fixed_factor(sclk->hw);
++ }
++ return ret;
++}
++
++static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw)
++{
++ return container_of(hw, struct mtmips_clk, hw);
++}
++
++static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 val;
++
++ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val);
++ if (!(val & RT5350_CLKCFG0_XTAL_SEL))
++ return 20000000;
++
++ return 40000000;
++}
++
++static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw,
++ unsigned long xtal_clk)
++{
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 t;
++
++ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++ t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK;
++
++ switch (t) {
++ case RT5350_SYSCFG0_CPUCLK_360:
++ return 360000000;
++ case RT5350_SYSCFG0_CPUCLK_320:
++ return 320000000;
++ case RT5350_SYSCFG0_CPUCLK_300:
++ return 300000000;
++ default:
++ BUG();
++ }
++}
++
++static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ if (parent_rate == 320000000)
++ return parent_rate / 4;
++
++ return parent_rate / 3;
++}
++
++static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw,
++ unsigned long xtal_clk)
++{
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 t;
++
++ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++ t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK;
++
++ switch (t) {
++ case RT3352_SYSCFG0_CPUCLK_LOW:
++ return 384000000;
++ case RT3352_SYSCFG0_CPUCLK_HIGH:
++ return 400000000;
++ default:
++ BUG();
++ }
++}
++
++static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw,
++ unsigned long xtal_clk)
++{
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 t;
++
++ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++ t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK;
++
++ switch (t) {
++ case RT305X_SYSCFG_CPUCLK_LOW:
++ return 320000000;
++ case RT305X_SYSCFG_CPUCLK_HIGH:
++ return 384000000;
++ default:
++ BUG();
++ }
++}
++
++static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw,
++ unsigned long xtal_clk)
++{
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 t;
++
++ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++ t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK;
++
++ switch (t) {
++ case RT3883_SYSCFG0_CPUCLK_250:
++ return 250000000;
++ case RT3883_SYSCFG0_CPUCLK_384:
++ return 384000000;
++ case RT3883_SYSCFG0_CPUCLK_480:
++ return 480000000;
++ case RT3883_SYSCFG0_CPUCLK_500:
++ return 500000000;
++ default:
++ BUG();
++ }
++}
++
++static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 ddr2;
++ u32 t;
++
++ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++ ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
++
++ switch (parent_rate) {
++ case 250000000:
++ return (ddr2) ? 125000000 : 83000000;
++ case 384000000:
++ return (ddr2) ? 128000000 : 96000000;
++ case 480000000:
++ return (ddr2) ? 160000000 : 120000000;
++ case 500000000:
++ return (ddr2) ? 166000000 : 125000000;
++ default:
++ WARN_ON_ONCE(parent_rate == 0);
++ return parent_rate / 4;
++ }
++}
++
++static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw,
++ unsigned long xtal_clk)
++{
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 t;
++
++ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++ t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK;
++
++ switch (t) {
++ case RT2880_CONFIG_CPUCLK_250:
++ return 250000000;
++ case RT2880_CONFIG_CPUCLK_266:
++ return 266000000;
++ case RT2880_CONFIG_CPUCLK_280:
++ return 280000000;
++ case RT2880_CONFIG_CPUCLK_300:
++ return 300000000;
++ default:
++ BUG();
++ }
++}
++
++static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
++{
++ u64 t;
++
++ t = ref_rate;
++ t *= mul;
++ t = div_u64(t, div);
++
++ return t;
++}
++
++static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ static const u32 clk_divider[] = { 2, 3, 4, 8 };
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ unsigned long cpu_pll;
++ u32 t;
++ u32 mul;
++ u32 div;
++
++ regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t);
++ if (t & CPLL_CFG0_BYPASS_REF_CLK) {
++ cpu_pll = parent_rate;
++ } else if ((t & CPLL_CFG0_SW_CFG) == 0) {
++ cpu_pll = 600000000;
++ } else {
++ mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
++ CPLL_CFG0_PLL_MULT_RATIO_MASK;
++ mul += 24;
++ if (t & CPLL_CFG0_LC_CURFCK)
++ mul *= 2;
++
++ div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
++ CPLL_CFG0_PLL_DIV_RATIO_MASK;
++
++ WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider));
++
++ cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]);
++ }
++
++ regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t);
++ if (t & CPLL_CFG1_CPU_AUX1)
++ return parent_rate;
++
++ if (t & CPLL_CFG1_CPU_AUX0)
++ return 480000000;
++
++ return cpu_pll;
++}
++
++static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 t;
++ u32 mul;
++ u32 div;
++
++ regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
++ mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
++ div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
++ CPU_SYS_CLKCFG_CPU_FDIV_MASK;
++
++ return mt7620_calc_rate(parent_rate, mul, div);
++}
++
++static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ static const u32 ocp_dividers[16] = {
++ [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
++ [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
++ [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
++ [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
++ [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
++ };
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 t;
++ u32 ocp_ratio;
++ u32 div;
++
++ regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
++ ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
++ CPU_SYS_CLKCFG_OCP_RATIO_MASK;
++
++ if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers)))
++ return parent_rate;
++
++ div = ocp_dividers[ocp_ratio];
++
++ if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
++ return parent_rate;
++
++ return parent_rate / div;
++}
++
++static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 t;
++
++ regmap_read(sysc, SYSC_REG_CLKCFG0, &t);
++ if (t & CLKCFG0_PERI_CLK_SEL)
++ return parent_rate;
++
++ return 40000000;
++}
++
++static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct mtmips_clk *clk = to_mtmips_clk(hw);
++ struct regmap *sysc = clk->priv->sysc;
++ u32 t;
++
++ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
++ if (t & MT7620_XTAL_FREQ_SEL)
++ return 40000000;
++
++ return 20000000;
++}
++
++static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw,
++ unsigned long xtal_clk)
++{
++ if (xtal_clk == 40000000)
++ return 580000000;
++
++ return 575000000;
++}
++
++#define CLK_BASE(_name, _parent, _recalc) { \
++ .init = &(const struct clk_init_data) { \
++ .name = _name, \
++ .ops = &(const struct clk_ops) { \
++ .recalc_rate = _recalc, \
++ }, \
++ .parent_data = &(const struct clk_parent_data) { \
++ .name = _parent, \
++ .fw_name = _parent \
++ }, \
++ .num_parents = _parent ? 1 : 0 \
++ }, \
++}
++
++static struct mtmips_clk rt2880_clks_base[] = {
++ { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
++};
++
++static struct mtmips_clk rt305x_clks_base[] = {
++ { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
++};
++
++static struct mtmips_clk rt3352_clks_base[] = {
++ { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
++ { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
++};
++
++static struct mtmips_clk rt3883_clks_base[] = {
++ { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
++ { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
++};
++
++static struct mtmips_clk rt5350_clks_base[] = {
++ { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
++ { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
++ { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) }
++};
++
++static struct mtmips_clk mt7620_clks_base[] = {
++ { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
++ { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
++ { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
++ { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
++ { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) }
++};
++
++static struct mtmips_clk mt76x8_clks_base[] = {
++ { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
++ { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) }
++};
++
++static int mtmips_register_clocks(struct device_node *np,
++ struct clk_hw_onecell_data *clk_data,
++ struct mtmips_clk_priv *priv)
++{
++ struct clk_hw **hws = clk_data->hws;
++ struct mtmips_clk *sclk;
++ int ret, i;
++
++ for (i = 0; i < priv->data->num_clk_base; i++) {
++ sclk = &priv->data->clk_base[i];
++ sclk->priv = priv;
++ ret = of_clk_hw_register(np, &sclk->hw);
++ if (ret) {
++ pr_err("Couldn't register top clock %i\n", i);
++ goto err_clk_unreg;
++ }
++
++ hws[i] = &sclk->hw;
++ }
++
++ return 0;
++
++err_clk_unreg:
++ while (--i >= 0) {
++ sclk = &priv->data->clk_base[i];
++ clk_hw_unregister(&sclk->hw);
++ }
++ return ret;
++}
++
++static const struct mtmips_clk_data rt2880_clk_data = {
++ .clk_base = rt2880_clks_base,
++ .num_clk_base = ARRAY_SIZE(rt2880_clks_base),
++ .clk_fixed = rt305x_fixed_clocks,
++ .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
++ .clk_factor = rt2880_factor_clocks,
++ .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
++ .clk_periph = rt2880_pherip_clks,
++ .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks),
++};
++
++static const struct mtmips_clk_data rt305x_clk_data = {
++ .clk_base = rt305x_clks_base,
++ .num_clk_base = ARRAY_SIZE(rt305x_clks_base),
++ .clk_fixed = rt305x_fixed_clocks,
++ .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
++ .clk_factor = rt305x_factor_clocks,
++ .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
++ .clk_periph = rt305x_pherip_clks,
++ .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks),
++};
++
++static const struct mtmips_clk_data rt3352_clk_data = {
++ .clk_base = rt3352_clks_base,
++ .num_clk_base = ARRAY_SIZE(rt3352_clks_base),
++ .clk_fixed = rt3352_fixed_clocks,
++ .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
++ .clk_factor = rt305x_factor_clocks,
++ .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
++ .clk_periph = rt5350_pherip_clks,
++ .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
++};
++
++static const struct mtmips_clk_data rt3883_clk_data = {
++ .clk_base = rt3883_clks_base,
++ .num_clk_base = ARRAY_SIZE(rt3883_clks_base),
++ .clk_fixed = rt305x_fixed_clocks,
++ .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
++ .clk_factor = NULL,
++ .num_clk_factor = 0,
++ .clk_periph = rt5350_pherip_clks,
++ .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
++};
++
++static const struct mtmips_clk_data rt5350_clk_data = {
++ .clk_base = rt5350_clks_base,
++ .num_clk_base = ARRAY_SIZE(rt5350_clks_base),
++ .clk_fixed = rt3352_fixed_clocks,
++ .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
++ .clk_factor = NULL,
++ .num_clk_factor = 0,
++ .clk_periph = rt5350_pherip_clks,
++ .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
++};
++
++static const struct mtmips_clk_data mt7620_clk_data = {
++ .clk_base = mt7620_clks_base,
++ .num_clk_base = ARRAY_SIZE(mt7620_clks_base),
++ .clk_fixed = NULL,
++ .num_clk_fixed = 0,
++ .clk_factor = NULL,
++ .num_clk_factor = 0,
++ .clk_periph = mt7620_pherip_clks,
++ .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
++};
++
++static const struct mtmips_clk_data mt76x8_clk_data = {
++ .clk_base = mt76x8_clks_base,
++ .num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
++ .clk_fixed = mt76x8_fixed_clocks,
++ .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
++ .clk_factor = rt305x_factor_clocks,
++ .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
++ .clk_periph = mt76x8_pherip_clks,
++ .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
++};
++
++static const struct of_device_id mtmips_of_match[] = {
++ {
++ .compatible = "ralink,rt2880-sysc",
++ .data = &rt2880_clk_data,
++ },
++ {
++ .compatible = "ralink,rt3050-sysc",
++ .data = &rt305x_clk_data,
++ },
++ {
++ .compatible = "ralink,rt3052-sysc",
++ .data = &rt305x_clk_data,
++ },
++ {
++ .compatible = "ralink,rt3352-sysc",
++ .data = &rt3352_clk_data,
++ },
++ {
++ .compatible = "ralink,rt3883-sysc",
++ .data = &rt3883_clk_data,
++ },
++ {
++ .compatible = "ralink,rt5350-sysc",
++ .data = &rt5350_clk_data,
++ },
++ {
++ .compatible = "ralink,mt7620-sysc",
++ .data = &mt7620_clk_data,
++ },
++ {
++ .compatible = "ralink,mt7628-sysc",
++ .data = &mt76x8_clk_data,
++ },
++ {
++ .compatible = "ralink,mt7688-sysc",
++ .data = &mt76x8_clk_data,
++ },
++ {}
++};
++
++static void __init mtmips_clk_regs_init(struct device_node *node,
++ struct mtmips_clk_priv *priv)
++{
++ u32 t;
++
++ if (!of_device_is_compatible(node, "ralink,mt7620-sysc"))
++ return;
++
++ /*
++ * When the CPU goes into sleep mode, the BUS
++ * clock will be too low for USB to function properly.
++ * Adjust the busses fractional divider to fix this
++ */
++ regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
++ t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
++ t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
++ regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t);
++}
++
++static void __init mtmips_clk_init(struct device_node *node)
++{
++ const struct of_device_id *match;
++ const struct mtmips_clk_data *data;
++ struct mtmips_clk_priv *priv;
++ struct clk_hw_onecell_data *clk_data;
++ int ret, i, count;
++
++ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return;
++
++ priv->sysc = syscon_node_to_regmap(node);
++ if (IS_ERR(priv->sysc)) {
++ pr_err("Could not get sysc syscon regmap\n");
++ goto free_clk_priv;
++ }
++
++ mtmips_clk_regs_init(node, priv);
++
++ match = of_match_node(mtmips_of_match, node);
++ if (WARN_ON(!match))
++ return;
++
++ data = match->data;
++ priv->data = data;
++ count = priv->data->num_clk_base + priv->data->num_clk_fixed +
++ priv->data->num_clk_factor + priv->data->num_clk_periph;
++ clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
++ if (!clk_data)
++ goto free_clk_priv;
++
++ ret = mtmips_register_clocks(node, clk_data, priv);
++ if (ret) {
++ pr_err("Couldn't register top clocks\n");
++ goto free_clk_data;
++ }
++
++ ret = mtmips_register_fixed_clocks(clk_data, priv);
++ if (ret) {
++ pr_err("Couldn't register fixed clocks\n");
++ goto unreg_clk_top;
++ }
++
++ ret = mtmips_register_factor_clocks(clk_data, priv);
++ if (ret) {
++ pr_err("Couldn't register factor clocks\n");
++ goto unreg_clk_fixed;
++ }
++
++ ret = mtmips_register_pherip_clocks(node, clk_data, priv);
++ if (ret) {
++ pr_err("Couldn't register peripheral clocks\n");
++ goto unreg_clk_factor;
++ }
++
++ clk_data->num = count;
++
++ ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++ if (ret) {
++ pr_err("Couldn't add clk hw provider\n");
++ goto unreg_clk_periph;
++ }
++
++ return;
++
++unreg_clk_periph:
++ for (i = 0; i < priv->data->num_clk_periph; i++) {
++ struct mtmips_clk *sclk = &priv->data->clk_periph[i];
++
++ clk_hw_unregister(&sclk->hw);
++ }
++
++unreg_clk_factor:
++ for (i = 0; i < priv->data->num_clk_factor; i++) {
++ struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i];
++
++ clk_hw_unregister_fixed_factor(sclk->hw);
++ }
++
++unreg_clk_fixed:
++ for (i = 0; i < priv->data->num_clk_fixed; i++) {
++ struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i];
++
++ clk_hw_unregister_fixed_rate(sclk->hw);
++ }
++
++unreg_clk_top:
++ for (i = 0; i < priv->data->num_clk_base; i++) {
++ struct mtmips_clk *sclk = &priv->data->clk_base[i];
++
++ clk_hw_unregister(&sclk->hw);
++ }
++
++free_clk_data:
++ kfree(clk_data);
++
++free_clk_priv:
++ kfree(priv);
++}
++CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init);
++CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init);
++
++struct mtmips_rst {
++ struct reset_controller_dev rcdev;
++ struct regmap *sysc;
++};
++
++static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev)
++{
++ return container_of(dev, struct mtmips_rst, rcdev);
++}
++
++static int mtmips_assert_device(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ struct mtmips_rst *data = to_mtmips_rst(rcdev);
++ struct regmap *sysc = data->sysc;
++
++ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
++}
++
++static int mtmips_deassert_device(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ struct mtmips_rst *data = to_mtmips_rst(rcdev);
++ struct regmap *sysc = data->sysc;
++
++ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
++}
++
++static int mtmips_reset_device(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ int ret;
++
++ ret = mtmips_assert_device(rcdev, id);
++ if (ret < 0)
++ return ret;
++
++ return mtmips_deassert_device(rcdev, id);
++}
++
++static int mtmips_rst_xlate(struct reset_controller_dev *rcdev,
++ const struct of_phandle_args *reset_spec)
++{
++ unsigned long id = reset_spec->args[0];
++
++ if (id == 0 || id >= rcdev->nr_resets)
++ return -EINVAL;
++
++ return id;
++}
++
++static const struct reset_control_ops reset_ops = {
++ .reset = mtmips_reset_device,
++ .assert = mtmips_assert_device,
++ .deassert = mtmips_deassert_device
++};
++
++static int mtmips_reset_init(struct device *dev, struct regmap *sysc)
++{
++ struct mtmips_rst *rst_data;
++
++ rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
++ if (!rst_data)
++ return -ENOMEM;
++
++ rst_data->sysc = sysc;
++ rst_data->rcdev.ops = &reset_ops;
++ rst_data->rcdev.owner = THIS_MODULE;
++ rst_data->rcdev.nr_resets = 32;
++ rst_data->rcdev.of_reset_n_cells = 1;
++ rst_data->rcdev.of_xlate = mtmips_rst_xlate;
++ rst_data->rcdev.of_node = dev_of_node(dev);
++
++ return devm_reset_controller_register(dev, &rst_data->rcdev);
++}
++
++static int mtmips_clk_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct device *dev = &pdev->dev;
++ struct mtmips_clk_priv *priv;
++ int ret;
++
++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ priv->sysc = syscon_node_to_regmap(np);
++ if (IS_ERR(priv->sysc))
++ return dev_err_probe(dev, PTR_ERR(priv->sysc),
++ "Could not get sysc syscon regmap\n");
++
++ ret = mtmips_reset_init(dev, priv->sysc);
++ if (ret)
++ return dev_err_probe(dev, ret, "Could not init reset controller\n");
++
++ return 0;
++}
++
++static const struct of_device_id mtmips_clk_of_match[] = {
++ { .compatible = "ralink,rt2880-reset" },
++ { .compatible = "ralink,rt2880-sysc" },
++ { .compatible = "ralink,rt3050-sysc" },
++ { .compatible = "ralink,rt3052-sysc" },
++ { .compatible = "ralink,rt3352-sysc" },
++ { .compatible = "ralink,rt3883-sysc" },
++ { .compatible = "ralink,rt5350-sysc" },
++ { .compatible = "ralink,mt7620-sysc" },
++ { .compatible = "ralink,mt7628-sysc" },
++ { .compatible = "ralink,mt7688-sysc" },
++ {}
++};
++
++static struct platform_driver mtmips_clk_driver = {
++ .probe = mtmips_clk_probe,
++ .driver = {
++ .name = "mtmips-clk",
++ .of_match_table = mtmips_clk_of_match,
++ },
++};
++
++static int __init mtmips_clk_reset_init(void)
++{
++ return platform_driver_register(&mtmips_clk_driver);
++}
++arch_initcall(mtmips_clk_reset_init);
--- /dev/null
+From ffcdf47379eae86dc8f8f02c62994dacf2c9038e Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:35 +0200
+Subject: [PATCH 3/9] mips: ralink: rt288x: remove clock related code
+
+A properly clock driver for ralink SoCs has been added. Hence there is no
+need to have clock related code in 'arch/mips/ralink' folder anymore.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mach-ralink/rt288x.h | 10 ----------
+ arch/mips/ralink/rt288x.c | 31 ------------------------------
+ 2 files changed, 41 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/rt288x.h
++++ b/arch/mips/include/asm/mach-ralink/rt288x.h
+@@ -17,7 +17,6 @@
+ #define SYSC_REG_CHIP_NAME1 0x04
+ #define SYSC_REG_CHIP_ID 0x0c
+ #define SYSC_REG_SYSTEM_CONFIG 0x10
+-#define SYSC_REG_CLKCFG 0x30
+
+ #define RT2880_CHIP_NAME0 0x38325452
+ #define RT2880_CHIP_NAME1 0x20203038
+@@ -26,15 +25,6 @@
+ #define CHIP_ID_ID_SHIFT 8
+ #define CHIP_ID_REV_MASK 0xff
+
+-#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
+-#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
+-#define SYSTEM_CONFIG_CPUCLK_250 0x0
+-#define SYSTEM_CONFIG_CPUCLK_266 0x1
+-#define SYSTEM_CONFIG_CPUCLK_280 0x2
+-#define SYSTEM_CONFIG_CPUCLK_300 0x3
+-
+-#define CLKCFG_SRAM_CS_N_WDT BIT(9)
+-
+ #define RT2880_SDRAM_BASE 0x08000000
+ #define RT2880_MEM_SIZE_MIN 2
+ #define RT2880_MEM_SIZE_MAX 128
+--- a/arch/mips/ralink/rt288x.c
++++ b/arch/mips/ralink/rt288x.c
+@@ -17,37 +17,6 @@
+
+ #include "common.h"
+
+-void __init ralink_clk_init(void)
+-{
+- unsigned long cpu_rate, wmac_rate = 40000000;
+- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+- t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
+-
+- switch (t) {
+- case SYSTEM_CONFIG_CPUCLK_250:
+- cpu_rate = 250000000;
+- break;
+- case SYSTEM_CONFIG_CPUCLK_266:
+- cpu_rate = 266666667;
+- break;
+- case SYSTEM_CONFIG_CPUCLK_280:
+- cpu_rate = 280000000;
+- break;
+- case SYSTEM_CONFIG_CPUCLK_300:
+- cpu_rate = 300000000;
+- break;
+- }
+-
+- ralink_clk_add("cpu", cpu_rate);
+- ralink_clk_add("300100.timer", cpu_rate / 2);
+- ralink_clk_add("300120.watchdog", cpu_rate / 2);
+- ralink_clk_add("300500.uart", cpu_rate / 2);
+- ralink_clk_add("300900.i2c", cpu_rate / 2);
+- ralink_clk_add("300c00.uartlite", cpu_rate / 2);
+- ralink_clk_add("400000.ethernet", cpu_rate / 2);
+- ralink_clk_add("480000.wmac", wmac_rate);
+-}
+-
+ void __init ralink_of_remap(void)
+ {
+ rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
--- /dev/null
+From daf73c70f69386fb15960526772ef584a4efcaf2 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:36 +0200
+Subject: [PATCH 4/9] mips: ralink: rt305x: remove clock related code
+
+A properly clock driver for ralink SoCs has been added. Hence there is no
+need to have clock related code in 'arch/mips/ralink' folder anymore.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mach-ralink/rt305x.h | 21 --------
+ arch/mips/ralink/rt305x.c | 78 ------------------------------
+ 2 files changed, 99 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/rt305x.h
++++ b/arch/mips/include/asm/mach-ralink/rt305x.h
+@@ -66,26 +66,9 @@ static inline int soc_is_rt5350(void)
+ #define CHIP_ID_ID_SHIFT 8
+ #define CHIP_ID_REV_MASK 0xff
+
+-#define RT305X_SYSCFG_CPUCLK_SHIFT 18
+-#define RT305X_SYSCFG_CPUCLK_MASK 0x1
+-#define RT305X_SYSCFG_CPUCLK_LOW 0x0
+-#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
+-
+ #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
+-#define RT305X_SYSCFG_CPUCLK_MASK 0x1
+ #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
+
+-#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
+-#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
+-#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
+-#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
+-
+-#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
+-#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
+-#define RT5350_SYSCFG0_CPUCLK_360 0x0
+-#define RT5350_SYSCFG0_CPUCLK_320 0x2
+-#define RT5350_SYSCFG0_CPUCLK_300 0x3
+-
+ #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
+ #define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
+ #define RT5350_SYSCFG0_DRAM_SIZE_2M 0
+@@ -116,13 +99,9 @@ static inline int soc_is_rt5350(void)
+
+ #define RT3352_SYSC_REG_SYSCFG0 0x010
+ #define RT3352_SYSC_REG_SYSCFG1 0x014
+-#define RT3352_SYSC_REG_CLKCFG1 0x030
+ #define RT3352_SYSC_REG_RSTCTRL 0x034
+ #define RT3352_SYSC_REG_USB_PS 0x05c
+
+-#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
+-#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
+-#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
+ #define RT3352_RSTCTRL_UHST BIT(22)
+ #define RT3352_RSTCTRL_UDEV BIT(25)
+ #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -53,84 +53,6 @@ static unsigned long rt5350_get_mem_size
+ return ret;
+ }
+
+-void __init ralink_clk_init(void)
+-{
+- unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
+- unsigned long wmac_rate = 40000000;
+-
+- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+-
+- if (soc_is_rt305x() || soc_is_rt3350()) {
+- t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
+- RT305X_SYSCFG_CPUCLK_MASK;
+- switch (t) {
+- case RT305X_SYSCFG_CPUCLK_LOW:
+- cpu_rate = 320000000;
+- break;
+- case RT305X_SYSCFG_CPUCLK_HIGH:
+- cpu_rate = 384000000;
+- break;
+- }
+- sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
+- } else if (soc_is_rt3352()) {
+- t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
+- RT3352_SYSCFG0_CPUCLK_MASK;
+- switch (t) {
+- case RT3352_SYSCFG0_CPUCLK_LOW:
+- cpu_rate = 384000000;
+- break;
+- case RT3352_SYSCFG0_CPUCLK_HIGH:
+- cpu_rate = 400000000;
+- break;
+- }
+- sys_rate = wdt_rate = cpu_rate / 3;
+- uart_rate = 40000000;
+- } else if (soc_is_rt5350()) {
+- t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
+- RT5350_SYSCFG0_CPUCLK_MASK;
+- switch (t) {
+- case RT5350_SYSCFG0_CPUCLK_360:
+- cpu_rate = 360000000;
+- sys_rate = cpu_rate / 3;
+- break;
+- case RT5350_SYSCFG0_CPUCLK_320:
+- cpu_rate = 320000000;
+- sys_rate = cpu_rate / 4;
+- break;
+- case RT5350_SYSCFG0_CPUCLK_300:
+- cpu_rate = 300000000;
+- sys_rate = cpu_rate / 3;
+- break;
+- default:
+- BUG();
+- }
+- uart_rate = 40000000;
+- wdt_rate = sys_rate;
+- } else {
+- BUG();
+- }
+-
+- if (soc_is_rt3352() || soc_is_rt5350()) {
+- u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
+-
+- if (!(val & RT3352_CLKCFG0_XTAL_SEL))
+- wmac_rate = 20000000;
+- }
+-
+- ralink_clk_add("cpu", cpu_rate);
+- ralink_clk_add("sys", sys_rate);
+- ralink_clk_add("10000900.i2c", uart_rate);
+- ralink_clk_add("10000a00.i2s", uart_rate);
+- ralink_clk_add("10000b00.spi", sys_rate);
+- ralink_clk_add("10000b40.spi", sys_rate);
+- ralink_clk_add("10000100.timer", wdt_rate);
+- ralink_clk_add("10000120.watchdog", wdt_rate);
+- ralink_clk_add("10000500.uart", uart_rate);
+- ralink_clk_add("10000c00.uartlite", uart_rate);
+- ralink_clk_add("10100000.ethernet", sys_rate);
+- ralink_clk_add("10180000.wmac", wmac_rate);
+-}
+-
+ void __init ralink_of_remap(void)
+ {
+ rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
--- /dev/null
+From 7cd1bb48885449a9323c7ff0f10012925e93b4e1 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:37 +0200
+Subject: [PATCH 5/9] mips: ralink: rt3883: remove clock related code
+
+A properly clock driver for ralink SoCs has been added. Hence there is no
+need to have clock related code in 'arch/mips/ralink' folder anymore.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mach-ralink/rt3883.h | 8 ------
+ arch/mips/ralink/rt3883.c | 44 ------------------------------
+ 2 files changed, 52 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/rt3883.h
++++ b/arch/mips/include/asm/mach-ralink/rt3883.h
+@@ -90,14 +90,6 @@
+ #define RT3883_REVID_VER_ID_SHIFT 8
+ #define RT3883_REVID_ECO_ID_MASK 0x0f
+
+-#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
+-#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
+-#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
+-#define RT3883_SYSCFG0_CPUCLK_250 0x0
+-#define RT3883_SYSCFG0_CPUCLK_384 0x1
+-#define RT3883_SYSCFG0_CPUCLK_480 0x2
+-#define RT3883_SYSCFG0_CPUCLK_500 0x3
+-
+ #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
+ #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
+ #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
+--- a/arch/mips/ralink/rt3883.c
++++ b/arch/mips/ralink/rt3883.c
+@@ -17,50 +17,6 @@
+
+ #include "common.h"
+
+-void __init ralink_clk_init(void)
+-{
+- unsigned long cpu_rate, sys_rate;
+- u32 syscfg0;
+- u32 clksel;
+- u32 ddr2;
+-
+- syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
+- clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
+- RT3883_SYSCFG0_CPUCLK_MASK);
+- ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
+-
+- switch (clksel) {
+- case RT3883_SYSCFG0_CPUCLK_250:
+- cpu_rate = 250000000;
+- sys_rate = (ddr2) ? 125000000 : 83000000;
+- break;
+- case RT3883_SYSCFG0_CPUCLK_384:
+- cpu_rate = 384000000;
+- sys_rate = (ddr2) ? 128000000 : 96000000;
+- break;
+- case RT3883_SYSCFG0_CPUCLK_480:
+- cpu_rate = 480000000;
+- sys_rate = (ddr2) ? 160000000 : 120000000;
+- break;
+- case RT3883_SYSCFG0_CPUCLK_500:
+- cpu_rate = 500000000;
+- sys_rate = (ddr2) ? 166000000 : 125000000;
+- break;
+- }
+-
+- ralink_clk_add("cpu", cpu_rate);
+- ralink_clk_add("10000100.timer", sys_rate);
+- ralink_clk_add("10000120.watchdog", sys_rate);
+- ralink_clk_add("10000500.uart", 40000000);
+- ralink_clk_add("10000900.i2c", 40000000);
+- ralink_clk_add("10000a00.i2s", 40000000);
+- ralink_clk_add("10000b00.spi", sys_rate);
+- ralink_clk_add("10000b40.spi", sys_rate);
+- ralink_clk_add("10000c00.uartlite", 40000000);
+- ralink_clk_add("10100000.ethernet", sys_rate);
+- ralink_clk_add("10180000.wmac", 40000000);
+-}
+-
+ void __init ralink_of_remap(void)
+ {
+ rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
--- /dev/null
+From 04b153abdfcbaba70ceef5a846067d4447fd0078 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:38 +0200
+Subject: [PATCH 6/9] mips: ralink: mt7620: remove clock related code
+
+A proper clock driver for ralink SoCs has been added. Hence there is no
+need to have clock related code in 'arch/mips/ralink' folder anymore.
+Since this is the last clock related code removal, remove also remaining
+prototypes in 'common.h' header file.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h | 35 -----
+ arch/mips/ralink/common.h | 3 -
+ arch/mips/ralink/mt7620.c | 226 -----------------------------
+ 3 files changed, 264 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -19,52 +19,17 @@
+ #define SYSC_REG_CHIP_REV 0x0c
+ #define SYSC_REG_SYSTEM_CONFIG0 0x10
+ #define SYSC_REG_SYSTEM_CONFIG1 0x14
+-#define SYSC_REG_CLKCFG0 0x2c
+-#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
+-#define SYSC_REG_CPLL_CONFIG0 0x54
+-#define SYSC_REG_CPLL_CONFIG1 0x58
+
+ #define MT7620_CHIP_NAME0 0x3637544d
+ #define MT7620_CHIP_NAME1 0x20203032
+ #define MT7628_CHIP_NAME1 0x20203832
+
+-#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
+-
+ #define CHIP_REV_PKG_MASK 0x1
+ #define CHIP_REV_PKG_SHIFT 16
+ #define CHIP_REV_VER_MASK 0xf
+ #define CHIP_REV_VER_SHIFT 8
+ #define CHIP_REV_ECO_MASK 0xf
+
+-#define CLKCFG0_PERI_CLK_SEL BIT(4)
+-
+-#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
+-#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
+-#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
+-#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
+-#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
+-#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
+-#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
+-#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
+-
+-#define CPLL_CFG0_SW_CFG BIT(31)
+-#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
+-#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
+-#define CPLL_CFG0_LC_CURFCK BIT(15)
+-#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
+-#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
+-#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
+-
+-#define CPLL_CFG1_CPU_AUX1 BIT(25)
+-#define CPLL_CFG1_CPU_AUX0 BIT(24)
+-
+ #define SYSCFG0_DRAM_TYPE_MASK 0x3
+ #define SYSCFG0_DRAM_TYPE_SHIFT 4
+ #define SYSCFG0_DRAM_TYPE_SDRAM 0
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -23,9 +23,6 @@ extern struct ralink_soc_info soc_info;
+
+ extern void ralink_of_remap(void);
+
+-extern void ralink_clk_init(void);
+-extern void ralink_clk_add(const char *dev, unsigned long rate);
+-
+ extern void ralink_rst_init(void);
+
+ extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -34,12 +34,6 @@
+ #define PMU1_CFG 0x8C
+ #define DIG_SW_SEL BIT(25)
+
+-/* clock scaling */
+-#define CLKCFG_FDIV_MASK 0x1f00
+-#define CLKCFG_FDIV_USB_VAL 0x0300
+-#define CLKCFG_FFRAC_MASK 0x001f
+-#define CLKCFG_FFRAC_USB_VAL 0x0003
+-
+ /* EFUSE bits */
+ #define EFUSE_MT7688 0x100000
+
+@@ -49,226 +43,6 @@
+ /* does the board have sdram or ddram */
+ static int dram_type;
+
+-static __init u32
+-mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
+-{
+- u64 t;
+-
+- t = ref_rate;
+- t *= mul;
+- do_div(t, div);
+-
+- return t;
+-}
+-
+-#define MHZ(x) ((x) * 1000 * 1000)
+-
+-static __init unsigned long
+-mt7620_get_xtal_rate(void)
+-{
+- u32 reg;
+-
+- reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
+- if (reg & SYSCFG0_XTAL_FREQ_SEL)
+- return MHZ(40);
+-
+- return MHZ(20);
+-}
+-
+-static __init unsigned long
+-mt7620_get_periph_rate(unsigned long xtal_rate)
+-{
+- u32 reg;
+-
+- reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
+- if (reg & CLKCFG0_PERI_CLK_SEL)
+- return xtal_rate;
+-
+- return MHZ(40);
+-}
+-
+-static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
+-
+-static __init unsigned long
+-mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
+-{
+- u32 reg;
+- u32 mul;
+- u32 div;
+-
+- reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
+- if (reg & CPLL_CFG0_BYPASS_REF_CLK)
+- return xtal_rate;
+-
+- if ((reg & CPLL_CFG0_SW_CFG) == 0)
+- return MHZ(600);
+-
+- mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
+- CPLL_CFG0_PLL_MULT_RATIO_MASK;
+- mul += 24;
+- if (reg & CPLL_CFG0_LC_CURFCK)
+- mul *= 2;
+-
+- div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
+- CPLL_CFG0_PLL_DIV_RATIO_MASK;
+-
+- WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
+-
+- return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
+-}
+-
+-static __init unsigned long
+-mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
+-{
+- u32 reg;
+-
+- reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
+- if (reg & CPLL_CFG1_CPU_AUX1)
+- return xtal_rate;
+-
+- if (reg & CPLL_CFG1_CPU_AUX0)
+- return MHZ(480);
+-
+- return cpu_pll_rate;
+-}
+-
+-static __init unsigned long
+-mt7620_get_cpu_rate(unsigned long pll_rate)
+-{
+- u32 reg;
+- u32 mul;
+- u32 div;
+-
+- reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+-
+- mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
+- div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
+- CPU_SYS_CLKCFG_CPU_FDIV_MASK;
+-
+- return mt7620_calc_rate(pll_rate, mul, div);
+-}
+-
+-static const u32 mt7620_ocp_dividers[16] __initconst = {
+- [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
+- [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
+- [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
+- [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
+- [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
+-};
+-
+-static __init unsigned long
+-mt7620_get_dram_rate(unsigned long pll_rate)
+-{
+- if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
+- return pll_rate / 4;
+-
+- return pll_rate / 3;
+-}
+-
+-static __init unsigned long
+-mt7620_get_sys_rate(unsigned long cpu_rate)
+-{
+- u32 reg;
+- u32 ocp_ratio;
+- u32 div;
+-
+- reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+-
+- ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
+- CPU_SYS_CLKCFG_OCP_RATIO_MASK;
+-
+- if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
+- return cpu_rate;
+-
+- div = mt7620_ocp_dividers[ocp_ratio];
+- if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
+- return cpu_rate;
+-
+- return cpu_rate / div;
+-}
+-
+-void __init ralink_clk_init(void)
+-{
+- unsigned long xtal_rate;
+- unsigned long cpu_pll_rate;
+- unsigned long pll_rate;
+- unsigned long cpu_rate;
+- unsigned long sys_rate;
+- unsigned long dram_rate;
+- unsigned long periph_rate;
+- unsigned long pcmi2s_rate;
+-
+- xtal_rate = mt7620_get_xtal_rate();
+-
+-#define RFMT(label) label ":%lu.%03luMHz "
+-#define RINT(x) ((x) / 1000000)
+-#define RFRAC(x) (((x) / 1000) % 1000)
+-
+- if (is_mt76x8()) {
+- if (xtal_rate == MHZ(40))
+- cpu_rate = MHZ(580);
+- else
+- cpu_rate = MHZ(575);
+- dram_rate = sys_rate = cpu_rate / 3;
+- periph_rate = MHZ(40);
+- pcmi2s_rate = MHZ(480);
+-
+- ralink_clk_add("10000d00.uartlite", periph_rate);
+- ralink_clk_add("10000e00.uartlite", periph_rate);
+- } else {
+- cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
+- pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
+-
+- cpu_rate = mt7620_get_cpu_rate(pll_rate);
+- dram_rate = mt7620_get_dram_rate(pll_rate);
+- sys_rate = mt7620_get_sys_rate(cpu_rate);
+- periph_rate = mt7620_get_periph_rate(xtal_rate);
+- pcmi2s_rate = periph_rate;
+-
+- pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
+- RINT(xtal_rate), RFRAC(xtal_rate),
+- RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
+- RINT(pll_rate), RFRAC(pll_rate));
+-
+- ralink_clk_add("10000500.uart", periph_rate);
+- }
+-
+- pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
+- RINT(cpu_rate), RFRAC(cpu_rate),
+- RINT(dram_rate), RFRAC(dram_rate),
+- RINT(sys_rate), RFRAC(sys_rate),
+- RINT(periph_rate), RFRAC(periph_rate));
+-#undef RFRAC
+-#undef RINT
+-#undef RFMT
+-
+- ralink_clk_add("cpu", cpu_rate);
+- ralink_clk_add("10000100.timer", periph_rate);
+- ralink_clk_add("10000120.watchdog", periph_rate);
+- ralink_clk_add("10000900.i2c", periph_rate);
+- ralink_clk_add("10000a00.i2s", pcmi2s_rate);
+- ralink_clk_add("10000b00.spi", sys_rate);
+- ralink_clk_add("10000b40.spi", sys_rate);
+- ralink_clk_add("10000c00.uartlite", periph_rate);
+- ralink_clk_add("10000d00.uart1", periph_rate);
+- ralink_clk_add("10000e00.uart2", periph_rate);
+- ralink_clk_add("10180000.wmac", xtal_rate);
+-
+- if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
+- /*
+- * When the CPU goes into sleep mode, the BUS clock will be
+- * too low for USB to function properly. Adjust the busses
+- * fractional divider to fix this
+- */
+- u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+-
+- val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
+- val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
+-
+- rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
+- }
+-}
+-
+ void __init ralink_of_remap(void)
+ {
+ rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
--- /dev/null
+From 201ddc05777cd8e084b508bcdda22214bfe2895e Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:39 +0200
+Subject: [PATCH 7/9] mips: ralink: remove reset related code
+
+A proper clock driver for ralink SoCs has been added. This driver is also
+a reset provider for the SoC. Hence there is no need to have reset related
+code in 'arch/mips/ralink' folder anymore. The only code that remains is
+the one related with mips_reboot_setup where a PCI reset is performed.
+We maintain this because I cannot test old ralink board with PCI to be
+sure all works if we remove also this code.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/ralink/common.h | 2 --
+ arch/mips/ralink/of.c | 4 ----
+ arch/mips/ralink/reset.c | 61 -----------------------------------------------
+ 3 files changed, 67 deletions(-)
+
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -23,8 +23,6 @@ extern struct ralink_soc_info soc_info;
+
+ extern void ralink_of_remap(void);
+
+-extern void ralink_rst_init(void);
+-
+ extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
+
+ __iomem void *plat_of_remap_node(const char *node);
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -95,10 +95,6 @@ static int __init plat_of_setup(void)
+ {
+ __dt_register_buses(soc_info.compatible, "palmbus");
+
+- /* make sure that the reset controller is setup early */
+- if (ralink_soc != MT762X_SOC_MT7621AT)
+- ralink_rst_init();
+-
+ return 0;
+ }
+
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -10,7 +10,6 @@
+ #include <linux/io.h>
+ #include <linux/of.h>
+ #include <linux/delay.h>
+-#include <linux/reset-controller.h>
+
+ #include <asm/reboot.h>
+
+@@ -22,66 +21,6 @@
+ #define RSTCTL_RESET_PCI BIT(26)
+ #define RSTCTL_RESET_SYSTEM BIT(0)
+
+-static int ralink_assert_device(struct reset_controller_dev *rcdev,
+- unsigned long id)
+-{
+- u32 val;
+-
+- if (id == 0)
+- return -1;
+-
+- val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
+- val |= BIT(id);
+- rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+-
+- return 0;
+-}
+-
+-static int ralink_deassert_device(struct reset_controller_dev *rcdev,
+- unsigned long id)
+-{
+- u32 val;
+-
+- if (id == 0)
+- return -1;
+-
+- val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
+- val &= ~BIT(id);
+- rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+-
+- return 0;
+-}
+-
+-static int ralink_reset_device(struct reset_controller_dev *rcdev,
+- unsigned long id)
+-{
+- ralink_assert_device(rcdev, id);
+- return ralink_deassert_device(rcdev, id);
+-}
+-
+-static const struct reset_control_ops reset_ops = {
+- .reset = ralink_reset_device,
+- .assert = ralink_assert_device,
+- .deassert = ralink_deassert_device,
+-};
+-
+-static struct reset_controller_dev reset_dev = {
+- .ops = &reset_ops,
+- .owner = THIS_MODULE,
+- .nr_resets = 32,
+- .of_reset_n_cells = 1,
+-};
+-
+-void ralink_rst_init(void)
+-{
+- reset_dev.of_node = of_find_compatible_node(NULL, NULL,
+- "ralink,rt2880-reset");
+- if (!reset_dev.of_node)
+- pr_err("Failed to find reset controller node");
+- else
+- reset_controller_register(&reset_dev);
+-}
+-
+ static void ralink_restart(char *command)
+ {
+ if (IS_ENABLED(CONFIG_PCI)) {
--- /dev/null
+From ad38c17b0c26ae2108b50ac1eb0281a2e1ce08e9 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:40 +0200
+Subject: [PATCH 8/9] mips: ralink: get cpu rate from new driver code
+
+At very early stage on boot, there is a need to set 'mips_hpt_frequency'.
+This timer frequency is a half of the CPU frequency. To get clocks properly
+set we need to call to 'of_clk_init()' and properly get cpu clock frequency
+afterwards. Depending on the SoC, CPU clock index and compatible differs, so
+use them to get the proper clock frm the clock provider. Hence, adapt code
+to be aligned with new clock driver.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/ralink/clk.c | 61 ++++++++++++++++++++++++++++++++++++++++++--------
+ 1 file changed, 52 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/ralink/clk.c
++++ b/arch/mips/ralink/clk.c
+@@ -11,29 +11,72 @@
+ #include <linux/clkdev.h>
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
++#include <asm/mach-ralink/ralink_regs.h>
+
+ #include <asm/time.h>
+
+ #include "common.h"
+
+-void ralink_clk_add(const char *dev, unsigned long rate)
++static const char *clk_cpu(int *idx)
+ {
+- struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
+-
+- if (!clk)
+- panic("failed to add clock");
+-
+- clkdev_create(clk, NULL, "%s", dev);
++ switch (ralink_soc) {
++ case RT2880_SOC:
++ *idx = 0;
++ return "ralink,rt2880-sysc";
++ case RT3883_SOC:
++ *idx = 0;
++ return "ralink,rt3883-sysc";
++ case RT305X_SOC_RT3050:
++ *idx = 0;
++ return "ralink,rt3050-sysc";
++ case RT305X_SOC_RT3052:
++ *idx = 0;
++ return "ralink,rt3052-sysc";
++ case RT305X_SOC_RT3350:
++ *idx = 1;
++ return "ralink,rt3350-sysc";
++ case RT305X_SOC_RT3352:
++ *idx = 1;
++ return "ralink,rt3352-sysc";
++ case RT305X_SOC_RT5350:
++ *idx = 1;
++ return "ralink,rt5350-sysc";
++ case MT762X_SOC_MT7620A:
++ *idx = 2;
++ return "ralink,mt7620-sysc";
++ case MT762X_SOC_MT7620N:
++ *idx = 2;
++ return "ralink,mt7620-sysc";
++ case MT762X_SOC_MT7628AN:
++ *idx = 1;
++ return "ralink,mt7628-sysc";
++ case MT762X_SOC_MT7688:
++ *idx = 1;
++ return "ralink,mt7688-sysc";
++ default:
++ *idx = -1;
++ return "invalid";
++ }
+ }
+
+ void __init plat_time_init(void)
+ {
++ struct of_phandle_args clkspec;
++ const char *compatible;
+ struct clk *clk;
++ int cpu_clk_idx;
+
+ ralink_of_remap();
+
+- ralink_clk_init();
+- clk = clk_get_sys("cpu", NULL);
++ compatible = clk_cpu(&cpu_clk_idx);
++ if (cpu_clk_idx == -1)
++ panic("unable to get CPU clock index");
++
++ of_clk_init(NULL);
++ clkspec.np = of_find_compatible_node(NULL, NULL, compatible);
++ clkspec.args_count = 1;
++ clkspec.args[0] = cpu_clk_idx;
++ clk = of_clk_get_from_provider(&clkspec);
+ if (IS_ERR(clk))
+ panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
+ pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
--- /dev/null
+From fc15a7193a4d37d79e873fa06cc423180ddd2ddf Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 19 Jun 2023 06:09:41 +0200
+Subject: [PATCH 9/9] MAINTAINERS: add Mediatek MTMIPS Clock maintainer
+
+Adding myself as maintainer for Mediatek MTMIPS clock driver.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ MAINTAINERS | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -11858,6 +11858,12 @@ S: Maintained
+ F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
+ F: drivers/clk/ralink/clk-mt7621.c
+
++MEDIATEK MTMIPS CLOCK DRIVER
++M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
++S: Maintained
++F: Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
++F: drivers/clk/ralink/clk-mtmips.c
++
+ MEDIATEK MT7621/28/88 I2C DRIVER
+ M: Stefan Roese <sr@denx.de>
+ L: linux-i2c@vger.kernel.org
--- /dev/null
+From fd99ac5055d4705e91c73d1adba18bc71c8511a8 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Tue, 20 Jun 2023 19:44:32 +0800
+Subject: [PATCH] mips: ralink: introduce commonly used remap node function
+
+The ralink_of_remap() function is repeated several times on SoC specific
+source files. They have the same structure, but just differ in compatible
+strings. In order to make commonly use of these codes, this patch
+introduces a newly designed mtmips_of_remap_node() function to match and
+remap all supported system controller and memory controller nodes.
+
+Build and run tested on MT7620 and MT7628.
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/ralink/common.h | 2 --
+ arch/mips/ralink/mt7620.c | 9 ---------
+ arch/mips/ralink/mt7621.c | 9 ---------
+ arch/mips/ralink/of.c | 42 +++++++++++++++++++++++++++++++++++-------
+ arch/mips/ralink/rt288x.c | 9 ---------
+ arch/mips/ralink/rt305x.c | 9 ---------
+ arch/mips/ralink/rt3883.c | 9 ---------
+ 7 files changed, 35 insertions(+), 54 deletions(-)
+
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -25,6 +25,4 @@ extern void ralink_of_remap(void);
+
+ extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
+
+-__iomem void *plat_of_remap_node(const char *node);
+-
+ #endif /* _RALINK_COMMON_H__ */
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -43,15 +43,6 @@
+ /* does the board have sdram or ddram */
+ static int dram_type;
+
+-void __init ralink_of_remap(void)
+-{
+- rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
+- rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
+-
+- if (!rt_sysc_membase || !rt_memc_membase)
+- panic("Failed to remap core resources");
+-}
+-
+ static __init void
+ mt7620_dram_init(struct ralink_soc_info *soc_info)
+ {
+--- a/arch/mips/ralink/mt7621.c
++++ b/arch/mips/ralink/mt7621.c
+@@ -58,15 +58,6 @@ static void __init mt7621_memory_detect(
+ memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
+ }
+
+-void __init ralink_of_remap(void)
+-{
+- rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+- rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
+-
+- if (!rt_sysc_membase || !rt_memc_membase)
+- panic("Failed to remap core resources");
+-}
+-
+ static unsigned int __init mt7621_get_soc_name0(void)
+ {
+ return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -29,26 +29,56 @@ __iomem void *rt_sysc_membase;
+ __iomem void *rt_memc_membase;
+ EXPORT_SYMBOL_GPL(rt_sysc_membase);
+
+-__iomem void *plat_of_remap_node(const char *node)
++static const struct of_device_id mtmips_memc_match[] = {
++ { .compatible = "mediatek,mt7621-memc" },
++ { .compatible = "ralink,mt7620a-memc" },
++ { .compatible = "ralink,rt2880-memc" },
++ { .compatible = "ralink,rt3050-memc" },
++ { .compatible = "ralink,rt3883-memc" },
++ {}
++};
++
++static const struct of_device_id mtmips_sysc_match[] = {
++ { .compatible = "mediatek,mt7621-sysc" },
++ { .compatible = "ralink,mt7620a-sysc" },
++ { .compatible = "ralink,rt2880-sysc" },
++ { .compatible = "ralink,rt3050-sysc" },
++ { .compatible = "ralink,rt3883-sysc" },
++ {}
++};
++
++static __iomem void *
++mtmips_of_remap_node(const struct of_device_id *match, const char *type)
+ {
+ struct resource res;
+ struct device_node *np;
+
+- np = of_find_compatible_node(NULL, NULL, node);
++ np = of_find_matching_node(NULL, match);
+ if (!np)
+- panic("Failed to find %s node", node);
++ panic("Failed to find %s controller node", type);
+
+ if (of_address_to_resource(np, 0, &res))
+- panic("Failed to get resource for %s", node);
++ panic("Failed to get resource for %s node", np->name);
+
+ if (!request_mem_region(res.start,
+ resource_size(&res),
+ res.name))
+- panic("Failed to request resources for %s", node);
++ panic("Failed to request resources for %s node", np->name);
++
++ of_node_put(np);
+
+ return ioremap(res.start, resource_size(&res));
+ }
+
++void __init ralink_of_remap(void)
++{
++ rt_sysc_membase = mtmips_of_remap_node(mtmips_sysc_match, "system");
++ rt_memc_membase = mtmips_of_remap_node(mtmips_memc_match, "memory");
++
++ if (!rt_sysc_membase || !rt_memc_membase)
++ panic("Failed to remap core resources");
++}
++
+ void __init device_tree_init(void)
+ {
+ unflatten_and_copy_device_tree();
+--- a/arch/mips/ralink/rt288x.c
++++ b/arch/mips/ralink/rt288x.c
+@@ -17,15 +17,6 @@
+
+ #include "common.h"
+
+-void __init ralink_of_remap(void)
+-{
+- rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
+- rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
+-
+- if (!rt_sysc_membase || !rt_memc_membase)
+- panic("Failed to remap core resources");
+-}
+-
+ void __init prom_soc_init(struct ralink_soc_info *soc_info)
+ {
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -53,15 +53,6 @@ static unsigned long rt5350_get_mem_size
+ return ret;
+ }
+
+-void __init ralink_of_remap(void)
+-{
+- rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
+- rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
+-
+- if (!rt_sysc_membase || !rt_memc_membase)
+- panic("Failed to remap core resources");
+-}
+-
+ void __init prom_soc_init(struct ralink_soc_info *soc_info)
+ {
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
+--- a/arch/mips/ralink/rt3883.c
++++ b/arch/mips/ralink/rt3883.c
+@@ -17,15 +17,6 @@
+
+ #include "common.h"
+
+-void __init ralink_of_remap(void)
+-{
+- rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
+- rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
+-
+- if (!rt_sysc_membase || !rt_memc_membase)
+- panic("Failed to remap core resources");
+-}
+-
+ void __init prom_soc_init(struct ralink_soc_info *soc_info)
+ {
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
--- /dev/null
+From 6e68dae946e3a0333fbde5487ce163142ca10ae0 Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <nathan@kernel.org>
+Date: Thu, 22 Jun 2023 15:56:19 +0000
+Subject: clk: ralink: mtmips: Fix uninitialized use of ret in
+ mtmips_register_{fixed,factor}_clocks()
+
+Clang warns:
+
+ drivers/clk/ralink/clk-mtmips.c:309:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
+ 309 | return ret;
+ | ^~~
+ drivers/clk/ralink/clk-mtmips.c:285:9: note: initialize the variable 'ret' to silence this warning
+ 285 | int ret, i;
+ | ^
+ | = 0
+ drivers/clk/ralink/clk-mtmips.c:359:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
+ 359 | return ret;
+ | ^~~
+ drivers/clk/ralink/clk-mtmips.c:335:9: note: initialize the variable 'ret' to silence this warning
+ 335 | int ret, i;
+ | ^
+ | = 0
+ 2 errors generated.
+
+Set ret to the return value of clk_hw_register_fixed_rate() using the
+PTR_ERR() macro, which ensures ret is not used uninitialized, clearing
+up the warning.
+
+Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
+Closes: https://github.com/ClangBuiltLinux/linux/issues/1879
+Signed-off-by: Nathan Chancellor <nathan@kernel.org>
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ drivers/clk/ralink/clk-mtmips.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/clk/ralink/clk-mtmips.c
++++ b/drivers/clk/ralink/clk-mtmips.c
+@@ -292,6 +292,7 @@ static int mtmips_register_fixed_clocks(
+ sclk->parent, 0,
+ sclk->rate);
+ if (IS_ERR(sclk->hw)) {
++ ret = PTR_ERR(sclk->hw);
+ pr_err("Couldn't register fixed clock %d\n", idx);
+ goto err_clk_unreg;
+ }
+@@ -342,6 +343,7 @@ static int mtmips_register_factor_clocks
+ sclk->parent, sclk->flags,
+ sclk->mult, sclk->div);
+ if (IS_ERR(sclk->hw)) {
++ ret = PTR_ERR(sclk->hw);
+ pr_err("Couldn't register factor clock %d\n", idx);
+ goto err_clk_unreg;
+ }
--- /dev/null
+From 670f77f76f650b1b341d31d009cc2fb03a4d1fcf Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 23 Jun 2023 08:17:48 +0800
+Subject: mips: ralink: match all supported system controller compatible
+ strings
+
+Recently, A new clock and reset controller driver has been introduced to
+the ralink mips target[1]. It provides proper system control and adds more
+SoC specific compatible strings. In order to better initialize CPUs, this
+patch removes the outdated "ralink,mt7620a-sysc" and add all dt-binding
+documented compatible strings to the system controller match table.
+
+[1] https://lore.kernel.org/all/20230619040941.1340372-1-sergio.paracuellos@gmail.com/
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/ralink/of.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -40,10 +40,15 @@ static const struct of_device_id mtmips_
+
+ static const struct of_device_id mtmips_sysc_match[] = {
+ { .compatible = "mediatek,mt7621-sysc" },
+- { .compatible = "ralink,mt7620a-sysc" },
++ { .compatible = "ralink,mt7620-sysc" },
++ { .compatible = "ralink,mt7628-sysc" },
++ { .compatible = "ralink,mt7688-sysc" },
+ { .compatible = "ralink,rt2880-sysc" },
+ { .compatible = "ralink,rt3050-sysc" },
++ { .compatible = "ralink,rt3052-sysc" },
++ { .compatible = "ralink,rt3352-sysc" },
+ { .compatible = "ralink,rt3883-sysc" },
++ { .compatible = "ralink,rt5350-sysc" },
+ {}
+ };
+
+++ /dev/null
---- a/arch/mips/ralink/reset.c
-+++ b/arch/mips/ralink/reset.c
-@@ -11,6 +11,7 @@
- #include <linux/of.h>
- #include <linux/delay.h>
- #include <linux/reset-controller.h>
-+#include <linux/platform_device.h>
-
- #include <asm/reboot.h>
-
-@@ -65,21 +66,39 @@ static const struct reset_control_ops re
- .deassert = ralink_deassert_device,
- };
-
--static struct reset_controller_dev reset_dev = {
-- .ops = &reset_ops,
-- .owner = THIS_MODULE,
-- .nr_resets = 32,
-- .of_reset_n_cells = 1,
-+static int ralink_reset_probe(struct platform_device *pdev)
-+{
-+ struct reset_controller_dev *rcdev;
-+
-+ rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL);
-+ if (!rcdev)
-+ return -ENOMEM;
-+
-+ rcdev->ops = &reset_ops;
-+ rcdev->owner = THIS_MODULE;
-+ rcdev->nr_resets = 32;
-+ rcdev->of_reset_n_cells = 1;
-+ rcdev->of_node = pdev->dev.of_node;
-+
-+ return devm_reset_controller_register(&pdev->dev, rcdev);
-+}
-+
-+static const struct of_device_id ralink_reset_dt_ids[] = {
-+ { .compatible = "ralink,rt2880-reset" },
-+ {}
-+};
-+
-+static struct platform_driver ralink_reset_driver = {
-+ .probe = ralink_reset_probe,
-+ .driver = {
-+ .name = "ralink-reset",
-+ .of_match_table = ralink_reset_dt_ids,
-+ }
- };
-
- void ralink_rst_init(void)
- {
-- reset_dev.of_node = of_find_compatible_node(NULL, NULL,
-- "ralink,rt2880-reset");
-- if (!reset_dev.of_node)
-- pr_err("Failed to find reset controller node");
-- else
-- reset_controller_register(&reset_dev);
-+ platform_driver_register(&ralink_reset_driver);
- }
-
- static void ralink_restart(char *command)
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -96,4 +96,16 @@ static inline int mt7620_get_eco(void)
+@@ -61,4 +61,16 @@ static inline int mt7620_get_eco(void)
return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
}
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_BLK_MQ_PCI=y
CONFIG_CEVT_R4K=y
+CONFIG_CLK_MTMIPS=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_BOOL=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MIPS=y
CONFIG_MIPS_ASID_BITS=8
CONFIG_RALINK=y
CONFIG_RALINK_WDT=y
CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
CONFIG_RESET_CONTROLLER=y
CONFIG_SERIAL_8250_RT288X=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_CEVT_SYSTICK_QUIRK=y
CONFIG_CLKEVT_RT3352=y
CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_MTMIPS=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_BOOL=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_RIXI=y
CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y`
+CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R2=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_BLK_MQ_PCI=y
CONFIG_CEVT_R4K=y
+CONFIG_CLK_MTMIPS=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_BOOL=y
projects / openwrt / openwrt.git / commitdiff