mx5: Use explicit clock gate names

Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 8b0af3b1855a257bac5c9031641af08776279824..cba5d1bf0b4eee6414fad047d7cf34e5f1a2bd6e 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -102,9 +102,9 @@ void set_usboh3_clk(void)
 void enable_usboh3_clk(unsigned char enable)
 {
        if (enable)
-               setbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
+               setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
        else
-               clrbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
+               clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
 }
 
 #ifdef CONFIG_I2C_MXC
@@ -115,7 +115,8 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 
        if (i2c_num > 2)
                return -EINVAL;
-       mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
+       mask = MXC_CCM_CCGR_CG_MASK <<
+                       (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
        if (enable)
                setbits_le32(&mxc_ccm->CCGR1, mask);
        else
@@ -132,9 +133,9 @@ void set_usb_phy1_clk(void)
 void enable_usb_phy1_clk(unsigned char enable)
 {
        if (enable)
-               setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
+               setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
        else
-               clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
+               clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
 }
 
 void set_usb_phy2_clk(void)
@@ -145,9 +146,9 @@ void set_usb_phy2_clk(void)
 void enable_usb_phy2_clk(unsigned char enable)
 {
        if (enable)
-               setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
+               setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
        else
-               clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
+               clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
 }
 
 /*

diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index ab0e8186071def91395bbc44edfb2303cedec875..d5eb3033884dca6c4fc90785af49d7f8ccfca371 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -286,10 +286,281 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK                           0x3
 
-#define MXC_CCM_CCGR4_CG5_OFFSET                       10
-#define MXC_CCM_CCGR4_CG6_OFFSET                       12
-#define MXC_CCM_CCGR5_CG5_OFFSET                       10
-#define MXC_CCM_CCGR2_CG14_OFFSET                      28
+#define MXC_CCM_CCGR0_ARM_BUS_OFFSET                   0
+#define MXC_CCM_CCGR0_ARM_BUS(v)                       (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR0_ARM_AXI_OFFSET                   2
+#define MXC_CCM_CCGR0_ARM_AXI(v)                       (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET                 4
+#define MXC_CCM_CCGR0_ARM_DEBUG(v)                     (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR0_TZIC_OFFSET                      6
+#define MXC_CCM_CCGR0_TZIC(v)                          (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR0_DAP_OFFSET                       8
+#define MXC_CCM_CCGR0_DAP(v)                           (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR0_TPIU_OFFSET                      10
+#define MXC_CCM_CCGR0_TPIU(v)                          (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR0_CTI2_OFFSET                      12
+#define MXC_CCM_CCGR0_CTI2(v)                          (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR0_CTI3_OFFSET                      14
+#define MXC_CCM_CCGR0_CTI3(v)                          (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR0_AHBMUX1_OFFSET                   16
+#define MXC_CCM_CCGR0_AHBMUX1(v)                       (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR0_AHBMUX2_OFFSET                   18
+#define MXC_CCM_CCGR0_AHBMUX2(v)                       (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR0_ROMCP_OFFSET                     20
+#define MXC_CCM_CCGR0_ROMCP(v)                         (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR0_ROM_OFFSET                       22
+#define MXC_CCM_CCGR0_ROM(v)                           (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET                  24
+#define MXC_CCM_CCGR0_AIPS_TZ1(v)                      (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET                  26
+#define MXC_CCM_CCGR0_AIPS_TZ2(v)                      (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR0_AHB_MAX_OFFSET                   28
+#define MXC_CCM_CCGR0_AHB_MAX(v)                       (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR0_IIM_OFFSET                       30
+#define MXC_CCM_CCGR0_IIM(v)                           (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR1_TMAX1_OFFSET                     0
+#define MXC_CCM_CCGR1_TMAX1(v)                         (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR1_TMAX2_OFFSET                     2
+#define MXC_CCM_CCGR1_TMAX2(v)                         (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR1_TMAX3_OFFSET                     4
+#define MXC_CCM_CCGR1_TMAX3(v)                         (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR1_UART1_IPG_OFFSET                 6
+#define MXC_CCM_CCGR1_UART1_IPG(v)                     (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR1_UART1_PER_OFFSET                 8
+#define MXC_CCM_CCGR1_UART1_PER(v)                     (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR1_UART2_IPG_OFFSET                 10
+#define MXC_CCM_CCGR1_UART2_IPG(v)                     (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR1_UART2_PER_OFFSET                 12
+#define MXC_CCM_CCGR1_UART2_PER(v)                     (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR1_UART3_IPG_OFFSET                 14
+#define MXC_CCM_CCGR1_UART3_IPG(v)                     (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR1_UART3_PER_OFFSET                 16
+#define MXC_CCM_CCGR1_UART3_PER(v)                     (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR1_I2C1_OFFSET                      18
+#define MXC_CCM_CCGR1_I2C1(v)                          (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR1_I2C2_OFFSET                      20
+#define MXC_CCM_CCGR1_I2C2(v)                          (((v) & 0x3) << 20)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET                 22
+#define MXC_CCM_CCGR1_HSI2C_IPG(v)                     (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET              24
+#define MXC_CCM_CCGR1_HSI2C_SERIAL(v)                  (((v) & 0x3) << 24)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR1_I2C3_OFFSET                      22
+#define MXC_CCM_CCGR1_I2C3(v)                          (((v) & 0x3) << 22)
+#endif
+#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET                  26
+#define MXC_CCM_CCGR1_FIRI_IPG(v)                      (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET               28
+#define MXC_CCM_CCGR1_FIRI_SERIAL(v)                   (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR1_SCC_OFFSET                       30
+#define MXC_CCM_CCGR1_SCC(v)                           (((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR2_USB_PHY_OFFSET                   0
+#define MXC_CCM_CCGR2_USB_PHY(v)                       (((v) & 0x3) << 0)
+#endif
+#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET                 2
+#define MXC_CCM_CCGR2_EPIT1_IPG(v)                     (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET                  4
+#define MXC_CCM_CCGR2_EPIT1_HF(v)                      (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET                 6
+#define MXC_CCM_CCGR2_EPIT2_IPG(v)                     (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET                  8
+#define MXC_CCM_CCGR2_EPIT2_HF(v)                      (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET                  10
+#define MXC_CCM_CCGR2_PWM1_IPG(v)                      (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR2_PWM1_HF_OFFSET                   12
+#define MXC_CCM_CCGR2_PWM1_HF(v)                       (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET                  14
+#define MXC_CCM_CCGR2_PWM2_IPG(v)                      (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR2_PWM2_HF_OFFSET                   16
+#define MXC_CCM_CCGR2_PWM2_HF(v)                       (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR2_GPT_IPG_OFFSET                   18
+#define MXC_CCM_CCGR2_GPT_IPG(v)                       (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR2_GPT_HF_OFFSET                    20
+#define MXC_CCM_CCGR2_GPT_HF(v)                                (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR2_OWIRE_OFFSET                     22
+#define MXC_CCM_CCGR2_OWIRE(v)                         (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR2_FEC_OFFSET                       24
+#define MXC_CCM_CCGR2_FEC(v)                           (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET            26
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v)                        (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET                        28
+#define MXC_CCM_CCGR2_USBOH3_60M(v)                    (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR2_TVE_OFFSET                       30
+#define MXC_CCM_CCGR2_TVE(v)                           (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET                        0
+#define MXC_CCM_CCGR3_ESDHC1_IPG(v)                    (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET                        2
+#define MXC_CCM_CCGR3_ESDHC1_PER(v)                    (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET                        4
+#define MXC_CCM_CCGR3_ESDHC2_IPG(v)                    (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET                        6
+#define MXC_CCM_CCGR3_ESDHC2_PER(v)                    (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET                        8
+#define MXC_CCM_CCGR3_ESDHC3_IPG(v)                    (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET                        10
+#define MXC_CCM_CCGR3_ESDHC3_PER(v)                    (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET                        12
+#define MXC_CCM_CCGR3_ESDHC4_IPG(v)                    (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET                        14
+#define MXC_CCM_CCGR3_ESDHC4_PER(v)                    (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET                  16
+#define MXC_CCM_CCGR3_SSI1_IPG(v)                      (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET                  18
+#define MXC_CCM_CCGR3_SSI1_SSI(v)                      (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET                  20
+#define MXC_CCM_CCGR3_SSI2_IPG(v)                      (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET                  22
+#define MXC_CCM_CCGR3_SSI2_SSI(v)                      (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET                  24
+#define MXC_CCM_CCGR3_SSI3_IPG(v)                      (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET                  26
+#define MXC_CCM_CCGR3_SSI3_SSI(v)                      (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET                  28
+#define MXC_CCM_CCGR3_SSI_EXT1(v)                      (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET                  30
+#define MXC_CCM_CCGR3_SSI_EXT2(v)                      (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR4_PATA_OFFSET                      0
+#define MXC_CCM_CCGR4_PATA(v)                          (((v) & 0x3) << 0)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR4_SIM_IPG_OFFSET                   2
+#define MXC_CCM_CCGR4_SIM_IPG(v)                       (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET                        4
+#define MXC_CCM_CCGR4_SIM_SERIAL(v)                    (((v) & 0x3) << 4)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR4_SATA_OFFSET                      2
+#define MXC_CCM_CCGR4_SATA(v)                          (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET                  6
+#define MXC_CCM_CCGR4_CAN2_IPG(v)                      (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET               8
+#define MXC_CCM_CCGR4_CAN2_SERIAL(v)                   (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR4_USB_PHY1_OFFSET                  10
+#define MXC_CCM_CCGR4_USB_PHY1(v)                      (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR4_USB_PHY2_OFFSET                  12
+#define MXC_CCM_CCGR4_USB_PHY2(v)                      (((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR4_SAHARA_OFFSET                    14
+#define MXC_CCM_CCGR4_SAHARA(v)                                (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR4_RTIC_OFFSET                      16
+#define MXC_CCM_CCGR4_RTIC(v)                          (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET                        18
+#define MXC_CCM_CCGR4_ECSPI1_IPG(v)                    (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET                        20
+#define MXC_CCM_CCGR4_ECSPI1_PER(v)                    (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET                        22
+#define MXC_CCM_CCGR4_ECSPI2_IPG(v)                    (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET                        24
+#define MXC_CCM_CCGR4_ECSPI2_PER(v)                    (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET                  26
+#define MXC_CCM_CCGR4_CSPI_IPG(v)                      (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR4_SRTC_OFFSET                      28
+#define MXC_CCM_CCGR4_SRTC(v)                          (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR4_SDMA_OFFSET                      30
+#define MXC_CCM_CCGR4_SDMA(v)                          (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR5_SPBA_OFFSET                      0
+#define MXC_CCM_CCGR5_SPBA(v)                          (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR5_GPU_OFFSET                       2
+#define MXC_CCM_CCGR5_GPU(v)                           (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR5_GARB_OFFSET                      4
+#define MXC_CCM_CCGR5_GARB(v)                          (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR5_VPU_OFFSET                       6
+#define MXC_CCM_CCGR5_VPU(v)                           (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR5_VPU_REF_OFFSET                   8
+#define MXC_CCM_CCGR5_VPU_REF(v)                       (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR5_IPU_OFFSET                       10
+#define MXC_CCM_CCGR5_IPU(v)                           (((v) & 0x3) << 10)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_IPUMUX12_OFFSET                  12
+#define MXC_CCM_CCGR5_IPUMUX12(v)                      (((v) & 0x3) << 12)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR5_IPUMUX1_OFFSET                   12
+#define MXC_CCM_CCGR5_IPUMUX1(v)                       (((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR5_EMI_FAST_OFFSET                  14
+#define MXC_CCM_CCGR5_EMI_FAST(v)                      (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET                  16
+#define MXC_CCM_CCGR5_EMI_SLOW(v)                      (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR5_EMI_INT1_OFFSET                  18
+#define MXC_CCM_CCGR5_EMI_INT1(v)                      (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET                  20
+#define MXC_CCM_CCGR5_EMI_ENFC(v)                      (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET                  22
+#define MXC_CCM_CCGR5_EMI_WRCK(v)                      (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR5_GPC_IPG_OFFSET                   24
+#define MXC_CCM_CCGR5_GPC_IPG(v)                       (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR5_SPDIF0_OFFSET                    26
+#define MXC_CCM_CCGR5_SPDIF0(v)                                (((v) & 0x3) << 26)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_SPDIF1_OFFSET                    28
+#define MXC_CCM_CCGR5_SPDIF1(v)                                (((v) & 0x3) << 28)
+#endif
+#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET                 30
+#define MXC_CCM_CCGR5_SPDIF_IPG(v)                     (((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_IPUMUX2_OFFSET                   0
+#define MXC_CCM_CCGR6_IPUMUX2(v)                       (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR6_OCRAM_OFFSET                     2
+#define MXC_CCM_CCGR6_OCRAM(v)                         (((v) & 0x3) << 2)
+#endif
+#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET                 4
+#define MXC_CCM_CCGR6_CSI_MCLK1(v)                     (((v) & 0x3) << 4)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET                 6
+#define MXC_CCM_CCGR6_CSI_MCLK2(v)                     (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR6_EMI_GARB_OFFSET                  8
+#define MXC_CCM_CCGR6_EMI_GARB(v)                      (((v) & 0x3) << 8)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_EMI_INT2_OFFSET                  8
+#define MXC_CCM_CCGR6_EMI_INT2(v)                      (((v) & 0x3) << 8)
+#endif
+#define MXC_CCM_CCGR6_IPU_DI0_OFFSET                   10
+#define MXC_CCM_CCGR6_IPU_DI0(v)                       (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR6_IPU_DI1_OFFSET                   12
+#define MXC_CCM_CCGR6_IPU_DI1(v)                       (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR6_GPU2D_OFFSET                     14
+#define MXC_CCM_CCGR6_GPU2D(v)                         (((v) & 0x3) << 14)
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET                  16
+#define MXC_CCM_CCGR6_ESAI_IPG(v)                      (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET                 18
+#define MXC_CCM_CCGR6_ESAI_ROOT(v)                     (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET                  20
+#define MXC_CCM_CCGR6_CAN1_IPG(v)                      (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET               22
+#define MXC_CCM_CCGR6_CAN1_SERIAL(v)                   (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR6_PL301_4X1_OFFSET                 24
+#define MXC_CCM_CCGR6_PL301_4X1(v)                     (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR6_PL301_2X2_OFFSET                 26
+#define MXC_CCM_CCGR6_PL301_2X2(v)                     (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR6_LDB_DI0_OFFSET                   28
+#define MXC_CCM_CCGR6_LDB_DI0(v)                       (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR6_LDB_DI1_OFFSET                   30
+#define MXC_CCM_CCGR6_LDB_DI1(v)                       (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET                  0
+#define MXC_CCM_CCGR7_ASRC_IPG(v)                      (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET                        2
+#define MXC_CCM_CCGR7_ASRC_ASRCK(v)                    (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR7_MLB_OFFSET                       4
+#define MXC_CCM_CCGR7_MLB(v)                           (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR7_IEEE1588_OFFSET                  6
+#define MXC_CCM_CCGR7_IEEE1588(v)                      (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR7_UART4_IPG_OFFSET                 8
+#define MXC_CCM_CCGR7_UART4_IPG(v)                     (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR7_UART4_PER_OFFSET                 10
+#define MXC_CCM_CCGR7_UART4_PER(v)                     (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR7_UART5_IPG_OFFSET                 12
+#define MXC_CCM_CCGR7_UART5_IPG(v)                     (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR7_UART5_PER_OFFSET                 14
+#define MXC_CCM_CCGR7_UART5_PER(v)                     (((v) & 0x3) << 14)
+#endif
 
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)

diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index cc8f881a2d0155fa456d3540663fe13081a7b012..0f2d113a6f18d0e2ecc32eb00b2f13ad6d7454a1 100644 (file)
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -214,7 +214,7 @@ static struct clk ipu_clk = {
 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        .enable_reg = (u32 *)(CCM_BASE_ADDR +
                offsetof(struct mxc_ccm_reg, CCGR5)),
-       .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
+       .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
 #else
        .enable_reg = (u32 *)(CCM_BASE_ADDR +
                offsetof(struct mxc_ccm_reg, CCGR3)),