#
# TSP source files specific to FVP platform
-BL32_SOURCES += drivers/arm/gic/gic_v2.c \
+BL32_SOURCES += drivers/arm/gic/arm_gic.c \
+ drivers/arm/gic/gic_v2.c \
plat/common/aarch64/platform_mp_stack.S \
+ plat/common/plat_gic.c \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/aarch64/fvp_helpers.S \
- plat/fvp/bl32_fvp_setup.c \
- plat/fvp/fvp_gic.c
+ plat/fvp/bl32_fvp_setup.c
* `V`: Verbose build. If assigned anything other than 0, the build commands
are printed. Default is 0
-* `FVP_GIC_ARCH`: Choice of ARM GIC architecture version used by the FVP port
- for implementing the platform GIC API. This API is used by the interrupt
- management framework. Default is 2 i.e. version 2.0
+* `ARM_GIC_ARCH`: Choice of ARM GIC architecture version used by the ARM GIC
+ driver for implementing the platform GIC API. This API is used
+ by the interrupt management framework. Default is 2 i.e. version 2.0.
* `IMF_READ_INTERRUPT_ID`: Boolean flag used by the interrupt management
framework to enable passing of the interrupt id to its handler. The id is
--- /dev/null
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <arm_gic.h>
+#include <assert.h>
+#include <bl_common.h>
+#include <debug.h>
+#include <gic_v2.h>
+#include <gic_v3.h>
+#include <interrupt_mgmt.h>
+#include <platform.h>
+#include <stdint.h>
+
+
+static unsigned int g_gicc_base;
+static unsigned int g_gicd_base;
+static unsigned long g_gicr_base;
+static const unsigned int *g_irq_sec_ptr;
+static unsigned int g_num_irqs;
+
+
+/*******************************************************************************
+ * This function does some minimal GICv3 configuration. The Firmware itself does
+ * not fully support GICv3 at this time and relies on GICv2 emulation as
+ * provided by GICv3. This function allows software (like Linux) in later stages
+ * to use full GICv3 features.
+ ******************************************************************************/
+static void gicv3_cpuif_setup(void)
+{
+ unsigned int scr_val, val;
+ uintptr_t base;
+
+ /*
+ * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
+ * bit set. In order to allow interrupts to get routed to the CPU we
+ * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
+ * to clear (GICv3 Architecture specification 5.4.23).
+ * GICR_WAKER is NOT banked per CPU, compute the correct base address
+ * per CPU.
+ */
+ assert(g_gicr_base);
+ base = gicv3_get_rdist(g_gicr_base, read_mpidr());
+ if (base == (uintptr_t)NULL) {
+ /* No re-distributor base address. This interface cannot be
+ * configured.
+ */
+ panic();
+ }
+
+ val = gicr_read_waker(base);
+
+ val &= ~WAKER_PS;
+ gicr_write_waker(base, val);
+ dsb();
+
+ /* We need to wait for ChildrenAsleep to clear. */
+ val = gicr_read_waker(base);
+ while (val & WAKER_CA)
+ val = gicr_read_waker(base);
+
+ /*
+ * We need to set SCR_EL3.NS in order to see GICv3 non-secure state.
+ * Restore SCR_EL3.NS again before exit.
+ */
+ scr_val = read_scr();
+ write_scr(scr_val | SCR_NS_BIT);
+ isb(); /* ensure NS=1 takes effect before accessing ICC_SRE_EL2 */
+
+ /*
+ * By default EL2 and NS-EL1 software should be able to enable GICv3
+ * System register access without any configuration at EL3. But it turns
+ * out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So
+ * we need to set it here again. In order to do that we need to enable
+ * register access. We leave it enabled as it should be fine and might
+ * prevent problems with later software trying to access GIC System
+ * Registers.
+ */
+ val = read_icc_sre_el3();
+ write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
+
+ val = read_icc_sre_el2();
+ write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE);
+
+ write_icc_pmr_el1(GIC_PRI_MASK);
+ isb(); /* commit ICC_* changes before setting NS=0 */
+
+ /* Restore SCR_EL3 */
+ write_scr(scr_val);
+ isb(); /* ensure NS=0 takes effect immediately */
+}
+
+/*******************************************************************************
+ * This function does some minimal GICv3 configuration when cores go
+ * down.
+ ******************************************************************************/
+static void gicv3_cpuif_deactivate(void)
+{
+ unsigned int val;
+ uintptr_t base;
+
+ /*
+ * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
+ * wait for GICR_WAKER.ChildrenAsleep to get set.
+ * (GICv3 Architecture specification 5.4.23).
+ * GICR_WAKER is NOT banked per CPU, compute the correct base address
+ * per CPU.
+ */
+ assert(g_gicr_base);
+ base = gicv3_get_rdist(g_gicr_base, read_mpidr());
+ if (base == (uintptr_t)NULL) {
+ /* No re-distributor base address. This interface cannot be
+ * configured.
+ */
+ panic();
+ }
+
+ val = gicr_read_waker(base);
+ val |= WAKER_PS;
+ gicr_write_waker(base, val);
+ dsb();
+
+ /* We need to wait for ChildrenAsleep to set. */
+ val = gicr_read_waker(base);
+ while ((val & WAKER_CA) == 0)
+ val = gicr_read_waker(base);
+}
+
+
+/*******************************************************************************
+ * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
+ * and set the priority mask register to allow all interrupts to trickle in.
+ ******************************************************************************/
+void arm_gic_cpuif_setup(void)
+{
+ unsigned int val;
+
+ assert(g_gicc_base);
+ val = gicc_read_iidr(g_gicc_base);
+
+ /*
+ * If GICv3 we need to do a bit of additional setup. We want to
+ * allow default GICv2 behaviour but allow the next stage to
+ * enable full gicv3 features.
+ */
+ if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
+ gicv3_cpuif_setup();
+
+ val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
+ val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
+
+ gicc_write_pmr(g_gicc_base, GIC_PRI_MASK);
+ gicc_write_ctlr(g_gicc_base, val);
+}
+
+/*******************************************************************************
+ * Place the cpu interface in a state where it can never make a cpu exit wfi as
+ * as result of an asserted interrupt. This is critical for powering down a cpu
+ ******************************************************************************/
+void arm_gic_cpuif_deactivate(void)
+{
+ unsigned int val;
+
+ /* Disable secure, non-secure interrupts and disable their bypass */
+ assert(g_gicc_base);
+ val = gicc_read_ctlr(g_gicc_base);
+ val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
+ val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
+ val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
+ gicc_write_ctlr(g_gicc_base, val);
+
+ val = gicc_read_iidr(g_gicc_base);
+
+ /*
+ * If GICv3 we need to do a bit of additional setup. Make sure the
+ * RDIST is put to sleep.
+ */
+ if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
+ gicv3_cpuif_deactivate();
+}
+
+/*******************************************************************************
+ * Per cpu gic distributor setup which will be done by all cpus after a cold
+ * boot/hotplug. This marks out the secure interrupts & enables them.
+ ******************************************************************************/
+void arm_gic_pcpu_distif_setup(void)
+{
+ unsigned int index, irq_num;
+
+ assert(g_gicd_base);
+ gicd_write_igroupr(g_gicd_base, 0, ~0);
+
+ assert(g_irq_sec_ptr);
+ for (index = 0; index < g_num_irqs; index++) {
+ irq_num = g_irq_sec_ptr[index];
+ if (irq_num < MIN_SPI_ID) {
+ /* We have an SGI or a PPI */
+ gicd_clr_igroupr(g_gicd_base, irq_num);
+ gicd_set_ipriorityr(g_gicd_base, irq_num,
+ GIC_HIGHEST_SEC_PRIORITY);
+ gicd_set_isenabler(g_gicd_base, irq_num);
+ }
+ }
+}
+
+/*******************************************************************************
+ * Global gic distributor setup which will be done by the primary cpu after a
+ * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
+ * then enables the secure GIC distributor interface.
+ ******************************************************************************/
+static void arm_gic_distif_setup(void)
+{
+ unsigned int num_ints, ctlr, index, irq_num;
+
+ /* Disable the distributor before going further */
+ assert(g_gicd_base);
+ ctlr = gicd_read_ctlr(g_gicd_base);
+ ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
+ gicd_write_ctlr(g_gicd_base, ctlr);
+
+ /*
+ * Mark out non-secure interrupts. Calculate number of
+ * IGROUPR registers to consider. Will be equal to the
+ * number of IT_LINES
+ */
+ num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK;
+ num_ints++;
+ for (index = 0; index < num_ints; index++)
+ gicd_write_igroupr(g_gicd_base, index << IGROUPR_SHIFT, ~0);
+
+ /* Configure secure interrupts now */
+ assert(g_irq_sec_ptr);
+ for (index = 0; index < g_num_irqs; index++) {
+ irq_num = g_irq_sec_ptr[index];
+ if (irq_num >= MIN_SPI_ID) {
+ /* We have an SPI */
+ gicd_clr_igroupr(g_gicd_base, irq_num);
+ gicd_set_ipriorityr(g_gicd_base, irq_num,
+ GIC_HIGHEST_SEC_PRIORITY);
+ gicd_set_itargetsr(g_gicd_base, irq_num,
+ platform_get_core_pos(read_mpidr()));
+ gicd_set_isenabler(g_gicd_base, irq_num);
+ }
+ }
+ arm_gic_pcpu_distif_setup();
+
+ gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0);
+}
+
+/*******************************************************************************
+ * Initialize the ARM GIC driver with the provided platform inputs
+******************************************************************************/
+void arm_gic_init(unsigned int gicc_base,
+ unsigned int gicd_base,
+ unsigned long gicr_base,
+ const unsigned int *irq_sec_ptr,
+ unsigned int num_irqs
+ )
+{
+ assert(gicc_base);
+ assert(gicd_base);
+ assert(gicr_base);
+ assert(irq_sec_ptr);
+ g_gicc_base = gicc_base;
+ g_gicd_base = gicd_base;
+ g_gicr_base = gicr_base;
+ g_irq_sec_ptr = irq_sec_ptr;
+ g_num_irqs = num_irqs;
+}
+
+/*******************************************************************************
+ * Setup the ARM GIC CPU and distributor interfaces.
+******************************************************************************/
+void arm_gic_setup(void)
+{
+ arm_gic_cpuif_setup();
+ arm_gic_distif_setup();
+}
+
+/*******************************************************************************
+ * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
+ * The interrupt controller knows which pin/line it uses to signal a type of
+ * interrupt. This function provides a common implementation of
+ * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
+ * across platforms. It lets the interrupt management framework determine
+ * for a type of interrupt and security state, which line should be used in the
+ * SCR_EL3 to control its routing to EL3. The interrupt line is represented as
+ * the bit position of the IRQ or FIQ bit in the SCR_EL3.
+ ******************************************************************************/
+uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
+ uint32_t security_state)
+{
+ assert(type == INTR_TYPE_S_EL1 ||
+ type == INTR_TYPE_EL3 ||
+ type == INTR_TYPE_NS);
+
+ assert(security_state == NON_SECURE || security_state == SECURE);
+
+ /*
+ * We ignore the security state parameter under the assumption that
+ * both normal and secure worlds are using ARM GICv2. This parameter
+ * will be used when the secure world starts using GICv3.
+ */
+#if ARM_GIC_ARCH == 2
+ return gicv2_interrupt_type_to_line(g_gicc_base, type);
+#else
+#error "Invalid ARM GIC architecture version specified for platform port"
+#endif /* ARM_GIC_ARCH */
+}
+
+#if ARM_GIC_ARCH == 2
+/*******************************************************************************
+ * This function returns the type of the highest priority pending interrupt at
+ * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
+ * interrupt pending.
+ ******************************************************************************/
+uint32_t arm_gic_get_pending_interrupt_type(void)
+{
+ uint32_t id;
+
+ assert(g_gicc_base);
+ id = gicc_read_hppir(g_gicc_base);
+
+ /* Assume that all secure interrupts are S-EL1 interrupts */
+ if (id < 1022)
+ return INTR_TYPE_S_EL1;
+
+ if (id == GIC_SPURIOUS_INTERRUPT)
+ return INTR_TYPE_INVAL;
+
+ return INTR_TYPE_NS;
+}
+
+/*******************************************************************************
+ * This function returns the id of the highest priority pending interrupt at
+ * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
+ * interrupt pending.
+ ******************************************************************************/
+uint32_t arm_gic_get_pending_interrupt_id(void)
+{
+ uint32_t id;
+
+ assert(g_gicc_base);
+ id = gicc_read_hppir(g_gicc_base);
+
+ if (id < 1022)
+ return id;
+
+ if (id == 1023)
+ return INTR_ID_UNAVAILABLE;
+
+ /*
+ * Find out which non-secure interrupt it is under the assumption that
+ * the GICC_CTLR.AckCtl bit is 0.
+ */
+ return gicc_read_ahppir(g_gicc_base);
+}
+
+/*******************************************************************************
+ * This functions reads the GIC cpu interface Interrupt Acknowledge register
+ * to start handling the pending interrupt. It returns the contents of the IAR.
+ ******************************************************************************/
+uint32_t arm_gic_acknowledge_interrupt(void)
+{
+ assert(g_gicc_base);
+ return gicc_read_IAR(g_gicc_base);
+}
+
+/*******************************************************************************
+ * This functions writes the GIC cpu interface End Of Interrupt register with
+ * the passed value to finish handling the active interrupt
+ ******************************************************************************/
+void arm_gic_end_of_interrupt(uint32_t id)
+{
+ assert(g_gicc_base);
+ gicc_write_EOIR(g_gicc_base, id);
+}
+
+/*******************************************************************************
+ * This function returns the type of the interrupt id depending upon the group
+ * this interrupt has been configured under by the interrupt controller i.e.
+ * group0 or group1.
+ ******************************************************************************/
+uint32_t arm_gic_get_interrupt_type(uint32_t id)
+{
+ uint32_t group;
+
+ assert(g_gicd_base);
+ group = gicd_get_igroupr(g_gicd_base, id);
+
+ /* Assume that all secure interrupts are S-EL1 interrupts */
+ if (group == GRP0)
+ return INTR_TYPE_S_EL1;
+ else
+ return INTR_TYPE_NS;
+}
+
+#else
+#error "Invalid ARM GIC architecture version specified for platform port"
+#endif /* ARM_GIC_ARCH */
--- /dev/null
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARM_GIC_H__
+#define __ARM_GIC_H__
+
+#include <stdint.h>
+
+/*******************************************************************************
+ * Function declarations
+ ******************************************************************************/
+void arm_gic_init(unsigned int gicc_base,
+ unsigned int gicd_base,
+ unsigned long gicr_base,
+ const unsigned int *irq_sec_ptr,
+ unsigned int num_irqs);
+void arm_gic_setup(void);
+void arm_gic_cpuif_deactivate(void);
+void arm_gic_cpuif_setup(void);
+void arm_gic_pcpu_distif_setup(void);
+
+uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
+ uint32_t security_state);
+uint32_t arm_gic_get_pending_interrupt_type(void);
+uint32_t arm_gic_get_pending_interrupt_id(void);
+uint32_t arm_gic_acknowledge_interrupt(void);
+void arm_gic_end_of_interrupt(uint32_t id);
+uint32_t arm_gic_get_interrupt_type(uint32_t id);
+
+#endif /* __GIC_H__ */
#define MAX_PPIS 14
#define MAX_SGIS 16
+#define MIN_SGI_ID 0
+#define MIN_PPI_ID 16
+#define MIN_SPI_ID 32
+
#define GRP0 0
#define GRP1 1
#define GIC_PRI_MASK 0xff
--- /dev/null
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arm_gic.h>
+
+/*
+ * The following platform GIC functions are weakly defined. They
+ * provide typical implementations that may be re-used by multiple
+ * platforms but may also be overridden by a platform if required.
+ */
+#pragma weak plat_ic_get_pending_interrupt_id
+#pragma weak plat_ic_get_pending_interrupt_type
+#pragma weak plat_ic_acknowledge_interrupt
+#pragma weak plat_ic_get_interrupt_type
+#pragma weak plat_ic_end_of_interrupt
+#pragma weak plat_interrupt_type_to_line
+
+uint32_t plat_ic_get_pending_interrupt_id(void)
+{
+ return arm_gic_get_pending_interrupt_id();
+}
+
+uint32_t plat_ic_get_pending_interrupt_type(void)
+{
+ return arm_gic_get_pending_interrupt_type();
+}
+
+uint32_t plat_ic_acknowledge_interrupt(void)
+{
+ return arm_gic_acknowledge_interrupt();
+}
+
+uint32_t plat_ic_get_interrupt_type(uint32_t id)
+{
+ return arm_gic_get_interrupt_type(id);
+}
+
+void plat_ic_end_of_interrupt(uint32_t id)
+{
+ arm_gic_end_of_interrupt(id);
+}
+
+uint32_t plat_interrupt_type_to_line(uint32_t type,
+ uint32_t security_state)
+{
+ return arm_gic_interrupt_type_to_line(type, security_state);
+}
#include <arch.h>
#include <arch_helpers.h>
+#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <cci400.h>
{0}
};
+/* Array of secure interrupts to be configured by the gic driver */
+const unsigned int irq_sec_array[] = {
+ IRQ_TZ_WDOG,
+ IRQ_SEC_PHY_TIMER,
+ IRQ_SEC_SGI_0,
+ IRQ_SEC_SGI_1,
+ IRQ_SEC_SGI_2,
+ IRQ_SEC_SGI_3,
+ IRQ_SEC_SGI_4,
+ IRQ_SEC_SGI_5,
+ IRQ_SEC_SGI_6,
+ IRQ_SEC_SGI_7
+};
+
+const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
+ sizeof(irq_sec_array[0]);
+
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
* the platform memory map & initialize the mmu, for the given exception level
cci_enable_coherency(read_mpidr());
}
+void fvp_gic_init(void)
+{
+ arm_gic_init(plat_config.gicc_base,
+ plat_config.gicd_base,
+ BASE_GICR_BASE,
+ irq_sec_array,
+ num_sec_irqs);
+}
+
/*******************************************************************************
* Gets SPSR for BL32 entry
#include <arch.h>
#include <arch_helpers.h>
+#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <bl31.h>
unsigned int reg_val;
/* Initialize the gic cpu and distributor interfaces */
- gic_setup();
+ fvp_gic_init();
+ arm_gic_setup();
/*
* TODO: Configure the CLCD before handing control to
******************************************************************************/
void bl32_platform_setup(void)
{
-
+ fvp_gic_init();
}
/*******************************************************************************
+++ /dev/null
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <bl_common.h>
-#include <debug.h>
-#include <gic_v2.h>
-#include <gic_v3.h>
-#include <interrupt_mgmt.h>
-#include <platform.h>
-#include <plat_config.h>
-#include <stdint.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
-
-/*******************************************************************************
- * This function does some minimal GICv3 configuration. The Firmware itself does
- * not fully support GICv3 at this time and relies on GICv2 emulation as
- * provided by GICv3. This function allows software (like Linux) in later stages
- * to use full GICv3 features.
- ******************************************************************************/
-void gicv3_cpuif_setup(void)
-{
- unsigned int scr_val, val;
- uintptr_t base;
-
- /*
- * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
- * bit set. In order to allow interrupts to get routed to the CPU we
- * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
- * to clear (GICv3 Architecture specification 5.4.23).
- * GICR_WAKER is NOT banked per CPU, compute the correct base address
- * per CPU.
- */
- base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr());
- if (base == (uintptr_t)NULL) {
- /* No re-distributor base address. This interface cannot be
- * configured.
- */
- panic();
- }
-
- val = gicr_read_waker(base);
-
- val &= ~WAKER_PS;
- gicr_write_waker(base, val);
- dsb();
-
- /* We need to wait for ChildrenAsleep to clear. */
- val = gicr_read_waker(base);
- while (val & WAKER_CA) {
- val = gicr_read_waker(base);
- }
-
- /*
- * We need to set SCR_EL3.NS in order to see GICv3 non-secure state.
- * Restore SCR_EL3.NS again before exit.
- */
- scr_val = read_scr();
- write_scr(scr_val | SCR_NS_BIT);
- isb(); /* ensure NS=1 takes effect before accessing ICC_SRE_EL2 */
-
- /*
- * By default EL2 and NS-EL1 software should be able to enable GICv3
- * System register access without any configuration at EL3. But it turns
- * out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So
- * we need to set it here again. In order to do that we need to enable
- * register access. We leave it enabled as it should be fine and might
- * prevent problems with later software trying to access GIC System
- * Registers.
- */
- val = read_icc_sre_el3();
- write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
-
- val = read_icc_sre_el2();
- write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE);
-
- write_icc_pmr_el1(GIC_PRI_MASK);
- isb(); /* commite ICC_* changes before setting NS=0 */
-
- /* Restore SCR_EL3 */
- write_scr(scr_val);
- isb(); /* ensure NS=0 takes effect immediately */
-}
-
-/*******************************************************************************
- * This function does some minimal GICv3 configuration when cores go
- * down.
- ******************************************************************************/
-void gicv3_cpuif_deactivate(void)
-{
- unsigned int val;
- uintptr_t base;
-
- /*
- * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
- * wait for GICR_WAKER.ChildrenAsleep to get set.
- * (GICv3 Architecture specification 5.4.23).
- * GICR_WAKER is NOT banked per CPU, compute the correct base address
- * per CPU.
- */
- base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr());
- if (base == (uintptr_t)NULL) {
- /* No re-distributor base address. This interface cannot be
- * configured.
- */
- panic();
- }
-
- val = gicr_read_waker(base);
- val |= WAKER_PS;
- gicr_write_waker(base, val);
- dsb();
-
- /* We need to wait for ChildrenAsleep to set. */
- val = gicr_read_waker(base);
- while ((val & WAKER_CA) == 0) {
- val = gicr_read_waker(base);
- }
-}
-
-
-/*******************************************************************************
- * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
- * and set the priority mask register to allow all interrupts to trickle in.
- ******************************************************************************/
-void gic_cpuif_setup(unsigned int gicc_base)
-{
- unsigned int val;
-
- val = gicc_read_iidr(gicc_base);
-
- /*
- * If GICv3 we need to do a bit of additional setup. We want to
- * allow default GICv2 behaviour but allow the next stage to
- * enable full gicv3 features.
- */
- if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
- gicv3_cpuif_setup();
- }
-
- val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
- val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
-
- gicc_write_pmr(gicc_base, GIC_PRI_MASK);
- gicc_write_ctlr(gicc_base, val);
-}
-
-/*******************************************************************************
- * Place the cpu interface in a state where it can never make a cpu exit wfi as
- * as result of an asserted interrupt. This is critical for powering down a cpu
- ******************************************************************************/
-void gic_cpuif_deactivate(unsigned int gicc_base)
-{
- unsigned int val;
-
- /* Disable secure, non-secure interrupts and disable their bypass */
- val = gicc_read_ctlr(gicc_base);
- val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
- val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
- val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
- gicc_write_ctlr(gicc_base, val);
-
- val = gicc_read_iidr(gicc_base);
-
- /*
- * If GICv3 we need to do a bit of additional setup. Make sure the
- * RDIST is put to sleep.
- */
- if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
- gicv3_cpuif_deactivate();
- }
-}
-
-/*******************************************************************************
- * Per cpu gic distributor setup which will be done by all cpus after a cold
- * boot/hotplug. This marks out the secure interrupts & enables them.
- ******************************************************************************/
-void gic_pcpu_distif_setup(unsigned int gicd_base)
-{
- gicd_write_igroupr(gicd_base, 0, ~0);
-
- gicd_clr_igroupr(gicd_base, IRQ_SEC_PHY_TIMER);
- gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_0);
- gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_1);
- gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_2);
- gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_3);
- gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_4);
- gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_5);
- gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_6);
- gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_7);
-
- gicd_set_ipriorityr(gicd_base, IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY);
-
- gicd_set_isenabler(gicd_base, IRQ_SEC_PHY_TIMER);
- gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_0);
- gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_1);
- gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_2);
- gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_3);
- gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_4);
- gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_5);
- gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_6);
- gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_7);
-}
-
-/*******************************************************************************
- * Global gic distributor setup which will be done by the primary cpu after a
- * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
- * then enables the secure GIC distributor interface.
- ******************************************************************************/
-void gic_distif_setup(unsigned int gicd_base)
-{
- unsigned int ctr, num_ints, ctlr;
-
- /* Disable the distributor before going further */
- ctlr = gicd_read_ctlr(gicd_base);
- ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
- gicd_write_ctlr(gicd_base, ctlr);
-
- /*
- * Mark out non-secure interrupts. Calculate number of
- * IGROUPR registers to consider. Will be equal to the
- * number of IT_LINES
- */
- num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
- num_ints++;
- for (ctr = 0; ctr < num_ints; ctr++)
- gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0);
-
- /* Configure secure interrupts now */
- gicd_clr_igroupr(gicd_base, IRQ_TZ_WDOG);
- gicd_set_ipriorityr(gicd_base, IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG,
- platform_get_core_pos(read_mpidr()));
- gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG);
- gic_pcpu_distif_setup(gicd_base);
-
- gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0);
-}
-
-void gic_setup(void)
-{
- gic_cpuif_setup(get_plat_config()->gicc_base);
- gic_distif_setup(get_plat_config()->gicd_base);
-}
-
-/*******************************************************************************
- * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
- * The interrupt controller knows which pin/line it uses to signal a type of
- * interrupt. The platform knows which interrupt controller type is being used
- * in a particular security state e.g. with an ARM GIC, normal world could use
- * the GICv2 features while the secure world could use GICv3 features and vice
- * versa.
- * This function is exported by the platform to let the interrupt management
- * framework determine for a type of interrupt and security state, which line
- * should be used in the SCR_EL3 to control its routing to EL3. The interrupt
- * line is represented as the bit position of the IRQ or FIQ bit in the SCR_EL3.
- ******************************************************************************/
-uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
-{
- uint32_t gicc_base = get_plat_config()->gicc_base;
-
- assert(type == INTR_TYPE_S_EL1 ||
- type == INTR_TYPE_EL3 ||
- type == INTR_TYPE_NS);
-
- assert(security_state == NON_SECURE || security_state == SECURE);
-
- /*
- * We ignore the security state parameter under the assumption that
- * both normal and secure worlds are using ARM GICv2. This parameter
- * will be used when the secure world starts using GICv3.
- */
-#if FVP_GIC_ARCH == 2
- return gicv2_interrupt_type_to_line(gicc_base, type);
-#else
-#error "Invalid GIC architecture version specified for FVP port"
-#endif
-}
-
-#if FVP_GIC_ARCH == 2
-/*******************************************************************************
- * This function returns the type of the highest priority pending interrupt at
- * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
- * interrupt pending.
- ******************************************************************************/
-uint32_t plat_ic_get_pending_interrupt_type(void)
-{
- uint32_t id;
-
- id = gicc_read_hppir(get_plat_config()->gicc_base);
-
- /* Assume that all secure interrupts are S-EL1 interrupts */
- if (id < 1022)
- return INTR_TYPE_S_EL1;
-
- if (id == GIC_SPURIOUS_INTERRUPT)
- return INTR_TYPE_INVAL;
-
- return INTR_TYPE_NS;
-}
-
-/*******************************************************************************
- * This function returns the id of the highest priority pending interrupt at
- * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
- * interrupt pending.
- ******************************************************************************/
-uint32_t plat_ic_get_pending_interrupt_id(void)
-{
- uint32_t id, gicc_base;
-
- gicc_base = get_plat_config()->gicc_base;
- id = gicc_read_hppir(gicc_base);
-
- if (id < 1022)
- return id;
-
- if (id == 1023)
- return INTR_ID_UNAVAILABLE;
-
- /*
- * Find out which non-secure interrupt it is under the assumption that
- * the GICC_CTLR.AckCtl bit is 0.
- */
- return gicc_read_ahppir(gicc_base);
-}
-
-/*******************************************************************************
- * This functions reads the GIC cpu interface Interrupt Acknowledge register
- * to start handling the pending interrupt. It returns the contents of the IAR.
- ******************************************************************************/
-uint32_t plat_ic_acknowledge_interrupt(void)
-{
- return gicc_read_IAR(get_plat_config()->gicc_base);
-}
-
-/*******************************************************************************
- * This functions writes the GIC cpu interface End Of Interrupt register with
- * the passed value to finish handling the active interrupt
- ******************************************************************************/
-void plat_ic_end_of_interrupt(uint32_t id)
-{
- gicc_write_EOIR(get_plat_config()->gicc_base, id);
- return;
-}
-
-/*******************************************************************************
- * This function returns the type of the interrupt id depending upon the group
- * this interrupt has been configured under by the interrupt controller i.e.
- * group0 or group1.
- ******************************************************************************/
-uint32_t plat_ic_get_interrupt_type(uint32_t id)
-{
- uint32_t group;
-
- group = gicd_get_igroupr(get_plat_config()->gicd_base, id);
-
- /* Assume that all secure interrupts are S-EL1 interrupts */
- if (group == GRP0)
- return INTR_TYPE_S_EL1;
- else
- return INTR_TYPE_NS;
-}
-
-#else
-#error "Invalid GIC architecture version specified for FVP port"
-#endif
*/
#include <arch_helpers.h>
+#include <arm_gic.h>
#include <assert.h>
#include <bakery_lock.h>
#include <cci400.h>
unsigned int state)
{
int rc = PSCI_E_SUCCESS;
- unsigned int gicc_base, ectlr;
+ unsigned int ectlr;
switch (afflvl) {
case MPIDR_AFFLVL1:
* Prevent interrupts from spuriously waking up
* this cpu
*/
- gicc_base = get_plat_config()->gicc_base;
- gic_cpuif_deactivate(gicc_base);
+ arm_gic_cpuif_deactivate();
/*
* Program the power controller to power this
unsigned int state)
{
int rc = PSCI_E_SUCCESS;
- unsigned int gicc_base, ectlr;
+ unsigned int ectlr;
unsigned long linear_id;
mailbox_t *fvp_mboxes;
* Prevent interrupts from spuriously waking up
* this cpu
*/
- gicc_base = get_plat_config()->gicc_base;
- gic_cpuif_deactivate(gicc_base);
+ arm_gic_cpuif_deactivate();
/*
* Program the power controller to power this
int rc = PSCI_E_SUCCESS;
unsigned long linear_id;
mailbox_t *fvp_mboxes;
- unsigned int gicd_base, gicc_base, ectlr;
+ unsigned int ectlr;
switch (afflvl) {
sizeof(unsigned long));
/* Enable the gic cpu interface */
- gicc_base = get_plat_config()->gicc_base;
- gic_cpuif_setup(gicc_base);
+ arm_gic_cpuif_setup();
/* TODO: This setup is needed only after a cold boot */
- gicd_base = get_plat_config()->gicd_base;
- gic_pcpu_distif_setup(gicd_base);
+ arm_gic_pcpu_distif_setup();
break;
void fvp_cci_setup(void);
-/* Declarations for fvp_gic.c */
-void gic_cpuif_deactivate(unsigned int);
-void gic_cpuif_setup(unsigned int);
-void gic_pcpu_distif_setup(unsigned int);
-void gic_setup(void);
+void fvp_gic_init(void);
/* Declarations for fvp_topology.c */
int fvp_setup_topology(void);
plat/fvp/aarch64/fvp_common.c
BL31_SOURCES += drivers/arm/cci400/cci400.c \
+ drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
drivers/arm/tzc400/tzc400.c \
+ plat/common/plat_gic.c \
plat/common/aarch64/platform_mp_stack.S \
plat/fvp/bl31_fvp_setup.c \
- plat/fvp/fvp_gic.c \
plat/fvp/fvp_pm.c \
plat/fvp/fvp_security.c \
plat/fvp/fvp_topology.c \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/drivers/pwrc/fvp_pwrc.c
-# Flag used by the FVP port to determine the version of ARM GIC architecture
-# to use for interrupt management in EL3.
-FVP_GIC_ARCH := 2
-$(eval $(call add_define,FVP_GIC_ARCH))
+# Flag used by the platform port to determine the version of ARM GIC
+# architecture to use for interrupt management in EL3.
+ARM_GIC_ARCH := 2
+$(eval $(call add_define,ARM_GIC_ARCH))
projects / project / bcm63xx / atf.git / commitdiff