Juno R2: Configure the correct L2 RAM latency values

The default reset values for the L2 Data & Tag RAM latencies on the
Cortex-A72 on Juno R2 are not suitable. This patch modifies
the Juno platform reset handler to configure the right settings
on Juno R2.

Change-Id: I20953de7ba0619324a389e0b7bbf951b64057db8

diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index bb32f9b97e96e525d62a7d09347f80e3d5c997c8..fa10ca90254660317a190e5e24c257863d008da2 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -62,6 +62,7 @@
 #define L2CTLR_TAG_RAM_LATENCY_SHIFT   6
 
 #define L2_DATA_RAM_LATENCY_3_CYCLES   0x2
+#define L2_TAG_RAM_LATENCY_2_CYCLES    0x1
 #define L2_TAG_RAM_LATENCY_3_CYCLES    0x2
 
 #endif /* __CORTEX_A72_H__ */

diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S
index ab06da2048ac6247f05a67408d42d39a1a23c226..1931535e74b466a8d977922a00c897b6f61a101c 100644 (file)
--- a/plat/arm/board/juno/aarch64/juno_helpers.S
+++ b/plat/arm/board/juno/aarch64/juno_helpers.S
@@ -33,6 +33,7 @@
 #include <bl_common.h>
 #include <cortex_a53.h>
 #include <cortex_a57.h>
+#include <cortex_a72.h>
 #include <v2m_def.h>
 #include "../juno_def.h"
 
@@ -153,10 +154,31 @@ endfunc JUNO_HANDLER(1)
         * - Quad core Cortex-A53 processor cluster;
         * - Dual core Cortex-A72 processor cluster.
         *
-        * This handler does nothing.
+        * This handler does the following:
+        * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
+        * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72
+        *
+        * Note that:
+        * - Defect #831273 doesn't affect Juno R2.
         * --------------------------------------------------------------------
         */
 func JUNO_HANDLER(2)
+       /* --------------------------------------------------------------------
+        * Nothing to do on Cortex-A53.
+        * --------------------------------------------------------------------
+        */
+       jump_if_cpu_midr CORTEX_A72_MIDR, A72
+       ret
+
+A72:
+       /* --------------------------------------------------------------------
+        * Cortex-A72 specific settings
+        * --------------------------------------------------------------------
+        */
+       mov     x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
+                     (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
+       msr     L2CTLR_EL1, x0
+       isb
        ret
 endfunc JUNO_HANDLER(2)