ARM: Add platform support for LSI AXM55xx SoC
authorAnders Berg <anders.berg@lsi.com>
Fri, 23 May 2014 09:08:35 +0000 (11:08 +0200)
committerArnd Bergmann <arnd@arndb.de>
Fri, 23 May 2014 16:18:39 +0000 (18:18 +0200)
The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15
cores (in a 4x4 cluster configuration). The cores within each cluster share an
L2 cache, and the clusters are connected to each other via a CCN-504 cache
coherent interconnect.

This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located
above 4GB in the memory map.

Signed-off-by: Anders Berg <anders.berg@lsi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Documentation/devicetree/bindings/arm/axxia.txt [new file with mode: 0644]
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/mach-axxia/Kconfig [new file with mode: 0644]
arch/arm/mach-axxia/Makefile [new file with mode: 0644]
arch/arm/mach-axxia/axxia.c [new file with mode: 0644]
arch/arm/mach-axxia/platsmp.c [new file with mode: 0644]
include/dt-bindings/clock/lsi,axm5516-clks.h [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/arm/axxia.txt b/Documentation/devicetree/bindings/arm/axxia.txt
new file mode 100644 (file)
index 0000000..7b4ef9c
--- /dev/null
@@ -0,0 +1,12 @@
+Axxia AXM55xx device tree bindings
+
+Boards using the AXM55xx SoC need to have the following properties:
+
+Required root node property:
+
+  - compatible = "lsi,axm5516"
+
+Boards:
+
+  LSI AXM5516 Validation board (Amarillo)
+       compatible = "lsi,axm5516-amarillo", "lsi,axm5516"
index ab438cb5af5570f5aae9b3215b9c73586ce80427..1f8651a3a16e891a3b184eaa08916e40b9d2b210 100644 (file)
@@ -950,6 +950,8 @@ source "arch/arm/mach-mvebu/Kconfig"
 
 source "arch/arm/mach-at91/Kconfig"
 
+source "arch/arm/mach-axxia/Kconfig"
+
 source "arch/arm/mach-bcm/Kconfig"
 
 source "arch/arm/mach-berlin/Kconfig"
index 41c1931f01552589e7939a9e8d95a9d3ad94bf53..6721fab13734daca10fd1d4050c196c7004fab84 100644 (file)
@@ -138,10 +138,12 @@ endif
 textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)            += at91
+machine-$(CONFIG_ARCH_AXXIA)           += axxia
 machine-$(CONFIG_ARCH_BCM)             += bcm
 machine-$(CONFIG_ARCH_BERLIN)          += berlin
 machine-$(CONFIG_ARCH_CLPS711X)                += clps711x
diff --git a/arch/arm/mach-axxia/Kconfig b/arch/arm/mach-axxia/Kconfig
new file mode 100644 (file)
index 0000000..8be7e0a
--- /dev/null
@@ -0,0 +1,16 @@
+config ARCH_AXXIA
+       bool "LSI Axxia platforms" if (ARCH_MULTI_V7 && ARM_LPAE)
+       select ARCH_DMA_ADDR_T_64BIT
+       select ARM_AMBA
+       select ARM_GIC
+       select ARM_TIMER_SP804
+       select HAVE_ARM_ARCH_TIMER
+       select MFD_SYSCON
+       select MIGHT_HAVE_PCI
+       select PCI_DOMAINS if PCI
+       select ZONE_DMA
+       help
+         This enables support for the LSI Axxia devices.
+
+         The LSI Axxia platforms require a Flattened Device Tree to be passed
+         to the kernel.
diff --git a/arch/arm/mach-axxia/Makefile b/arch/arm/mach-axxia/Makefile
new file mode 100644 (file)
index 0000000..ec4f68b
--- /dev/null
@@ -0,0 +1,2 @@
+obj-y                          += axxia.o
+obj-$(CONFIG_SMP)              += platsmp.o
diff --git a/arch/arm/mach-axxia/axxia.c b/arch/arm/mach-axxia/axxia.c
new file mode 100644 (file)
index 0000000..19e5a1d
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * Support for the LSI Axxia SoC devices based on ARM cores.
+ *
+ * Copyright (C) 2012 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <asm/mach/arch.h>
+
+static const char *axxia_dt_match[] __initconst = {
+       "lsi,axm5516",
+       "lsi,axm5516-sim",
+       "lsi,axm5516-emu",
+       NULL
+};
+
+DT_MACHINE_START(AXXIA_DT, "LSI Axxia AXM55XX")
+       .dt_compat = axxia_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
new file mode 100644 (file)
index 0000000..959d4df
--- /dev/null
@@ -0,0 +1,89 @@
+/*
+ * linux/arch/arm/mach-axxia/platsmp.c
+ *
+ * Copyright (C) 2012 LSI Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+
+/* Syscon register offsets for releasing cores from reset */
+#define SC_CRIT_WRITE_KEY      0x1000
+#define SC_RST_CPU_HOLD                0x1010
+
+/*
+ * Write the kernel entry point for secondary CPUs to the specified address
+ */
+static void write_release_addr(u32 release_phys)
+{
+       u32 *virt = (u32 *) phys_to_virt(release_phys);
+       writel_relaxed(virt_to_phys(secondary_startup), virt);
+       /* Make sure this store is visible to other CPUs */
+       smp_wmb();
+       __cpuc_flush_dcache_area(virt, sizeof(u32));
+}
+
+static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+       struct device_node *syscon_np;
+       void __iomem *syscon;
+       u32 tmp;
+
+       syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon");
+       if (!syscon_np)
+               return -ENOENT;
+
+       syscon = of_iomap(syscon_np, 0);
+       if (!syscon)
+               return -ENOMEM;
+
+       tmp = readl(syscon + SC_RST_CPU_HOLD);
+       writel(0xab, syscon + SC_CRIT_WRITE_KEY);
+       tmp &= ~(1 << cpu);
+       writel(tmp, syscon + SC_RST_CPU_HOLD);
+
+       return 0;
+}
+
+static void __init axxia_smp_prepare_cpus(unsigned int max_cpus)
+{
+       int cpu_count = 0;
+       int cpu;
+
+       /*
+        * Initialise the present map, which describes the set of CPUs actually
+        * populated at the present time.
+        */
+       for_each_possible_cpu(cpu) {
+               struct device_node *np;
+               u32 release_phys;
+
+               np = of_get_cpu_node(cpu, NULL);
+               if (!np)
+                       continue;
+               if (of_property_read_u32(np, "cpu-release-addr", &release_phys))
+                       continue;
+
+               if (cpu_count < max_cpus) {
+                       set_cpu_present(cpu, true);
+                       cpu_count++;
+               }
+
+               if (release_phys != 0)
+                       write_release_addr(release_phys);
+       }
+}
+
+static struct smp_operations axxia_smp_ops __initdata = {
+       .smp_prepare_cpus       = axxia_smp_prepare_cpus,
+       .smp_boot_secondary     = axxia_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(axxia_smp, "lsi,syscon-release", &axxia_smp_ops);
diff --git a/include/dt-bindings/clock/lsi,axm5516-clks.h b/include/dt-bindings/clock/lsi,axm5516-clks.h
new file mode 100644 (file)
index 0000000..beb41ac
--- /dev/null
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2014 LSI Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AXM5516_H
+#define _DT_BINDINGS_CLK_AXM5516_H
+
+#define AXXIA_CLK_FAB_PLL      0
+#define AXXIA_CLK_CPU_PLL      1
+#define AXXIA_CLK_SYS_PLL      2
+#define AXXIA_CLK_SM0_PLL      3
+#define AXXIA_CLK_SM1_PLL      4
+#define AXXIA_CLK_FAB_DIV      5
+#define AXXIA_CLK_SYS_DIV      6
+#define AXXIA_CLK_NRCP_DIV     7
+#define AXXIA_CLK_CPU0_DIV     8
+#define AXXIA_CLK_CPU1_DIV     9
+#define AXXIA_CLK_CPU2_DIV     10
+#define AXXIA_CLK_CPU3_DIV     11
+#define AXXIA_CLK_PER_DIV      12
+#define AXXIA_CLK_MMC_DIV      13
+#define AXXIA_CLK_FAB          14
+#define AXXIA_CLK_SYS          15
+#define AXXIA_CLK_NRCP         16
+#define AXXIA_CLK_CPU0         17
+#define AXXIA_CLK_CPU1         18
+#define AXXIA_CLK_CPU2         19
+#define AXXIA_CLK_CPU3         20
+#define AXXIA_CLK_PER          21
+#define AXXIA_CLK_MMC          22
+
+#endif