net/mlx5: Export ipsec capabilities
authorAviad Yehezkel <aviadye@mellanox.com>
Mon, 29 Jan 2018 13:05:50 +0000 (15:05 +0200)
committerSaeed Mahameed <saeedm@mellanox.com>
Wed, 7 Mar 2018 23:54:30 +0000 (15:54 -0800)
We will need that for ipsec verbs.

Signed-off-by: Aviad Yehezkel <aviadye@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c
drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c
include/linux/mlx5/accel.h [new file with mode: 0644]

index b88ae12d906675272a260d59b296ec33cea775db..375ba438e7cff34e90e286e14ee47b0908a8109a 100644 (file)
@@ -45,7 +45,7 @@ void *mlx5_accel_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev,
        if (!MLX5_IPSEC_DEV(mdev))
                return ERR_PTR(-EOPNOTSUPP);
 
-       if (mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_V2_CMD)
+       if (mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_V2_CMD)
                cmd_size = sizeof(*cmd);
        else
                cmd_size = sizeof(cmd->ipsec_sa_v1);
@@ -62,6 +62,7 @@ u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev)
 {
        return mlx5_fpga_ipsec_device_caps(mdev);
 }
+EXPORT_SYMBOL_GPL(mlx5_accel_ipsec_device_caps);
 
 unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev)
 {
index 14a2e95e82c310a5e3b863f1d48a22d1ba811096..421ed71a029bbbfec7c587397f766bf84f1ef7c8 100644 (file)
 #define __MLX5_ACCEL_IPSEC_H__
 
 #include <linux/mlx5/driver.h>
+#include <linux/mlx5/accel.h>
 
 #ifdef CONFIG_MLX5_ACCEL
 
-enum {
-       MLX5_ACCEL_IPSEC_DEVICE = BIT(1),
-       MLX5_ACCEL_IPSEC_IPV6 = BIT(2),
-       MLX5_ACCEL_IPSEC_ESP = BIT(3),
-       MLX5_ACCEL_IPSEC_LSO = BIT(4),
-       MLX5_ACCEL_IPSEC_NO_TRAILER = BIT(5),
-       MLX5_ACCEL_IPSEC_V2_CMD = BIT(7),
-};
-
 #define MLX5_IPSEC_SADB_IP_AH       BIT(7)
 #define MLX5_IPSEC_SADB_IP_ESP      BIT(6)
 #define MLX5_IPSEC_SADB_SA_VALID    BIT(5)
@@ -70,7 +62,7 @@ enum mlx5_accel_ipsec_enc_mode {
 };
 
 #define MLX5_IPSEC_DEV(mdev) (mlx5_accel_ipsec_device_caps(mdev) & \
-                             MLX5_ACCEL_IPSEC_DEVICE)
+                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 
 struct mlx5_accel_ipsec_sa_v1 {
        __be32 cmd;
@@ -126,8 +118,6 @@ void *mlx5_accel_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev,
  */
 int mlx5_accel_ipsec_sa_cmd_wait(void *context);
 
-u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
-
 unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev);
 int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
                                   unsigned int count);
index a8c3fe7cff0f5b045efbe3aca1bdf3daa965ae8f..6f4a01620cc366020a145c98e3512e856f4a8f7f 100644 (file)
@@ -242,7 +242,8 @@ static inline int mlx5e_xfrm_validate_state(struct xfrm_state *x)
                return -EINVAL;
        }
        if (x->props.family == AF_INET6 &&
-           !(mlx5_accel_ipsec_device_caps(priv->mdev) & MLX5_ACCEL_IPSEC_IPV6)) {
+           !(mlx5_accel_ipsec_device_caps(priv->mdev) &
+            MLX5_ACCEL_IPSEC_CAP_IPV6)) {
                netdev_info(netdev, "IPv6 xfrm state offload is not supported by this device\n");
                return -EINVAL;
        }
@@ -375,7 +376,7 @@ int mlx5e_ipsec_init(struct mlx5e_priv *priv)
        ipsec->en_priv = priv;
        ipsec->en_priv->ipsec = ipsec;
        ipsec->no_trailer = !!(mlx5_accel_ipsec_device_caps(priv->mdev) &
-                              MLX5_ACCEL_IPSEC_NO_TRAILER);
+                              MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER);
        netdev_dbg(priv->netdev, "IPSec attached to netdevice\n");
        return 0;
 }
@@ -422,7 +423,7 @@ void mlx5e_ipsec_build_netdev(struct mlx5e_priv *priv)
        if (!priv->ipsec)
                return;
 
-       if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_ESP) ||
+       if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_ESP) ||
            !MLX5_CAP_ETH(mdev, swp)) {
                mlx5_core_dbg(mdev, "mlx5e: ESP and SWP offload not supported\n");
                return;
@@ -441,7 +442,7 @@ void mlx5e_ipsec_build_netdev(struct mlx5e_priv *priv)
        netdev->features |= NETIF_F_HW_ESP_TX_CSUM;
        netdev->hw_enc_features |= NETIF_F_HW_ESP_TX_CSUM;
 
-       if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_LSO) ||
+       if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_LSO) ||
            !MLX5_CAP_ETH(mdev, swp_lso)) {
                mlx5_core_dbg(mdev, "mlx5e: ESP LSO not supported\n");
                return;
index fa5b5a0888ecd3c687647343894fc90a27f02322..e7e28277733d3c9253ffbe65354f447f78ba41f5 100644 (file)
@@ -257,7 +257,7 @@ u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev)
        u32 ret = 0;
 
        if (mlx5_fpga_is_ipsec_device(mdev))
-               ret |= MLX5_ACCEL_IPSEC_DEVICE;
+               ret |= MLX5_ACCEL_IPSEC_CAP_DEVICE;
        else
                return ret;
 
@@ -265,19 +265,19 @@ u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev)
                return ret;
 
        if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, esp))
-               ret |= MLX5_ACCEL_IPSEC_ESP;
+               ret |= MLX5_ACCEL_IPSEC_CAP_ESP;
 
        if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, ipv6))
-               ret |= MLX5_ACCEL_IPSEC_IPV6;
+               ret |= MLX5_ACCEL_IPSEC_CAP_IPV6;
 
        if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, lso))
-               ret |= MLX5_ACCEL_IPSEC_LSO;
+               ret |= MLX5_ACCEL_IPSEC_CAP_LSO;
 
        if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, rx_no_trailer))
-               ret |= MLX5_ACCEL_IPSEC_NO_TRAILER;
+               ret |= MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER;
 
        if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, v2_command))
-               ret |= MLX5_ACCEL_IPSEC_V2_CMD;
+               ret |= MLX5_ACCEL_IPSEC_CAP_V2_CMD;
 
        return ret;
 }
@@ -375,7 +375,7 @@ static int mlx5_fpga_ipsec_enable_supported_caps(struct mlx5_core_dev *mdev)
        u32 dev_caps = mlx5_fpga_ipsec_device_caps(mdev);
        u32 flags = 0;
 
-       if (dev_caps & MLX5_ACCEL_IPSEC_NO_TRAILER)
+       if (dev_caps & MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER)
                flags |= MLX5_FPGA_IPSEC_CAP_NO_TRAILER;
 
        return mlx5_fpga_ipsec_set_caps(mdev, flags);
diff --git a/include/linux/mlx5/accel.h b/include/linux/mlx5/accel.h
new file mode 100644 (file)
index 0000000..601280c
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#ifndef __MLX5_ACCEL_H__
+#define __MLX5_ACCEL_H__
+
+#include <linux/mlx5/driver.h>
+
+enum mlx5_accel_ipsec_caps {
+       MLX5_ACCEL_IPSEC_CAP_DEVICE             = 1 << 0,
+       MLX5_ACCEL_IPSEC_CAP_ESP                = 1 << 2,
+       MLX5_ACCEL_IPSEC_CAP_IPV6               = 1 << 3,
+       MLX5_ACCEL_IPSEC_CAP_LSO                = 1 << 4,
+       MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER      = 1 << 5,
+       MLX5_ACCEL_IPSEC_CAP_V2_CMD             = 1 << 6,
+};
+
+#ifdef CONFIG_MLX5_ACCEL
+
+u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
+
+#else
+
+static inline u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; }
+
+#endif
+#endif