drm/amdgpu/dce6: add dce_v6_0_disable_dce

Needed for virtual dce support

Reviewed-By: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index b948d6cb139936670228d6a9e805ecd7fbe9b225..e6a7687dec215d932df0ff75f401067fb5dd64f7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -611,12 +611,55 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
                                          bool render)
 {
-       if (!render) 
+       if (!render)
                WREG32(R_000300_VGA_RENDER_CONTROL,
                        RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
 
 }
 
+static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
+{
+       int num_crtc = 0;
+
+       switch (adev->asic_type) {
+       case CHIP_TAHITI:
+       case CHIP_PITCAIRN:
+       case CHIP_VERDE:
+               num_crtc = 6;
+               break;
+       case CHIP_OLAND:
+               num_crtc = 2;
+               break;
+       default:
+               num_crtc = 0;
+       }
+       return num_crtc;
+}
+
+void dce_v6_0_disable_dce(struct amdgpu_device *adev)
+{
+       /*Disable VGA render and enabled crtc, if has DCE engine*/
+       if (amdgpu_atombios_has_dce_engine_info(adev)) {
+               u32 tmp;
+               int crtc_enabled, i;
+
+               dce_v6_0_set_vga_render_state(adev, false);
+
+               /*Disable crtc*/
+               for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
+                       crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) &
+                               EVERGREEN_CRTC_MASTER_EN;
+                       if (crtc_enabled) {
+                               WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+                               tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+                               tmp &= ~EVERGREEN_CRTC_MASTER_EN;
+                               WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
+                               WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+                       }
+               }
+       }
+}
+
 static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
 {
 
@@ -2338,21 +2381,20 @@ static int dce_v6_0_early_init(void *handle)
        dce_v6_0_set_display_funcs(adev);
        dce_v6_0_set_irq_funcs(adev);
 
+       adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
+
        switch (adev->asic_type) {
        case CHIP_TAHITI:
        case CHIP_PITCAIRN:
        case CHIP_VERDE:
-               adev->mode_info.num_crtc = 6;
                adev->mode_info.num_hpd = 6;
                adev->mode_info.num_dig = 6;
                break;
        case CHIP_OLAND:
-               adev->mode_info.num_crtc = 2;
                adev->mode_info.num_hpd = 2;
                adev->mode_info.num_dig = 2;
                break;
        default:
-               /* FIXME: not supported yet */
                return -EINVAL;
        }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
index 6a5528105bb652543c1aa02ea2c2fcf08e4e4823..4c6cd18e9053d7d3cfe2669870d4a1394c76b67f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
@@ -26,4 +26,6 @@
 
 extern const struct amd_ip_funcs dce_v6_0_ip_funcs;
 
+void dce_v6_0_disable_dce(struct amdgpu_device *adev);
+
 #endif