clk: ti: Fix dm814x clkctrl for ethernet

We are missing alwon ethernet clock for dm814x and this prevents us
from probing the CPSW with device tree only data. Looks like Ethernet
currently only works if it has been enabled in the bootloader.

Looks like relying on the bootloader clocks is not an issue with the
mainline kernel currently, but it will be an issue when configuring
CPSW Ethernet to probe with device tree data only as we will be managing
the clocks.

Fixes: 26ca2e973844 ("clk: ti: dm814: add clkctrl clock data")
Cc: linux-clk@vger.kernel.org
Cc: Graeme Smecher <gsmecher@threespeedlogic.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi
index e5e4d0affefad2c7705a3fc80ade0b44db6dd577..f7939f43413b9856edd61daed860a0efa883e7f5 100644 (file)
--- a/arch/arm/boot/dts/dm814x-clocks.dtsi
+++ b/arch/arm/boot/dts/dm814x-clocks.dtsi
@@ -362,4 +362,18 @@
                        #clock-cells = <2>;
                };
        };
+
+       alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
+               compatible = "ti,omap4-cm";
+               reg = <0x15d4 0x4>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x15d4 0x4>;
+
+               alwon_ethernet_clkctrl: clk@0 {
+                       compatible = "ti,clkctrl";
+                       reg = <0 0x4>;
+                       #clock-cells = <2>;
+               };
+       };
 };

diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c
index 087cfa75ac24846d5e9cd37bae040a4c333d49bb..4f8bd34ec1a561c5172af8860d18f7fb22cb0367 100644 (file)
--- a/drivers/clk/ti/clk-814x.c
+++ b/drivers/clk/ti/clk-814x.c
@@ -25,7 +25,6 @@ static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst
        { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
        { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
        { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
-       { DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
        { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
        { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
        { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
@@ -39,9 +38,15 @@ static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst
        { 0 },
 };
 
+static const struct
+omap_clkctrl_reg_data dm814_alwon_ethernet_clkctrl_regs[] __initconst = {
+       { 0, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
+};
+
 const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
        { 0x48180500, dm814_default_clkctrl_regs },
        { 0x48181400, dm814_alwon_clkctrl_regs },
+       { 0x481815d4, dm814_alwon_ethernet_clkctrl_regs },
        { 0 },
 };
 

diff --git a/include/dt-bindings/clock/dm814.h b/include/dt-bindings/clock/dm814.h
index f0f04e0a249ec9c9040b88c59c4900c079cf33d7..33b8826d936bc1675d2e579ec459fbc71cc9c2ae 100644 (file)
--- a/include/dt-bindings/clock/dm814.h
+++ b/include/dt-bindings/clock/dm814.h
@@ -34,4 +34,9 @@
 #define DM814_MMC2_CLKCTRL     DM814_CLKCTRL_INDEX(0x220)
 #define DM814_MMC3_CLKCTRL     DM814_CLKCTRL_INDEX(0x224)
 
+/* alwon_ethernet clocks */
+#define DM814_ETHERNET_CLKCTRL_OFFSET  0x1d4
+#define DM814_ETHERNET_CLKCTRL_INDEX(offset)   ((offset) - DM814_ETHERNET_CLKCTRL_OFFSET)
+#define DM814_ETHERNET_CPGMAC0_CLKCTRL DM814_ETHERNET_CLKCTRL_INDEX(0x1d4)
+
 #endif