drm/msm/gpu: Remove unused bus scaling code
authorJordan Crouse <jcrouse@codeaurora.org>
Tue, 21 Nov 2017 19:40:53 +0000 (12:40 -0700)
committerRob Clark <robdclark@gmail.com>
Wed, 10 Jan 2018 13:58:42 +0000 (08:58 -0500)
Remove the downstream bus scaling code. It isn't needed for for
compatibility with a downstream or vendor kernel. Get it out of the
way to clear space for devfreq support.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/adreno/adreno_gpu.c
drivers/gpu/drm/msm/adreno/adreno_gpu.h
drivers/gpu/drm/msm/msm_gpu.c
drivers/gpu/drm/msm/msm_gpu.h

index 2f0610f8fc8d21d4da72aa80cca9a5a98b10d92e..61e3091fada9718a9e65c64da46e5db2425b0146 100644 (file)
@@ -480,13 +480,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
        adreno_gpu->rev = config->rev;
 
        gpu->fast_rate = config->fast_rate;
-       gpu->bus_freq  = config->bus_freq;
-#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
-       gpu->bus_scale_table = config->bus_scale_table;
-#endif
 
-       DBG("fast_rate=%u, slow_rate=27000000, bus_freq=%u",
-                       gpu->fast_rate, gpu->bus_freq);
+       DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
 
        adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
        adreno_gpu_config.irqname = "kgsl_3d0_irq";
index 28e3de6e5f94ac394515ae7b42e31095b67b5893..88d1bdfd9aae11d16dfc2f705b90f58c666111ca 100644 (file)
@@ -129,10 +129,7 @@ struct adreno_gpu {
 /* platform config data (ie. from DT, or pdata) */
 struct adreno_platform_config {
        struct adreno_rev rev;
-       uint32_t fast_rate, bus_freq;
-#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
-       struct msm_bus_scale_pdata *bus_scale_table;
-#endif
+       uint32_t fast_rate;
 };
 
 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
index 6fbc2fc259ce28d77e83ba65e409dd520467009a..5416fe85d8163fdb435f5254bba208dd7c9fd6eb 100644 (file)
  * Power Management:
  */
 
-#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
-#include <mach/board.h>
-static void bs_init(struct msm_gpu *gpu)
-{
-       if (gpu->bus_scale_table) {
-               gpu->bsc = msm_bus_scale_register_client(gpu->bus_scale_table);
-               DBG("bus scale client: %08x", gpu->bsc);
-       }
-}
-
-static void bs_fini(struct msm_gpu *gpu)
-{
-       if (gpu->bsc) {
-               msm_bus_scale_unregister_client(gpu->bsc);
-               gpu->bsc = 0;
-       }
-}
-
-static void bs_set(struct msm_gpu *gpu, int idx)
-{
-       if (gpu->bsc) {
-               DBG("set bus scaling: %d", idx);
-               msm_bus_scale_client_update_request(gpu->bsc, idx);
-       }
-}
-#else
-static void bs_init(struct msm_gpu *gpu) {}
-static void bs_fini(struct msm_gpu *gpu) {}
-static void bs_set(struct msm_gpu *gpu, int idx) {}
-#endif
-
 static int enable_pwrrail(struct msm_gpu *gpu)
 {
        struct drm_device *dev = gpu->dev;
@@ -143,8 +112,6 @@ static int enable_axi(struct msm_gpu *gpu)
 {
        if (gpu->ebi1_clk)
                clk_prepare_enable(gpu->ebi1_clk);
-       if (gpu->bus_freq)
-               bs_set(gpu, gpu->bus_freq);
        return 0;
 }
 
@@ -152,8 +119,6 @@ static int disable_axi(struct msm_gpu *gpu)
 {
        if (gpu->ebi1_clk)
                clk_disable_unprepare(gpu->ebi1_clk);
-       if (gpu->bus_freq)
-               bs_set(gpu, 0);
        return 0;
 }
 
@@ -755,8 +720,6 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
        gpu->pdev = pdev;
        platform_set_drvdata(pdev, gpu);
 
-       bs_init(gpu);
-
        gpu->aspace = msm_gpu_create_address_space(gpu, pdev,
                config->va_start, config->va_end);
 
@@ -826,8 +789,6 @@ void msm_gpu_cleanup(struct msm_gpu *gpu)
 
        WARN_ON(!list_empty(&gpu->active_list));
 
-       bs_fini(gpu);
-
        for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
                msm_ringbuffer_destroy(gpu->rb[i]);
                gpu->rb[i] = NULL;
index e113d64574d3c3cd096100d8d0221952f782f147..0de26b6f3732eea16afc23958048abe3a8e9930f 100644 (file)
@@ -108,12 +108,7 @@ struct msm_gpu {
        struct clk **grp_clks;
        int nr_clocks;
        struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
-       uint32_t fast_rate, bus_freq;
-
-#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
-       struct msm_bus_scale_pdata *bus_scale_table;
-       uint32_t bsc;
-#endif
+       uint32_t fast_rate;
 
        /* Hang and Inactivity Detection:
         */