net: hns3: Modify the order of initializing command queue register

According to hardware's description, the head pointer register should
be written before the tail pointer register while doing command queue
initialization.

Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
index eca4b23fd0a8c5e925b38d3decfaac77c8b34f85..cf40afca66dbe4919b266712088050926e3c87ee 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
@@ -119,8 +119,8 @@ static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring)
                hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG,
                                (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
                                HCLGE_NIC_CMQ_ENABLE);
-               hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0);
                hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0);
+               hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0);
        } else {
                hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG,
                                lower_32_bits(dma));
@@ -129,8 +129,8 @@ static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring)
                hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG,
                                (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
                                HCLGE_NIC_CMQ_ENABLE);
-               hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
                hclge_write_dev(hw, HCLGE_NIC_CRQ_HEAD_REG, 0);
+               hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
        }
 }