drm/i915/dsb: function to trigger workload execution of DSB.

Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.

v1: Initial version.
v2: Optimized code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
v4: reset ins_start_offset after commit. (Jani)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190920115930.27829-8-animesh.manna@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 6fb4529689f1851bd0a9bf2f87191e3c9f529f86..f4c0b37683a5147b6fd9e34e54f241fabf6db3b2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -224,3 +224,46 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
                               (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
                               i915_mmio_reg_offset(reg);
 }
+
+void intel_dsb_commit(struct intel_dsb *dsb)
+{
+       struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+       struct drm_device *dev = crtc->base.dev;
+       struct drm_i915_private *dev_priv = to_i915(dev);
+       enum pipe pipe = crtc->pipe;
+       u32 tail;
+
+       if (!dsb->free_pos)
+               return;
+
+       if (!intel_dsb_enable_engine(dsb))
+               goto reset;
+
+       if (is_dsb_busy(dsb)) {
+               DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n");
+               goto reset;
+       }
+       I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
+
+       tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+       if (tail > dsb->free_pos * 4)
+               memset(&dsb->cmd_buf[dsb->free_pos], 0,
+                      (tail - dsb->free_pos * 4));
+
+       if (is_dsb_busy(dsb)) {
+               DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n");
+               goto reset;
+       }
+       DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
+                     i915_ggtt_offset(dsb->vma), tail);
+       I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
+       if (wait_for(!is_dsb_busy(dsb), 1)) {
+               DRM_ERROR("Timed out waiting for DSB workload completion.\n");
+               goto reset;
+       }
+
+reset:
+       dsb->free_pos = 0;
+       dsb->ins_start_offset = 0;
+       intel_dsb_disable_engine(dsb);
+}

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index e4dd0ab799ec6120901eec552aa31edcb4ef3e0c..6f95c8e909e64f74e642e28366254e71f11577c2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -47,5 +47,6 @@ void intel_dsb_put(struct intel_dsb *dsb);
 void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
 void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
                                 u32 val);
+void intel_dsb_commit(struct intel_dsb *dsb);
 
 #endif

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5fcbaaa8f3c61f806c1105eb229bfb18788f3593..8649a30289631042c66becfbe5b4bba9138d1917 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11702,6 +11702,8 @@ enum skl_power_gate {
 #define _DSBSL_INSTANCE_BASE           0x70B00
 #define DSBSL_INSTANCE(pipe, id)       (_DSBSL_INSTANCE_BASE + \
                                         (pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id)             _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id)             _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
 #define DSB_CTRL(pipe, id)             _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
 #define   DSB_ENABLE                   (1 << 31)
 #define   DSB_STATUS                   (1 << 0)