--- /dev/null
+#!/bin/sh
+#
+# Copyright (C) 2007 OpenWrt.org
+#
+#
+
+do_fixcrc() {
+ mtd fixtrx firmware
+}
+
+case `uname -r` in
+ 3.8* | 3.9* ) do_fixcrc;;
+esac
+
--- /dev/null
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_ARPD is not set
+CONFIG_BCM47XX=y
+CONFIG_BCM47XX_BCMA=y
+CONFIG_BCM47XX_SSB=y
+CONFIG_BCM47XX_WDT=y
+CONFIG_BCMA=y
+CONFIG_BCMA_BLOCKIO=y
+CONFIG_BCMA_DEBUG=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DRIVER_MIPS=y
+CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA_NFLASH=y
+CONFIG_BCMA_SFLASH=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CMDLINE="noinitrd console=ttyS0,115200"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+CONFIG_CPU_MIPSR1=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_FW_CFE=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_SEAD3 is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_BCM47XXSFLASH=y
+CONFIG_MTD_BCM47XX_PARTS=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_BCM47XXNFLASH=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_SM_COMMON is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERCPU_RWSEM=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_RSA is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SSB=y
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_DEBUG=y
+CONFIG_SSB_DRIVER_EXTIF=y
+CONFIG_SSB_DRIVER_GIGE=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_SSB_DRIVER_MIPS=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_EMBEDDED=y
+CONFIG_SSB_PCICORE_HOSTMODE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_SERIAL=y
+CONFIG_SSB_SFLASH=y
+CONFIG_SSB_SPROM=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_UIDGID_CONVERTED=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+# CONFIG_USB_HCD_BCMA is not set
+# CONFIG_USB_HCD_SSB is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+--- a/drivers/mtd/bcm47xxpart.c
++++ b/drivers/mtd/bcm47xxpart.c
+@@ -169,11 +169,12 @@ static int bcm47xxpart_parse(struct mtd_
+ * Assume that partitions end at the beginning of the one they are
+ * followed by.
+ */
+- for (i = 0; i < curr_part - 1; i++)
+- parts[i].size = parts[i + 1].offset - parts[i].offset;
+- if (curr_part > 0)
+- parts[curr_part - 1].size =
+- master->size - parts[curr_part - 1].offset;
++ for (i = 0; i < curr_part; i++) {
++ u64 next_part_offset = (i < curr_part - 1) ?
++ parts[i + 1].offset : master->size;
++
++ parts[i].size = next_part_offset - parts[i].offset;
++ }
+
+ *pparts = parts;
+ return curr_part;
--- /dev/null
+--- a/drivers/mtd/bcm47xxpart.c
++++ b/drivers/mtd/bcm47xxpart.c
+@@ -61,6 +61,8 @@ static int bcm47xxpart_parse(struct mtd_
+ uint32_t offset;
+ uint32_t blocksize = 0x10000;
+ struct trx_header *trx;
++ int trx_part = -1;
++ int last_trx_part = -1;
+
+ /* Alloc */
+ parts = kzalloc(sizeof(struct mtd_partition) * BCM47XXPART_MAX_PARTS,
+@@ -131,6 +133,10 @@ static int bcm47xxpart_parse(struct mtd_
+ if (buf[0x000 / 4] == TRX_MAGIC) {
+ trx = (struct trx_header *)buf;
+
++ trx_part = curr_part;
++ bcm47xxpart_add_part(&parts[curr_part++], "firmware",
++ offset, 0);
++
+ i = 0;
+ /* We have LZMA loader if offset[2] points to sth */
+ if (trx->offset[2]) {
+@@ -154,6 +160,8 @@ static int bcm47xxpart_parse(struct mtd_
+ offset + trx->offset[i], 0);
+ i++;
+
++ last_trx_part = curr_part - 1;
++
+ /*
+ * We have whole TRX scanned, skip to the next part. Use
+ * roundown (not roundup), as the loop will increase
+@@ -174,6 +182,9 @@ static int bcm47xxpart_parse(struct mtd_
+ parts[i + 1].offset : master->size;
+
+ parts[i].size = next_part_offset - parts[i].offset;
++ if (i == last_trx_part && trx_part >= 0)
++ parts[trx_part].size = next_part_offset -
++ parts[trx_part].offset;
+ }
+
+ *pparts = parts;
--- /dev/null
+--- a/drivers/mtd/bcm47xxpart.c
++++ b/drivers/mtd/bcm47xxpart.c
+@@ -59,11 +59,14 @@ static int bcm47xxpart_parse(struct mtd_
+ uint32_t *buf;
+ size_t bytes_read;
+ uint32_t offset;
+- uint32_t blocksize = 0x10000;
++ uint32_t blocksize = master->erasesize;
+ struct trx_header *trx;
+ int trx_part = -1;
+ int last_trx_part = -1;
+
++ if (blocksize <= 0x10000)
++ blocksize = 0x10000;
++
+ /* Alloc */
+ parts = kzalloc(sizeof(struct mtd_partition) * BCM47XXPART_MAX_PARTS,
+ GFP_KERNEL);
--- /dev/null
+--- a/drivers/mtd/bcm47xxpart.c
++++ b/drivers/mtd/bcm47xxpart.c
+@@ -19,12 +19,6 @@
+ /* 10 parts were found on sflash on Netgear WNDR4500 */
+ #define BCM47XXPART_MAX_PARTS 12
+
+-/*
+- * Amount of bytes we read when analyzing each block of flash memory.
+- * Set it big enough to allow detecting partition and reading important data.
+- */
+-#define BCM47XXPART_BYTES_TO_READ 0x404
+-
+ /* Magics */
+ #define BOARD_DATA_MAGIC 0x5246504D /* MPFR */
+ #define POT_MAGIC1 0x54544f50 /* POTT */
+@@ -63,14 +57,17 @@ static int bcm47xxpart_parse(struct mtd_
+ struct trx_header *trx;
+ int trx_part = -1;
+ int last_trx_part = -1;
++ int max_bytes_to_read = 0x8004;
+
+ if (blocksize <= 0x10000)
+ blocksize = 0x10000;
++ if (blocksize == 0x20000)
++ max_bytes_to_read = 0x18004;
+
+ /* Alloc */
+ parts = kzalloc(sizeof(struct mtd_partition) * BCM47XXPART_MAX_PARTS,
+ GFP_KERNEL);
+- buf = kzalloc(BCM47XXPART_BYTES_TO_READ, GFP_KERNEL);
++ buf = kzalloc(max_bytes_to_read, GFP_KERNEL);
+
+ /* Parse block by block looking for magics */
+ for (offset = 0; offset <= master->size - blocksize;
+@@ -85,7 +82,7 @@ static int bcm47xxpart_parse(struct mtd_
+ }
+
+ /* Read beginning of the block */
+- if (mtd_read(master, offset, BCM47XXPART_BYTES_TO_READ,
++ if (mtd_read(master, offset, max_bytes_to_read,
+ &bytes_read, (uint8_t *)buf) < 0) {
+ pr_err("mtd_read error while parsing (offset: 0x%X)!\n",
+ offset);
+@@ -100,9 +97,16 @@ static int bcm47xxpart_parse(struct mtd_
+ }
+
+ /* Standard NVRAM */
+- if (buf[0x000 / 4] == NVRAM_HEADER) {
++ if (buf[0x000 / 4] == NVRAM_HEADER ||
++ buf[0x1000 / 4] == NVRAM_HEADER ||
++ buf[0x8000 / 4] == NVRAM_HEADER ||
++ (blocksize == 0x20000 && (
++ buf[0x10000 / 4] == NVRAM_HEADER ||
++ buf[0x11000 / 4] == NVRAM_HEADER ||
++ buf[0x18000 / 4] == NVRAM_HEADER))) {
+ bcm47xxpart_add_part(&parts[curr_part++], "nvram",
+ offset, 0);
++ offset = rounddown(offset, blocksize);
+ continue;
+ }
+
--- /dev/null
+--- a/drivers/mtd/bcm47xxpart.c
++++ b/drivers/mtd/bcm47xxpart.c
+@@ -58,6 +58,7 @@ static int bcm47xxpart_parse(struct mtd_
+ int trx_part = -1;
+ int last_trx_part = -1;
+ int max_bytes_to_read = 0x8004;
++ bool found_nvram = false;
+
+ if (blocksize <= 0x10000)
+ blocksize = 0x10000;
+@@ -107,6 +108,7 @@ static int bcm47xxpart_parse(struct mtd_
+ bcm47xxpart_add_part(&parts[curr_part++], "nvram",
+ offset, 0);
+ offset = rounddown(offset, blocksize);
++ found_nvram = true;
+ continue;
+ }
+
+@@ -194,6 +196,15 @@ static int bcm47xxpart_parse(struct mtd_
+ parts[trx_part].offset;
+ }
+
++ if (!found_nvram) {
++ pr_err("can not find a nvram partition reserve last block\n");
++ bcm47xxpart_add_part(&parts[curr_part++], "nvram_guess",
++ master->size - blocksize, MTD_WRITEABLE);
++ for (i = 0; i < curr_part; i++) {
++ if (parts[i].size + parts[i].offset == master->size)
++ parts[i].offset -= blocksize;
++ }
++ }
+ *pparts = parts;
+ return curr_part;
+ };
--- /dev/null
+--- a/drivers/mtd/devices/bcm47xxsflash.c
++++ b/drivers/mtd/devices/bcm47xxsflash.c
+@@ -5,6 +5,8 @@
+ #include <linux/platform_device.h>
+ #include <linux/bcma/bcma.h>
+
++#include "bcm47xxsflash.h"
++
+ MODULE_LICENSE("GPL");
+ MODULE_DESCRIPTION("Serial flash driver for BCMA bus");
+
+@@ -13,26 +15,27 @@ static const char *probes[] = { "bcm47xx
+ static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+ {
+- struct bcma_sflash *sflash = mtd->priv;
++ struct bcm47xxsflash *b47s = mtd->priv;
+
+ /* Check address range */
+ if ((from + len) > mtd->size)
+ return -EINVAL;
+
+- memcpy_fromio(buf, (void __iomem *)KSEG0ADDR(sflash->window + from),
++ memcpy_fromio(buf, (void __iomem *)KSEG0ADDR(b47s->window + from),
+ len);
+
+ return len;
+ }
+
+-static void bcm47xxsflash_fill_mtd(struct bcma_sflash *sflash,
+- struct mtd_info *mtd)
++static void bcm47xxsflash_fill_mtd(struct bcm47xxsflash *b47s)
+ {
+- mtd->priv = sflash;
++ struct mtd_info *mtd = &b47s->mtd;
++
++ mtd->priv = b47s;
+ mtd->name = "bcm47xxsflash";
+ mtd->owner = THIS_MODULE;
+ mtd->type = MTD_ROM;
+- mtd->size = sflash->size;
++ mtd->size = b47s->size;
+ mtd->_read = bcm47xxsflash_read;
+
+ /* TODO: implement writing support and verify/change following code */
+@@ -43,16 +46,23 @@ static void bcm47xxsflash_fill_mtd(struc
+ static int bcm47xxsflash_probe(struct platform_device *pdev)
+ {
+ struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
++ struct bcm47xxsflash *b47s;
+ int err;
+
+- sflash->mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
+- if (!sflash->mtd) {
++ b47s = kzalloc(sizeof(*b47s), GFP_KERNEL);
++ if (!b47s) {
+ err = -ENOMEM;
+ goto out;
+ }
+- bcm47xxsflash_fill_mtd(sflash, sflash->mtd);
++ sflash->priv = b47s;
++
++ b47s->window = sflash->window;
++ b47s->blocksize = sflash->blocksize;
++ b47s->numblocks = sflash->numblocks;
++ b47s->size = sflash->size;
++ bcm47xxsflash_fill_mtd(b47s);
+
+- err = mtd_device_parse_register(sflash->mtd, probes, NULL, NULL, 0);
++ err = mtd_device_parse_register(&b47s->mtd, probes, NULL, NULL, 0);
+ if (err) {
+ pr_err("Failed to register MTD device: %d\n", err);
+ goto err_dev_reg;
+@@ -61,7 +71,7 @@ static int bcm47xxsflash_probe(struct pl
+ return 0;
+
+ err_dev_reg:
+- kfree(sflash->mtd);
++ kfree(&b47s->mtd);
+ out:
+ return err;
+ }
+@@ -69,9 +79,10 @@ out:
+ static int bcm47xxsflash_remove(struct platform_device *pdev)
+ {
+ struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
++ struct bcm47xxsflash *b47s = sflash->priv;
+
+- mtd_device_unregister(sflash->mtd);
+- kfree(sflash->mtd);
++ mtd_device_unregister(&b47s->mtd);
++ kfree(b47s);
+
+ return 0;
+ }
+--- /dev/null
++++ b/drivers/mtd/devices/bcm47xxsflash.h
+@@ -0,0 +1,15 @@
++#ifndef __BCM47XXSFLASH_H
++#define __BCM47XXSFLASH_H
++
++#include <linux/mtd/mtd.h>
++
++struct bcm47xxsflash {
++ u32 window;
++ u32 blocksize;
++ u16 numblocks;
++ u32 size;
++
++ struct mtd_info mtd;
++};
++
++#endif /* BCM47XXSFLASH */
+--- a/include/linux/bcma/bcma_driver_chipcommon.h
++++ b/include/linux/bcma/bcma_driver_chipcommon.h
+@@ -528,6 +528,7 @@ struct bcma_sflash {
+ u32 size;
+
+ struct mtd_info *mtd;
++ void *priv;
+ };
+ #endif
+
--- /dev/null
+--- a/drivers/mtd/devices/bcm47xxsflash.c
++++ b/drivers/mtd/devices/bcm47xxsflash.c
+@@ -23,6 +23,7 @@ static int bcm47xxsflash_read(struct mtd
+
+ memcpy_fromio(buf, (void __iomem *)KSEG0ADDR(b47s->window + from),
+ len);
++ *retlen = len;
+
+ return len;
+ }
--- /dev/null
+--- a/drivers/mtd/devices/bcm47xxsflash.c
++++ b/drivers/mtd/devices/bcm47xxsflash.c
+@@ -89,6 +89,7 @@ static int bcm47xxsflash_remove(struct p
+ }
+
+ static struct platform_driver bcma_sflash_driver = {
++ .probe = bcm47xxsflash_probe,
+ .remove = bcm47xxsflash_remove,
+ .driver = {
+ .name = "bcma_sflash",
+@@ -100,7 +101,7 @@ static int __init bcm47xxsflash_init(voi
+ {
+ int err;
+
+- err = platform_driver_probe(&bcma_sflash_driver, bcm47xxsflash_probe);
++ err = platform_driver_register(&bcma_sflash_driver);
+ if (err)
+ pr_err("Failed to register BCMA serial flash driver: %d\n",
+ err);
--- /dev/null
+--- a/drivers/mtd/devices/bcm47xxsflash.c
++++ b/drivers/mtd/devices/bcm47xxsflash.c
+@@ -44,7 +44,11 @@ static void bcm47xxsflash_fill_mtd(struc
+ mtd->writebufsize = mtd->writesize = 1;
+ }
+
+-static int bcm47xxsflash_probe(struct platform_device *pdev)
++/**************************************************
++ * BCMA
++ **************************************************/
++
++static int bcm47xxsflash_bcma_probe(struct platform_device *pdev)
+ {
+ struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
+ struct bcm47xxsflash *b47s;
+@@ -77,7 +81,7 @@ out:
+ return err;
+ }
+
+-static int bcm47xxsflash_remove(struct platform_device *pdev)
++static int bcm47xxsflash_bcma_remove(struct platform_device *pdev)
+ {
+ struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
+ struct bcm47xxsflash *b47s = sflash->priv;
+@@ -89,14 +93,18 @@ static int bcm47xxsflash_remove(struct p
+ }
+
+ static struct platform_driver bcma_sflash_driver = {
+- .probe = bcm47xxsflash_probe,
+- .remove = bcm47xxsflash_remove,
++ .probe = bcm47xxsflash_bcma_probe,
++ .remove = bcm47xxsflash_bcma_remove,
+ .driver = {
+ .name = "bcma_sflash",
+ .owner = THIS_MODULE,
+ },
+ };
+
++/**************************************************
++ * Init
++ **************************************************/
++
+ static int __init bcm47xxsflash_init(void)
+ {
+ int err;
--- /dev/null
+--- a/drivers/mtd/nand/bcm47xxnflash/main.c
++++ b/drivers/mtd/nand/bcm47xxnflash/main.c
+@@ -94,7 +94,8 @@ static int __init bcm47xxnflash_init(voi
+ */
+ err = platform_driver_probe(&bcm47xxnflash_driver, bcm47xxnflash_probe);
+ if (err)
+- pr_err("Failed to register serial flash driver: %d\n", err);
++ pr_err("Failed to register bcm47xx nand flash driver: %d\n",
++ err);
+
+ return err;
+ }
--- /dev/null
+--- a/drivers/mtd/nand/bcm47xxnflash/main.c
++++ b/drivers/mtd/nand/bcm47xxnflash/main.c
+@@ -77,6 +77,7 @@ static int bcm47xxnflash_remove(struct p
+ }
+
+ static struct platform_driver bcm47xxnflash_driver = {
++ .probe = bcm47xxnflash_probe,
+ .remove = bcm47xxnflash_remove,
+ .driver = {
+ .name = "bcma_nflash",
+@@ -88,11 +89,7 @@ static int __init bcm47xxnflash_init(voi
+ {
+ int err;
+
+- /*
+- * Platform device "bcma_nflash" exists on SoCs and is registered very
+- * early, it won't be added during runtime (use platform_driver_probe).
+- */
+- err = platform_driver_probe(&bcm47xxnflash_driver, bcm47xxnflash_probe);
++ err = platform_driver_register(&bcm47xxnflash_driver);
+ if (err)
+ pr_err("Failed to register bcm47xx nand flash driver: %d\n",
+ err);
--- /dev/null
+--- a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
++++ b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
+@@ -1,6 +1,10 @@
+ #ifndef __BCM47XXNFLASH_H
+ #define __BCM47XXNFLASH_H
+
++#ifndef pr_fmt
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++#endif
++
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/nand.h>
+
+--- a/drivers/mtd/nand/bcm47xxnflash/main.c
++++ b/drivers/mtd/nand/bcm47xxnflash/main.c
+@@ -9,14 +9,14 @@
+ *
+ */
+
++#include "bcm47xxnflash.h"
++
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+ #include <linux/slab.h>
+ #include <linux/platform_device.h>
+ #include <linux/bcma/bcma.h>
+
+-#include "bcm47xxnflash.h"
+-
+ MODULE_DESCRIPTION("NAND flash driver for BCMA bus");
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR("Rafał Miłecki");
+--- a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
++++ b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
+@@ -9,13 +9,13 @@
+ *
+ */
+
++#include "bcm47xxnflash.h"
++
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+ #include <linux/slab.h>
+ #include <linux/bcma/bcma.h>
+
+-#include "bcm47xxnflash.h"
+-
+ /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
+ * shown ~1000 retries as maxiumum. */
+ #define NFLASH_READY_RETRIES 10000
--- /dev/null
+--- a/drivers/mtd/devices/bcm47xxsflash.c
++++ b/drivers/mtd/devices/bcm47xxsflash.c
+@@ -1,47 +1,153 @@
+-#include <linux/kernel.h>
++/*
++ * Broadcom SiliconBackplane chipcommon serial flash interface
++ *
++ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
++ * Copyright 2006, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#define pr_fmt(fmt) "bcm47xxsflash: " fmt
+ #include <linux/module.h>
+ #include <linux/slab.h>
++#include <linux/ioport.h>
++#include <linux/sched.h>
+ #include <linux/mtd/mtd.h>
++#include <linux/mtd/map.h>
++#include <linux/mtd/partitions.h>
++#include <linux/errno.h>
++#include <linux/delay.h>
+ #include <linux/platform_device.h>
+-#include <linux/bcma/bcma.h>
+-
+-#include "bcm47xxsflash.h"
++#include <linux/mtd/bcm47xxsflash.h>
+
+ MODULE_LICENSE("GPL");
+-MODULE_DESCRIPTION("Serial flash driver for BCMA bus");
++MODULE_DESCRIPTION("BCM47XX serial flash driver");
+
+ static const char *probes[] = { "bcm47xxpart", NULL };
+
++static int
++sflash_mtd_poll(struct bcm47xxsflash *sflash, unsigned int offset, int timeout)
++{
++ unsigned long now = jiffies;
++
++ for (;;) {
++ if (!sflash->poll(sflash, offset)) {
++ break;
++ }
++ if (time_after(jiffies, now + timeout)) {
++ pr_err("timeout while polling\n");
++ return -ETIMEDOUT;
++
++ }
++ cpu_relax();
++ udelay(1);
++ }
++
++ return 0;
++}
++
+ static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+ {
+- struct bcm47xxsflash *b47s = mtd->priv;
++ struct bcm47xxsflash *sflash = (struct bcm47xxsflash *)mtd->priv;
+
+ /* Check address range */
++ if (!len)
++ return 0;
++
+ if ((from + len) > mtd->size)
+ return -EINVAL;
+
+- memcpy_fromio(buf, (void __iomem *)KSEG0ADDR(b47s->window + from),
++ memcpy_fromio(buf, (void __iomem *)KSEG0ADDR(sflash->window + from),
+ len);
+ *retlen = len;
+
+ return len;
+ }
+
+-static void bcm47xxsflash_fill_mtd(struct bcm47xxsflash *b47s)
++static int
++sflash_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
+ {
+- struct mtd_info *mtd = &b47s->mtd;
++ int bytes;
++ int ret;
++ struct bcm47xxsflash *sflash = (struct bcm47xxsflash *)mtd->priv;
+
+- mtd->priv = b47s;
+- mtd->name = "bcm47xxsflash";
+- mtd->owner = THIS_MODULE;
+- mtd->type = MTD_ROM;
+- mtd->size = b47s->size;
+- mtd->_read = bcm47xxsflash_read;
++ /* Check address range */
++ if (!len)
++ return 0;
++
++ if ((to + len) > mtd->size)
++ return -EINVAL;
++
++ *retlen = 0;
++ while (len) {
++ ret = sflash->write(sflash, to, len, buf);
++ if (ret < 0)
++ return ret;
++
++ bytes = ret;
++
++ ret = sflash_mtd_poll(sflash, (unsigned int) to, HZ / 10);
++ if (ret)
++ return ret;
++
++ to += (loff_t) bytes;
++ len -= bytes;
++ buf += bytes;
++ *retlen += bytes;
++ }
+
+- /* TODO: implement writing support and verify/change following code */
+- mtd->flags = MTD_CAP_ROM;
+- mtd->writebufsize = mtd->writesize = 1;
++ return 0;
++}
++
++static int
++sflash_mtd_erase(struct mtd_info *mtd, struct erase_info *erase)
++{
++ struct bcm47xxsflash *sflash = (struct bcm47xxsflash *) mtd->priv;
++ int i, j, ret = 0;
++ unsigned int addr, len;
++
++ /* Check address range */
++ if (!erase->len)
++ return 0;
++ if ((erase->addr + erase->len) > mtd->size)
++ return -EINVAL;
++
++ addr = erase->addr;
++ len = erase->len;
++
++ /* Ensure that requested regions are aligned */
++ for (i = 0; i < mtd->numeraseregions; i++) {
++ for (j = 0; j < mtd->eraseregions[i].numblocks; j++) {
++ if (addr == mtd->eraseregions[i].offset +
++ mtd->eraseregions[i].erasesize * j &&
++ len >= mtd->eraseregions[i].erasesize) {
++ ret = sflash->erase(sflash, addr);
++ if (ret < 0)
++ break;
++ ret = sflash_mtd_poll(sflash, addr, 10 * HZ);
++ if (ret)
++ break;
++ addr += mtd->eraseregions[i].erasesize;
++ len -= mtd->eraseregions[i].erasesize;
++ }
++ }
++ if (ret)
++ break;
++ }
++
++ /* Set erase status */
++ if (ret)
++ erase->state = MTD_ERASE_FAILED;
++ else
++ erase->state = MTD_ERASE_DONE;
++
++ /* Call erase callback */
++ if (erase->callback)
++ erase->callback(erase);
++
++ return ret;
+ }
+
+ /**************************************************
+@@ -50,53 +156,94 @@ static void bcm47xxsflash_fill_mtd(struc
+
+ static int bcm47xxsflash_bcma_probe(struct platform_device *pdev)
+ {
+- struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
+- struct bcm47xxsflash *b47s;
+- int err;
++ struct bcm47xxsflash *sflash = dev_get_platdata(&pdev->dev);
++ struct mtd_info *mtd;
++ struct mtd_erase_region_info *eraseregions;
++ int ret = 0;
++
++ mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
++ if (!mtd){
++ ret = -ENOMEM;
++ goto err_out;
++ }
+
+- b47s = kzalloc(sizeof(*b47s), GFP_KERNEL);
+- if (!b47s) {
+- err = -ENOMEM;
+- goto out;
+- }
+- sflash->priv = b47s;
+-
+- b47s->window = sflash->window;
+- b47s->blocksize = sflash->blocksize;
+- b47s->numblocks = sflash->numblocks;
+- b47s->size = sflash->size;
+- bcm47xxsflash_fill_mtd(b47s);
+-
+- err = mtd_device_parse_register(&b47s->mtd, probes, NULL, NULL, 0);
+- if (err) {
+- pr_err("Failed to register MTD device: %d\n", err);
+- goto err_dev_reg;
++ eraseregions = kzalloc(sizeof(struct mtd_erase_region_info), GFP_KERNEL);
++ if (!eraseregions) {
++ ret = -ENOMEM;
++ goto err_free_mtd;
+ }
+
++ pr_info("found serial flash: blocksize=%dKB, numblocks=%d, size=%dKB\n",
++ sflash->blocksize / 1024, sflash->numblocks, sflash->size / 1024);
++
++ /* Setup region info */
++ eraseregions->offset = 0;
++ eraseregions->erasesize = sflash->blocksize;
++ eraseregions->numblocks = sflash->numblocks;
++ if (eraseregions->erasesize > mtd->erasesize)
++ mtd->erasesize = eraseregions->erasesize;
++ mtd->size = sflash->size;
++ mtd->numeraseregions = 1;
++
++ /* Register with MTD */
++ mtd->name = "bcm47xx-sflash";
++ mtd->type = MTD_NORFLASH;
++ mtd->flags = MTD_CAP_NORFLASH;
++ mtd->eraseregions = eraseregions;
++ mtd->_erase = sflash_mtd_erase;
++ mtd->_read = bcm47xxsflash_read;
++ mtd->_write = sflash_mtd_write;
++ mtd->writesize = 1;
++ mtd->priv = sflash;
++ ret = dev_set_drvdata(&pdev->dev, mtd);
++ mtd->owner = THIS_MODULE;
++ if (ret) {
++ pr_err("adding private data failed\n");
++ goto err_free_eraseregions;
++ }
++
++ ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0);
++
++ if (ret) {
++ pr_err("mtd_device_register failed\n");
++ goto err_free_eraseregions;
++ }
+ return 0;
+
+-err_dev_reg:
+- kfree(&b47s->mtd);
+-out:
+- return err;
++err_free_eraseregions:
++ kfree(eraseregions);
++err_free_mtd:
++ kfree(mtd);
++err_out:
++ return ret;
+ }
+
+ static int bcm47xxsflash_bcma_remove(struct platform_device *pdev)
+ {
+- struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
+- struct bcm47xxsflash *b47s = sflash->priv;
+-
+- mtd_device_unregister(&b47s->mtd);
+- kfree(b47s);
++ struct mtd_info *mtd = dev_get_drvdata(&pdev->dev);
+
++ if (mtd) {
++ mtd_device_unregister(mtd);
++ map_destroy(mtd);
++ kfree(mtd->eraseregions);
++ kfree(mtd);
++ dev_set_drvdata(&pdev->dev, NULL);
++ }
+ return 0;
+ }
+
++static const struct platform_device_id bcm47xxsflash_table[] = {
++ { "bcm47xx-sflash", 0 },
++ { }
++};
++MODULE_DEVICE_TABLE(platform, bcm47xxsflash_table);
++
+ static struct platform_driver bcma_sflash_driver = {
++ .id_table = bcm47xxsflash_table,
+ .probe = bcm47xxsflash_bcma_probe,
+ .remove = bcm47xxsflash_bcma_remove,
+ .driver = {
+- .name = "bcma_sflash",
++ .name = "bcm47xx-sflash",
+ .owner = THIS_MODULE,
+ },
+ };
+@@ -111,8 +258,7 @@ static int __init bcm47xxsflash_init(voi
+
+ err = platform_driver_register(&bcma_sflash_driver);
+ if (err)
+- pr_err("Failed to register BCMA serial flash driver: %d\n",
+- err);
++ pr_err("error registering platform driver: %i\n", err);
+
+ return err;
+ }
+--- /dev/null
++++ b/include/linux/mtd/bcm47xxsflash.h
+@@ -0,0 +1,33 @@
++#ifndef LINUX_MTD_BCM47XX_SFLASH_H_
++#define LINUX_MTD_BCM47XX_SFLASH_H_
++
++#include <linux/mtd/mtd.h>
++
++enum bcm47xxsflash_type {
++ BCM47XX_SFLASH_SSB,
++ BCM47XX_SFLASH_BCMA,
++};
++
++struct ssb_chipcommon;
++struct bcma_drv_cc;
++
++struct bcm47xxsflash {
++ enum bcm47xxsflash_type type;
++ union {
++ struct ssb_chipcommon *scc;
++ struct bcma_drv_cc *bcc;
++ };
++
++ bool present;
++ u16 numblocks;
++ u32 window;
++ u32 blocksize;
++ u32 size;
++
++ int (*poll)(struct bcm47xxsflash *dev, u32 offset);
++ int (*write)(struct bcm47xxsflash *dev, u32 offset, u32 len, const u8 *buf);
++ int (*erase)(struct bcm47xxsflash *dev, u32 offset);
++
++ struct mtd_info *mtd;
++};
++#endif /* LINUX_MTD_BCM47XX_SFLASH_H_ */
--- /dev/null
+--- a/drivers/ssb/Kconfig
++++ b/drivers/ssb/Kconfig
+@@ -139,7 +139,7 @@ config SSB_DRIVER_MIPS
+
+ config SSB_SFLASH
+ bool "SSB serial flash support"
+- depends on SSB_DRIVER_MIPS && BROKEN
++ depends on SSB_DRIVER_MIPS
+ default y
+
+ # Assumption: We are on embedded, if we compile the MIPS core.
+--- a/drivers/ssb/driver_chipcommon_sflash.c
++++ b/drivers/ssb/driver_chipcommon_sflash.c
+@@ -1,14 +1,35 @@
+ /*
+ * Sonics Silicon Backplane
+ * ChipCommon serial flash interface
++ * Copyright 2011, Jonas Gorski <jonas.gorski@gmail.com>
++ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
++ * Copyright 2010, Broadcom Corporation
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
++#include <linux/platform_device.h>
++#include <linux/delay.h>
+ #include <linux/ssb/ssb.h>
++#include <linux/ssb/ssb_driver_chipcommon.h>
+
+ #include "ssb_private.h"
+
++#define NUM_RETRIES 3
++
++static struct resource ssb_sflash_resource = {
++ .name = "ssb_sflash",
++ .start = SSB_FLASH2,
++ .end = 0,
++ .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
++};
++
++struct platform_device ssb_sflash_dev = {
++ .name = "bcm47xx-sflash",
++ .resource = &ssb_sflash_resource,
++ .num_resources = 1,
++};
++
+ struct ssb_sflash_tbl_e {
+ char *name;
+ u32 id;
+@@ -16,7 +37,7 @@ struct ssb_sflash_tbl_e {
+ u16 numblocks;
+ };
+
+-static struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
++static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
+ { "M25P20", 0x11, 0x10000, 4, },
+ { "M25P40", 0x12, 0x10000, 8, },
+
+@@ -27,7 +48,7 @@ static struct ssb_sflash_tbl_e ssb_sflas
+ { 0 },
+ };
+
+-static struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
++static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
+ { "SST25WF512", 1, 0x1000, 16, },
+ { "SST25VF512", 0x48, 0x1000, 16, },
+ { "SST25WF010", 2, 0x1000, 32, },
+@@ -45,7 +66,7 @@ static struct ssb_sflash_tbl_e ssb_sflas
+ { 0 },
+ };
+
+-static struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
++static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
+ { "AT45DB011", 0xc, 256, 512, },
+ { "AT45DB021", 0x14, 256, 1024, },
+ { "AT45DB041", 0x1c, 256, 2048, },
+@@ -70,10 +91,186 @@ static void ssb_sflash_cmd(struct ssb_ch
+ pr_err("SFLASH control command failed (timeout)!\n");
+ }
+
++static void ssb_sflash_write_u8(struct ssb_chipcommon *chipco, u32 offset, u8 byte)
++{
++ chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, offset);
++ chipco_write32(chipco, SSB_CHIPCO_FLASHDATA, byte);
++}
++
++/* Poll for command completion. Returns zero when complete. */
++static int ssb_sflash_poll(struct bcm47xxsflash *dev, u32 offset)
++{
++ struct ssb_chipcommon *chipco = dev->scc;
++
++ if (offset >= chipco->sflash.size)
++ return -22;
++
++ switch (chipco->capabilities & SSB_CHIPCO_CAP_FLASHT) {
++ case SSB_CHIPCO_FLASHT_STSER:
++ /* Check for ST Write In Progress bit */
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_RDSR);
++ return chipco_read32(chipco, SSB_CHIPCO_FLASHDATA)
++ & SSB_CHIPCO_FLASHDATA_ST_WIP;
++ case SSB_CHIPCO_FLASHT_ATSER:
++ /* Check for Atmel Ready bit */
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_STATUS);
++ return !(chipco_read32(chipco, SSB_CHIPCO_FLASHDATA)
++ & SSB_CHIPCO_FLASHDATA_AT_READY);
++ }
++
++ return 0;
++}
++
++
++static int sflash_st_write(struct bcm47xxsflash *dev, u32 offset, u32 len,
++ const u8 *buf)
++{
++ int written = 1;
++ struct ssb_chipcommon *chipco = dev->scc;
++
++ /* Enable writes */
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_WREN);
++ ssb_sflash_write_u8(chipco, offset, *buf++);
++ /* Issue a page program with CSA bit set */
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_CSA | SSB_CHIPCO_FLASHCTL_ST_PP);
++ offset++;
++ len--;
++ while (len > 0) {
++ if ((offset & 255) == 0) {
++ /* Page boundary, poll droping cs and return */
++ chipco_write32(chipco, SSB_CHIPCO_FLASHCTL, 0);
++ udelay(1);
++ if (!ssb_sflash_poll(dev, offset)) {
++ /* Flash rejected command */
++ return -EAGAIN;
++ }
++ return written;
++ } else {
++ /* Write single byte */
++ ssb_sflash_cmd(chipco,
++ SSB_CHIPCO_FLASHCTL_ST_CSA |
++ *buf++);
++ }
++ written++;
++ offset++;
++ len--;
++ }
++ /* All done, drop cs & poll */
++ chipco_write32(chipco, SSB_CHIPCO_FLASHCTL, 0);
++ udelay(1);
++ if (!ssb_sflash_poll(dev, offset)) {
++ /* Flash rejected command */
++ return -EAGAIN;
++ }
++ return written;
++}
++
++static int sflash_at_write(struct bcm47xxsflash *dev, u32 offset, u32 len,
++ const u8 *buf)
++{
++ struct ssb_chipcommon *chipco = dev->scc;
++ u32 page, byte, mask;
++ int ret = 0;
++
++ mask = dev->blocksize - 1;
++ page = (offset & ~mask) << 1;
++ byte = offset & mask;
++ /* Read main memory page into buffer 1 */
++ if (byte || (len < dev->blocksize)) {
++ int i = 100;
++ chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, page);
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD);
++ /* 250 us for AT45DB321B */
++ while (i > 0 && ssb_sflash_poll(dev, offset)) {
++ udelay(10);
++ i--;
++ }
++ BUG_ON(!ssb_sflash_poll(dev, offset));
++ }
++ /* Write into buffer 1 */
++ for (ret = 0; (ret < (int)len) && (byte < dev->blocksize); ret++) {
++ ssb_sflash_write_u8(chipco, byte++, *buf++);
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE);
++ }
++ /* Write buffer 1 into main memory page */
++ chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, page);
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM);
++
++ return ret;
++}
++
++/* Write len bytes starting at offset into buf. Returns number of bytes
++ * written. Caller should poll for completion.
++ */
++static int ssb_sflash_write(struct bcm47xxsflash *dev, u32 offset, u32 len,
++ const u8 *buf)
++{
++ int ret = 0, tries = NUM_RETRIES;
++ struct ssb_chipcommon *chipco = dev->scc;
++
++ if (!len)
++ return 0;
++
++ if ((offset + len) > chipco->sflash.size)
++ return -EINVAL;
++
++ switch (chipco->capabilities & SSB_CHIPCO_CAP_FLASHT) {
++ case SSB_CHIPCO_FLASHT_STSER:
++ do {
++ ret = sflash_st_write(dev, offset, len, buf);
++ tries--;
++ } while (ret == -EAGAIN && tries > 0);
++
++ if (ret == -EAGAIN && tries == 0) {
++ pr_info("ST Flash rejected write\n");
++ ret = -EIO;
++ }
++ break;
++ case SSB_CHIPCO_FLASHT_ATSER:
++ ret = sflash_at_write(dev, offset, len, buf);
++ break;
++ }
++
++ return ret;
++}
++
++/* Erase a region. Returns number of bytes scheduled for erasure.
++ * Caller should poll for completion.
++ */
++static int ssb_sflash_erase(struct bcm47xxsflash *dev, u32 offset)
++{
++ struct ssb_chipcommon *chipco = dev->scc;
++
++ if (offset >= chipco->sflash.size)
++ return -EINVAL;
++
++ switch (chipco->capabilities & SSB_CHIPCO_CAP_FLASHT) {
++ case SSB_CHIPCO_FLASHT_STSER:
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_WREN);
++ chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, offset);
++ /* Newer flashes have "sub-sectors" which can be erased independently
++ * with a new command: ST_SSE. The ST_SE command erases 64KB just as
++ * before.
++ */
++ if (dev->blocksize < (64 * 1024))
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_SSE);
++ else
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_SE);
++ return dev->blocksize;
++ case SSB_CHIPCO_FLASHT_ATSER:
++ chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, offset << 1);
++ ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE);
++ return dev->blocksize;
++ }
++
++ return 0;
++}
++
+ /* Initialize serial flash access */
+ int ssb_sflash_init(struct ssb_chipcommon *cc)
+ {
+- struct ssb_sflash_tbl_e *e;
++ struct bcm47xxsflash *sflash = &cc->sflash;
++ const struct ssb_sflash_tbl_e *e;
+ u32 id, id2;
+
+ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
+@@ -131,10 +328,26 @@ int ssb_sflash_init(struct ssb_chipcommo
+ return -ENOTSUPP;
+ }
+
+- pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
+- e->name, e->blocksize, e->numblocks);
+-
+- pr_err("Serial flash support is not implemented yet!\n");
++ sflash->window = SSB_FLASH2;
++ sflash->blocksize = e->blocksize;
++ sflash->numblocks = e->numblocks;
++ sflash->size = sflash->blocksize * sflash->numblocks;
++ sflash->present = true;
++ sflash->poll = ssb_sflash_poll;
++ sflash->write = ssb_sflash_write;
++ sflash->erase = ssb_sflash_erase;
++ sflash->type = BCM47XX_SFLASH_SSB;
++ sflash->scc = cc;
++
++ pr_info("Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
++ e->name, sflash->size / 1024, sflash->blocksize,
++ sflash->numblocks);
++
++ /* Prepare platform device, but don't register it yet. It's too early,
++ * malloc (required by device_private_init) is not available yet. */
++ ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
++ sflash->size;
++ ssb_sflash_dev.dev.platform_data = sflash;
+
+- return -ENOTSUPP;
++ return 0;
+ }
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -549,6 +549,15 @@ static int ssb_devices_register(struct s
+ dev_idx++;
+ }
+
++#ifdef CONFIG_SSB_SFLASH
++ if (bus->chipco.sflash.present) {
++ err = platform_device_register(&ssb_sflash_dev);
++ if (err)
++ ssb_printk(KERN_ERR PFX
++ "Error registering serial flash\n");
++ }
++#endif
++
+ #ifdef CONFIG_SSB_DRIVER_MIPS
+ if (bus->mipscore.pflash.present) {
+ err = platform_device_register(&ssb_pflash_dev);
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -220,6 +220,7 @@ extern u32 ssb_chipco_watchdog_timer_set
+ /* driver_chipcommon_sflash.c */
+ #ifdef CONFIG_SSB_SFLASH
+ int ssb_sflash_init(struct ssb_chipcommon *cc);
++extern struct platform_device ssb_sflash_dev;
+ #else
+ static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
+ {
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -13,6 +13,8 @@
+ * Licensed under the GPL version 2. See COPYING for details.
+ */
+
++#include <linux/mtd/bcm47xxsflash.h>
++
+ /** ChipCommon core registers. **/
+
+ #define SSB_CHIPCO_CHIPID 0x0000
+@@ -121,6 +123,17 @@
+ #define SSB_CHIPCO_FLASHCTL_BUSY SSB_CHIPCO_FLASHCTL_START
+ #define SSB_CHIPCO_FLASHADDR 0x0044
+ #define SSB_CHIPCO_FLASHDATA 0x0048
++/* Status register bits for ST flashes */
++#define SSB_CHIPCO_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
++#define SSB_CHIPCO_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
++#define SSB_CHIPCO_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
++#define SSB_CHIPCO_FLASHDATA_ST_BP_SHIFT 2
++#define SSB_CHIPCO_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
++/* Status register bits for Atmel flashes */
++#define SSB_CHIPCO_FLASHDATA_AT_READY 0x80
++#define SSB_CHIPCO_FLASHDATA_AT_MISMATCH 0x40
++#define SSB_CHIPCO_FLASHDATA_AT_ID_MASK 0x38
++#define SSB_CHIPCO_FLASHDATA_AT_ID_SHIFT 3
+ #define SSB_CHIPCO_BCAST_ADDR 0x0050
+ #define SSB_CHIPCO_BCAST_DATA 0x0054
+ #define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
+@@ -503,7 +516,7 @@
+ #define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */
+ #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
+ #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
+-#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
++#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00D9 /* Deep Power-down */
+ #define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
+ #define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
+ #define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
+@@ -594,6 +607,9 @@ struct ssb_chipcommon {
+ struct ssb_chipcommon_pmu pmu;
+ u32 ticks_per_ms;
+ u32 max_timer_ms;
++#ifdef CONFIG_SSB_SFLASH
++ struct bcm47xxsflash sflash;
++#endif
+ };
+
+ static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
--- /dev/null
+--- a/drivers/bcma/driver_chipcommon_sflash.c
++++ b/drivers/bcma/driver_chipcommon_sflash.c
+@@ -1,6 +1,9 @@
+ /*
+ * Broadcom specific AMBA
+ * ChipCommon serial flash interface
++ * Copyright 2011, Jonas Gorski <jonas.gorski@gmail.com>
++ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
++ * Copyright 2010, Broadcom Corporation
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+@@ -8,7 +11,11 @@
+ #include "bcma_private.h"
+
+ #include <linux/platform_device.h>
++#include <linux/delay.h>
+ #include <linux/bcma/bcma.h>
++#include <linux/bcma/bcma_driver_chipcommon.h>
++
++#define NUM_RETRIES 3
+
+ static struct resource bcma_sflash_resource = {
+ .name = "bcma_sflash",
+@@ -18,7 +25,7 @@ static struct resource bcma_sflash_resou
+ };
+
+ struct platform_device bcma_sflash_dev = {
+- .name = "bcma_sflash",
++ .name = "bcm47xx-sflash",
+ .resource = &bcma_sflash_resource,
+ .num_resources = 1,
+ };
+@@ -30,7 +37,7 @@ struct bcma_sflash_tbl_e {
+ u16 numblocks;
+ };
+
+-static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
++static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
+ { "M25P20", 0x11, 0x10000, 4, },
+ { "M25P40", 0x12, 0x10000, 8, },
+
+@@ -41,7 +48,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
+ { 0 },
+ };
+
+-static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
++static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
+ { "SST25WF512", 1, 0x1000, 16, },
+ { "SST25VF512", 0x48, 0x1000, 16, },
+ { "SST25WF010", 2, 0x1000, 32, },
+@@ -59,7 +66,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
+ { 0 },
+ };
+
+-static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
++static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
+ { "AT45DB011", 0xc, 256, 512, },
+ { "AT45DB021", 0x14, 256, 1024, },
+ { "AT45DB041", 0x1c, 256, 2048, },
+@@ -84,12 +91,186 @@ static void bcma_sflash_cmd(struct bcma_
+ bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
+ }
+
++static void bcma_sflash_write_u8(struct bcma_drv_cc *cc, u32 offset, u8 byte)
++{
++ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, offset);
++ bcma_cc_write32(cc, BCMA_CC_FLASHDATA, byte);
++}
++
++/* Poll for command completion. Returns zero when complete. */
++static int bcma_sflash_poll(struct bcm47xxsflash *dev, u32 offset)
++{
++ struct bcma_drv_cc *cc = dev->bcc;
++
++ if (offset >= cc->sflash.size)
++ return -22;
++
++ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
++ case BCMA_CC_FLASHT_STSER:
++ /* Check for ST Write In Progress bit */
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RDSR);
++ return bcma_cc_read32(cc, BCMA_CC_FLASHDATA)
++ & BCMA_CC_FLASHDATA_ST_WIP;
++ case BCMA_CC_FLASHT_ATSER:
++ /* Check for Atmel Ready bit */
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
++ return !(bcma_cc_read32(cc, BCMA_CC_FLASHDATA)
++ & BCMA_CC_FLASHDATA_AT_READY);
++ }
++
++ return 0;
++}
++
++static int sflash_st_write(struct bcm47xxsflash *dev, u32 offset, u32 len,
++ const u8 *buf)
++{
++ int written = 1;
++ struct bcma_drv_cc *cc = dev->bcc;
++
++ /* Enable writes */
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_WREN);
++ bcma_sflash_write_u8(cc, offset, *buf++);
++ /* Issue a page program with CSA bit set */
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_CSA | BCMA_CC_FLASHCTL_ST_PP);
++ offset++;
++ len--;
++ while (len > 0) {
++ if ((offset & 255) == 0) {
++ /* Page boundary, poll droping cs and return */
++ bcma_cc_write32(cc, BCMA_CC_FLASHCTL, 0);
++ udelay(1);
++ if (!bcma_sflash_poll(dev, offset)) {
++ /* Flash rejected command */
++ return -EAGAIN;
++ }
++ return written;
++ } else {
++ /* Write single byte */
++ bcma_sflash_cmd(cc,
++ BCMA_CC_FLASHCTL_ST_CSA |
++ *buf++);
++ }
++ written++;
++ offset++;
++ len--;
++ }
++ /* All done, drop cs & poll */
++ bcma_cc_write32(cc, BCMA_CC_FLASHCTL, 0);
++ udelay(1);
++ if (!bcma_sflash_poll(dev, offset)) {
++ /* Flash rejected command */
++ return -EAGAIN;
++ }
++ return written;
++}
++
++static int sflash_at_write(struct bcm47xxsflash *dev, u32 offset, u32 len,
++ const u8 *buf)
++{
++ struct bcma_drv_cc *cc = dev->bcc;
++ u32 page, byte, mask;
++ int ret = 0;
++
++ mask = dev->blocksize - 1;
++ page = (offset & ~mask) << 1;
++ byte = offset & mask;
++ /* Read main memory page into buffer 1 */
++ if (byte || (len < dev->blocksize)) {
++ int i = 100;
++ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, page);
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_BUF1_LOAD);
++ /* 250 us for AT45DB321B */
++ while (i > 0 && bcma_sflash_poll(dev, offset)) {
++ udelay(10);
++ i--;
++ }
++ BUG_ON(!bcma_sflash_poll(dev, offset));
++ }
++ /* Write into buffer 1 */
++ for (ret = 0; (ret < (int)len) && (byte < dev->blocksize); ret++) {
++ bcma_sflash_write_u8(cc, byte++, *buf++);
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_BUF1_WRITE);
++ }
++ /* Write buffer 1 into main memory page */
++ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, page);
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM);
++
++ return ret;
++}
++
++/* Write len bytes starting at offset into buf. Returns number of bytes
++ * written. Caller should poll for completion.
++ */
++static int bcma_sflash_write(struct bcm47xxsflash *dev, u32 offset, u32 len,
++ const u8 *buf)
++{
++ int ret = 0, tries = NUM_RETRIES;
++ struct bcma_drv_cc *cc = dev->bcc;
++
++ if (!len)
++ return 0;
++
++ if ((offset + len) > cc->sflash.size)
++ return -EINVAL;
++
++ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
++ case BCMA_CC_FLASHT_STSER:
++ do {
++ ret = sflash_st_write(dev, offset, len, buf);
++ tries--;
++ } while (ret == -EAGAIN && tries > 0);
++
++ if (ret == -EAGAIN && tries == 0) {
++ bcma_info(cc->core->bus, "ST Flash rejected write\n");
++ ret = -EIO;
++ }
++ break;
++ case BCMA_CC_FLASHT_ATSER:
++ ret = sflash_at_write(dev, offset, len, buf);
++ break;
++ }
++
++ return ret;
++}
++
++/* Erase a region. Returns number of bytes scheduled for erasure.
++ * Caller should poll for completion.
++ */
++static int bcma_sflash_erase(struct bcm47xxsflash *dev, u32 offset)
++{
++ struct bcma_drv_cc *cc = dev->bcc;
++
++ if (offset >= cc->sflash.size)
++ return -EINVAL;
++
++ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
++ case BCMA_CC_FLASHT_STSER:
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_WREN);
++ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, offset);
++ /* Newer flashes have "sub-sectors" which can be erased independently
++ * with a new command: ST_SSE. The ST_SE command erases 64KB just as
++ * before.
++ */
++ if (dev->blocksize < (64 * 1024))
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_SSE);
++ else
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_SE);
++ return dev->blocksize;
++ case BCMA_CC_FLASHT_ATSER:
++ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, offset << 1);
++ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_PAGE_ERASE);
++ return dev->blocksize;
++ }
++
++ return 0;
++}
++
+ /* Initialize serial flash access */
+ int bcma_sflash_init(struct bcma_drv_cc *cc)
+ {
+ struct bcma_bus *bus = cc->core->bus;
+- struct bcma_sflash *sflash = &cc->sflash;
+- struct bcma_sflash_tbl_e *e;
++ struct bcm47xxsflash *sflash = &cc->sflash;
++ const struct bcma_sflash_tbl_e *e;
+ u32 id, id2;
+
+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
+@@ -150,6 +331,11 @@ int bcma_sflash_init(struct bcma_drv_cc
+ sflash->numblocks = e->numblocks;
+ sflash->size = sflash->blocksize * sflash->numblocks;
+ sflash->present = true;
++ sflash->poll = bcma_sflash_poll;
++ sflash->write = bcma_sflash_write;
++ sflash->erase = bcma_sflash_erase;
++ sflash->type = BCM47XX_SFLASH_BCMA;
++ sflash->bcc = cc;
+
+ bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
+ e->name, sflash->size / 1024, sflash->blocksize,
+--- a/include/linux/bcma/bcma_driver_chipcommon.h
++++ b/include/linux/bcma/bcma_driver_chipcommon.h
+@@ -3,6 +3,7 @@
+
+ #include <linux/platform_device.h>
+ #include <linux/gpio.h>
++#include <linux/mtd/bcm47xxsflash.h>
+
+ /** ChipCommon core registers. **/
+ #define BCMA_CC_ID 0x0000
+@@ -519,19 +520,6 @@ struct bcma_pflash {
+ u32 window_size;
+ };
+
+-#ifdef CONFIG_BCMA_SFLASH
+-struct bcma_sflash {
+- bool present;
+- u32 window;
+- u32 blocksize;
+- u16 numblocks;
+- u32 size;
+-
+- struct mtd_info *mtd;
+- void *priv;
+-};
+-#endif
+-
+ #ifdef CONFIG_BCMA_NFLASH
+ struct mtd_info;
+
+@@ -565,7 +553,7 @@ struct bcma_drv_cc {
+ #ifdef CONFIG_BCMA_DRIVER_MIPS
+ struct bcma_pflash pflash;
+ #ifdef CONFIG_BCMA_SFLASH
+- struct bcma_sflash sflash;
++ struct bcm47xxsflash sflash;
+ #endif
+ #ifdef CONFIG_BCMA_NFLASH
+ struct bcma_nflash nflash;
--- /dev/null
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -3,7 +3,7 @@
+ *
+ * Copyright (C) 2005 Broadcom Corporation
+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+- * Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
++ * Copyright (C) 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+@@ -18,83 +18,168 @@
+ #include <linux/kernel.h>
+ #include <linux/string.h>
+ #include <asm/addrspace.h>
+-#include <asm/mach-bcm47xx/nvram.h>
++#include <bcm47xx_nvram.h>
+ #include <asm/mach-bcm47xx/bcm47xx.h>
+
+ static char nvram_buf[NVRAM_SPACE];
+
++static u32 find_nvram_size(u32 end)
++{
++ struct nvram_header *header;
++ u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
++ header = (struct nvram_header *)KSEG1ADDR(end - nvram_sizes[i]);
++ if (header->magic == NVRAM_HEADER)
++ return nvram_sizes[i];
++ }
++
++ return 0;
++}
++
+ /* Probe for NVRAM header */
+-static void early_nvram_init(void)
++static int nvram_find_and_copy(u32 base, u32 lim)
+ {
+-#ifdef CONFIG_BCM47XX_SSB
+- struct ssb_mipscore *mcore_ssb;
+-#endif
+-#ifdef CONFIG_BCM47XX_BCMA
+- struct bcma_drv_cc *bcma_cc;
+-#endif
+ struct nvram_header *header;
+ int i;
+- u32 base = 0;
+- u32 lim = 0;
+ u32 off;
+ u32 *src, *dst;
++ u32 size;
+
+- switch (bcm47xx_bus_type) {
+-#ifdef CONFIG_BCM47XX_SSB
+- case BCM47XX_BUS_TYPE_SSB:
+- mcore_ssb = &bcm47xx_bus.ssb.mipscore;
+- base = mcore_ssb->pflash.window;
+- lim = mcore_ssb->pflash.window_size;
+- break;
+-#endif
+-#ifdef CONFIG_BCM47XX_BCMA
+- case BCM47XX_BUS_TYPE_BCMA:
+- bcma_cc = &bcm47xx_bus.bcma.bus.drv_cc;
+- base = bcma_cc->pflash.window;
+- lim = bcma_cc->pflash.window_size;
+- break;
+-#endif
+- }
+-
++ /* TODO: when nvram is on nand flash check for bad blocks first. */
+ off = FLASH_MIN;
+ while (off <= lim) {
+ /* Windowed flash access */
+- header = (struct nvram_header *)
+- KSEG1ADDR(base + off - NVRAM_SPACE);
+- if (header->magic == NVRAM_HEADER)
++ size = find_nvram_size(base + off);
++ if (size) {
++ header = (struct nvram_header *)KSEG1ADDR(base + off -
++ size);
+ goto found;
++ }
+ off <<= 1;
+ }
+
+ /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
+ header = (struct nvram_header *) KSEG1ADDR(base + 4096);
+- if (header->magic == NVRAM_HEADER)
++ if (header->magic == NVRAM_HEADER) {
++ size = NVRAM_SPACE;
+ goto found;
++ }
+
+ header = (struct nvram_header *) KSEG1ADDR(base + 1024);
+- if (header->magic == NVRAM_HEADER)
++ if (header->magic == NVRAM_HEADER) {
++ size = NVRAM_SPACE;
+ goto found;
++ }
+
+- return;
++ pr_err("no nvram found\n");
++ return -ENXIO;
+
+ found:
++
++ if (header->len > size)
++ pr_err("The nvram size accoridng to the header seems to be bigger than the partition on flash\n");
++ if (header->len > NVRAM_SPACE)
++ pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
++ header->len, NVRAM_SPACE);
++
+ src = (u32 *) header;
+ dst = (u32 *) nvram_buf;
+ for (i = 0; i < sizeof(struct nvram_header); i += 4)
+ *dst++ = *src++;
+- for (; i < header->len && i < NVRAM_SPACE; i += 4)
++ for (; i < header->len && i < NVRAM_SPACE && i < size; i += 4)
+ *dst++ = le32_to_cpu(*src++);
++ memset(dst, 0x0, NVRAM_SPACE - i);
++
++ return 0;
++}
++
++#ifdef CONFIG_BCM47XX_SSB
++static int nvram_init_ssb(void)
++{
++ struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore;
++#ifdef CONFIG_SSB_SFLASH
++ struct ssb_chipcommon *chipco = &bcm47xx_bus.ssb.chipco;
++#endif
++ u32 base;
++ u32 lim;
++
++ if (mcore->pflash.present) {
++ base = mcore->pflash.window;
++ lim = mcore->pflash.window_size;
++#ifdef CONFIG_SSB_SFLASH
++ } else if (chipco->sflash.present) {
++ base = chipco->sflash.window;
++ lim = chipco->sflash.size;
++#endif
++ } else {
++ pr_err("Couldn't find supported flash memory\n");
++ return -ENXIO;
++ }
++
++ return nvram_find_and_copy(base, lim);
++}
++#endif
++
++#ifdef CONFIG_BCM47XX_BCMA
++static int nvram_init_bcma(void)
++{
++ struct bcma_drv_cc *cc = &bcm47xx_bus.bcma.bus.drv_cc;
++ u32 base;
++ u32 lim;
++
++#ifdef CONFIG_BCMA_NFLASH
++ if (cc->nflash.boot) {
++ base = BCMA_SOC_FLASH1;
++ lim = BCMA_SOC_FLASH1_SZ;
++ } else
++#endif
++ if (cc->pflash.present) {
++ base = cc->pflash.window;
++ lim = cc->pflash.window_size;
++#ifdef CONFIG_BCMA_SFLASH
++ } else if (cc->sflash.present) {
++ base = cc->sflash.window;
++ lim = cc->sflash.size;
++#endif
++ } else {
++ pr_err("Couldn't find supported flash memory\n");
++ return -ENXIO;
++ }
++
++ return nvram_find_and_copy(base, lim);
+ }
++#endif
+
+-int nvram_getenv(char *name, char *val, size_t val_len)
++static int nvram_init(void)
++{
++ switch (bcm47xx_bus_type) {
++#ifdef CONFIG_BCM47XX_SSB
++ case BCM47XX_BUS_TYPE_SSB:
++ return nvram_init_ssb();
++#endif
++#ifdef CONFIG_BCM47XX_BCMA
++ case BCM47XX_BUS_TYPE_BCMA:
++ return nvram_init_bcma();
++#endif
++ }
++ return -ENXIO;
++}
++
++int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len)
+ {
+ char *var, *value, *end, *eq;
++ int err;
+
+ if (!name)
+- return NVRAM_ERR_INV_PARAM;
++ return -EINVAL;
+
+- if (!nvram_buf[0])
+- early_nvram_init();
++ if (!nvram_buf[0]) {
++ err = nvram_init();
++ if (err)
++ return err;
++ }
+
+ /* Look for name=value and return value */
+ var = &nvram_buf[sizeof(struct nvram_header)];
+@@ -110,6 +195,6 @@ int nvram_getenv(char *name, char *val,
+ return snprintf(val, val_len, "%s", value);
+ }
+ }
+- return NVRAM_ERR_ENVNOTFOUND;
++ return -ENOENT;
+ }
+-EXPORT_SYMBOL(nvram_getenv);
++EXPORT_SYMBOL(bcm47xx_nvram_getenv);
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -35,7 +35,7 @@
+ #include <asm/reboot.h>
+ #include <asm/time.h>
+ #include <bcm47xx.h>
+-#include <asm/mach-bcm47xx/nvram.h>
++#include <bcm47xx_nvram.h>
+
+ union bcm47xx_bus bcm47xx_bus;
+ EXPORT_SYMBOL(bcm47xx_bus);
+@@ -115,7 +115,7 @@ static int bcm47xx_get_invariants(struct
+ memset(&iv->sprom, 0, sizeof(struct ssb_sprom));
+ bcm47xx_fill_sprom(&iv->sprom, NULL, false);
+
+- if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0)
++ if (bcm47xx_nvram_getenv("cardbus", buf, sizeof(buf)) >= 0)
+ iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10);
+
+ return 0;
+@@ -138,7 +138,7 @@ static void __init bcm47xx_register_ssb(
+ panic("Failed to initialize SSB bus (err %d)", err);
+
+ mcore = &bcm47xx_bus.ssb.mipscore;
+- if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
++ if (bcm47xx_nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
+ if (strstr(buf, "console=ttyS1")) {
+ struct ssb_serial_port port;
+
+--- a/arch/mips/bcm47xx/sprom.c
++++ b/arch/mips/bcm47xx/sprom.c
+@@ -27,7 +27,7 @@
+ */
+
+ #include <bcm47xx.h>
+-#include <nvram.h>
++#include <bcm47xx_nvram.h>
+
+ static void create_key(const char *prefix, const char *postfix,
+ const char *name, char *buf, int len)
+@@ -50,10 +50,10 @@ static int get_nvram_var(const char *pre
+
+ create_key(prefix, postfix, name, key, sizeof(key));
+
+- err = nvram_getenv(key, buf, len);
+- if (fallback && err == NVRAM_ERR_ENVNOTFOUND && prefix) {
++ err = bcm47xx_nvram_getenv(key, buf, len);
++ if (fallback && err == -ENOENT && prefix) {
+ create_key(NULL, postfix, name, key, sizeof(key));
+- err = nvram_getenv(key, buf, len);
++ err = bcm47xx_nvram_getenv(key, buf, len);
+ }
+ return err;
+ }
+@@ -144,7 +144,7 @@ static void nvram_read_macaddr(const cha
+ if (err < 0)
+ return;
+
+- nvram_parse_macaddr(buf, *val);
++ bcm47xx_nvram_parse_macaddr(buf, *val);
+ }
+
+ static void nvram_read_alpha2(const char *prefix, const char *name,
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
+@@ -0,0 +1,51 @@
++/*
++ * Copyright (C) 2005, Broadcom Corporation
++ * Copyright (C) 2006, Felix Fietkau <nbd@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#ifndef __BCM47XX_NVRAM_H
++#define __BCM47XX_NVRAM_H
++
++#include <linux/types.h>
++#include <linux/kernel.h>
++
++struct nvram_header {
++ u32 magic;
++ u32 len;
++ u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
++ u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
++ u32 config_ncdl; /* ncdl values for memc */
++};
++
++#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
++#define NVRAM_VERSION 1
++#define NVRAM_HEADER_SIZE 20
++#define NVRAM_SPACE 0x8000
++
++#define FLASH_MIN 0x00020000 /* Minimum flash size */
++
++#define NVRAM_MAX_VALUE_LEN 255
++#define NVRAM_MAX_PARAM_LEN 64
++
++extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len);
++
++static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
++{
++ if (strchr(buf, ':'))
++ sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
++ &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
++ &macaddr[5]);
++ else if (strchr(buf, '-'))
++ sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0],
++ &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
++ &macaddr[5]);
++ else
++ printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
++}
++
++#endif /* __BCM47XX_NVRAM_H */
+--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
++++ /dev/null
+@@ -1,54 +0,0 @@
+-/*
+- * Copyright (C) 2005, Broadcom Corporation
+- * Copyright (C) 2006, Felix Fietkau <nbd@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- */
+-
+-#ifndef __NVRAM_H
+-#define __NVRAM_H
+-
+-#include <linux/types.h>
+-#include <linux/kernel.h>
+-
+-struct nvram_header {
+- u32 magic;
+- u32 len;
+- u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
+- u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
+- u32 config_ncdl; /* ncdl values for memc */
+-};
+-
+-#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
+-#define NVRAM_VERSION 1
+-#define NVRAM_HEADER_SIZE 20
+-#define NVRAM_SPACE 0x8000
+-
+-#define FLASH_MIN 0x00020000 /* Minimum flash size */
+-
+-#define NVRAM_MAX_VALUE_LEN 255
+-#define NVRAM_MAX_PARAM_LEN 64
+-
+-#define NVRAM_ERR_INV_PARAM -8
+-#define NVRAM_ERR_ENVNOTFOUND -9
+-
+-extern int nvram_getenv(char *name, char *val, size_t val_len);
+-
+-static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6])
+-{
+- if (strchr(buf, ':'))
+- sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
+- &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
+- &macaddr[5]);
+- else if (strchr(buf, '-'))
+- sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0],
+- &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
+- &macaddr[5]);
+- else
+- printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
+-}
+-
+-#endif
+--- a/drivers/mtd/bcm47xxpart.c
++++ b/drivers/mtd/bcm47xxpart.c
+@@ -14,7 +14,7 @@
+ #include <linux/slab.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/partitions.h>
+-#include <asm/mach-bcm47xx/nvram.h>
++#include <bcm47xx_nvram.h>
+
+ /* 10 parts were found on sflash on Netgear WNDR4500 */
+ #define BCM47XXPART_MAX_PARTS 12
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -381,7 +381,7 @@ static void b44_set_flow_ctrl(struct b44
+ }
+
+ #ifdef CONFIG_BCM47XX
+-#include <asm/mach-bcm47xx/nvram.h>
++#include <bcm47xx_nvram.h>
+ static void b44_wap54g10_workaround(struct b44 *bp)
+ {
+ char buf[20];
+@@ -393,7 +393,7 @@ static void b44_wap54g10_workaround(stru
+ * see https://dev.openwrt.org/ticket/146
+ * check and reset bit "isolate"
+ */
+- if (nvram_getenv("boardnum", buf, sizeof(buf)) < 0)
++ if (bcm47xx_nvram_getenv("boardnum", buf, sizeof(buf)) < 0)
+ return;
+ if (simple_strtoul(buf, NULL, 0) == 2) {
+ err = __b44_readphy(bp, 0, MII_BMCR, &val);
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -14,7 +14,7 @@
+ #include <linux/delay.h>
+ #include <linux/export.h>
+ #ifdef CONFIG_BCM47XX
+-#include <asm/mach-bcm47xx/nvram.h>
++#include <bcm47xx_nvram.h>
+ #endif
+
+ #include "ssb_private.h"
+@@ -322,7 +322,7 @@ static void ssb_pmu_pll_init(struct ssb_
+ if (bus->bustype == SSB_BUSTYPE_SSB) {
+ #ifdef CONFIG_BCM47XX
+ char buf[20];
+- if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
++ if (bcm47xx_nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
+ crystalfreq = simple_strtoul(buf, NULL, 0);
+ #endif
+ }
+--- a/include/linux/ssb/ssb_driver_gige.h
++++ b/include/linux/ssb/ssb_driver_gige.h
+@@ -98,14 +98,14 @@ static inline bool ssb_gige_must_flush_p
+ }
+
+ #ifdef CONFIG_BCM47XX
+-#include <asm/mach-bcm47xx/nvram.h>
++#include <bcm47xx_nvram.h>
+ /* Get the device MAC address */
+ static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
+ {
+ char buf[20];
+- if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
++ if (bcm47xx_nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
+ return;
+- nvram_parse_macaddr(buf, macaddr);
++ bcm47xx_nvram_parse_macaddr(buf, macaddr);
+ }
+ #else
+ static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
--- /dev/null
+From 9be402f069cc259ad5795b77567d66c4e7f6bef6 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Sun, 18 Jul 2010 14:59:24 +0200
+Subject: [PATCH 4/6] MIPS: BCM47xx: Setup and register serial early
+
+Swap the first and second serial if console=ttyS1 was set.
+Set it up and register it for early serial support.
+
+This patch has been in OpenWRT for a long time.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ arch/mips/bcm47xx/setup.c | 39 ++++++++++++++++++++++++++++++++++++++-
+ 1 files changed, 38 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -31,6 +31,8 @@
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
+ #include <linux/bcma/bcma_soc.h>
++#include <linux/serial.h>
++#include <linux/serial_8250.h>
+ #include <asm/bootinfo.h>
+ #include <asm/reboot.h>
+ #include <asm/time.h>
+@@ -121,6 +123,31 @@ static int bcm47xx_get_invariants(struct
+ return 0;
+ }
+
++#ifdef CONFIG_SERIAL_8250
++static void __init bcm47xx_early_serial_setup(struct ssb_mipscore *mcore)
++{
++ int i;
++
++ for (i = 0; i < mcore->nr_serial_ports; i++) {
++ struct ssb_serial_port *port = &(mcore->serial_ports[i]);
++ struct uart_port s;
++
++ memset(&s, 0, sizeof(s));
++ s.line = i;
++ s.mapbase = (unsigned int) port->regs;
++ s.membase = port->regs;
++ s.irq = port->irq + 2;
++ s.uartclk = port->baud_base;
++ s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
++ s.iotype = SERIAL_IO_MEM;
++ s.regshift = port->reg_shift;
++
++ early_serial_setup(&s);
++ }
++ printk(KERN_DEBUG "Serial init done.\n");
++}
++#endif
++
+ static void __init bcm47xx_register_ssb(void)
+ {
+ int err;
+@@ -150,6 +177,10 @@ static void __init bcm47xx_register_ssb(
+ memcpy(&mcore->serial_ports[1], &port, sizeof(port));
+ }
+ }
++
++#ifdef CONFIG_SERIAL_8250
++ bcm47xx_early_serial_setup(mcore);
++#endif
+ }
+ #endif
+
--- /dev/null
+From 5219981646071abb6731634bf47781a53e248764 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Sun, 18 Jul 2010 15:11:26 +0200
+Subject: [PATCH 6/6] MIPS: BCM47xx: Remove CFE console
+
+Do not use the CFE console. It causes hangs on some devices like the
+Buffalo WHR-HP-G54.
+This was reported in https://dev.openwrt.org/ticket/4061 and
+https://forum.openwrt.org/viewtopic.php?id=17063
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ arch/mips/Kconfig | 1 -
+ arch/mips/bcm47xx/prom.c | 82 +++------------------------------------------
+ 2 files changed, 6 insertions(+), 77 deletions(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -115,7 +115,6 @@ config BCM47XX
+ select IRQ_CPU
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+- select SYS_HAS_EARLY_PRINTK
+ help
+ Support for BCM47XX based boards
+
+--- a/arch/mips/bcm47xx/prom.c
++++ b/arch/mips/bcm47xx/prom.c
+@@ -33,96 +33,28 @@
+ #include <asm/fw/cfe/cfe_api.h>
+ #include <asm/fw/cfe/cfe_error.h>
+
+-static int cfe_cons_handle;
+-
+ const char *get_system_type(void)
+ {
+ return "Broadcom BCM47XX";
+ }
+
+-void prom_putchar(char c)
+-{
+- while (cfe_write(cfe_cons_handle, &c, 1) == 0)
+- ;
+-}
+-
+-static __init void prom_init_cfe(void)
++static __init int prom_init_cfe(void)
+ {
+ uint32_t cfe_ept;
+ uint32_t cfe_handle;
+ uint32_t cfe_eptseal;
+- int argc = fw_arg0;
+- char **envp = (char **) fw_arg2;
+- int *prom_vec = (int *) fw_arg3;
+-
+- /*
+- * Check if a loader was used; if NOT, the 4 arguments are
+- * what CFE gives us (handle, 0, EPT and EPTSEAL)
+- */
+- if (argc < 0) {
+- cfe_handle = (uint32_t)argc;
+- cfe_ept = (uint32_t)envp;
+- cfe_eptseal = (uint32_t)prom_vec;
+- } else {
+- if ((int)prom_vec < 0) {
+- /*
+- * Old loader; all it gives us is the handle,
+- * so use the "known" entrypoint and assume
+- * the seal.
+- */
+- cfe_handle = (uint32_t)prom_vec;
+- cfe_ept = 0xBFC00500;
+- cfe_eptseal = CFE_EPTSEAL;
+- } else {
+- /*
+- * Newer loaders bundle the handle/ept/eptseal
+- * Note: prom_vec is in the loader's useg
+- * which is still alive in the TLB.
+- */
+- cfe_handle = prom_vec[0];
+- cfe_ept = prom_vec[2];
+- cfe_eptseal = prom_vec[3];
+- }
+- }
++
++ cfe_eptseal = (uint32_t) fw_arg3;
++ cfe_handle = (uint32_t) fw_arg0;
++ cfe_ept = (uint32_t) fw_arg2;
+
+ if (cfe_eptseal != CFE_EPTSEAL) {
+- /* too early for panic to do any good */
+ printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
+- while (1) ;
++ return -1;
+ }
+
+ cfe_init(cfe_handle, cfe_ept);
+-}
+-
+-static __init void prom_init_console(void)
+-{
+- /* Initialize CFE console */
+- cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
+-}
+-
+-static __init void prom_init_cmdline(void)
+-{
+- static char buf[COMMAND_LINE_SIZE] __initdata;
+-
+- /* Get the kernel command line from CFE */
+- if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
+- buf[COMMAND_LINE_SIZE - 1] = 0;
+- strcpy(arcs_cmdline, buf);
+- }
+-
+- /* Force a console handover by adding a console= argument if needed,
+- * as CFE is not available anymore later in the boot process. */
+- if ((strstr(arcs_cmdline, "console=")) == NULL) {
+- /* Try to read the default serial port used by CFE */
+- if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
+- || (strncmp("uart", buf, 4)))
+- /* Default to uart0 */
+- strcpy(buf, "uart0");
+-
+- /* Compute the new command line */
+- snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
+- arcs_cmdline, buf[4]);
+- }
++ return 0;
+ }
+
+ static __init void prom_init_mem(void)
+@@ -173,8 +105,6 @@ static __init void prom_init_mem(void)
+ void __init prom_init(void)
+ {
+ prom_init_cfe();
+- prom_init_console();
+- prom_init_cmdline();
+ prom_init_mem();
+ }
+
--- /dev/null
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -107,12 +107,14 @@ config ATH79
+ config BCM47XX
+ bool "Broadcom BCM47XX based boards"
+ select ARCH_WANT_OPTIONAL_GPIOLIB
++ select BOOT_RAW
+ select CEVT_R4K
+ select CSRC_R4K
+ select DMA_NONCOHERENT
+ select FW_CFE
+ select HW_HAS_PCI
+ select IRQ_CPU
++ select NO_EXCEPT_FILL
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ help
--- /dev/null
+--- a/arch/mips/include/asm/r4kcache.h
++++ b/arch/mips/include/asm/r4kcache.h
+@@ -17,6 +17,20 @@
+ #include <asm/cpu-features.h>
+ #include <asm/mipsmtregs.h>
+
++#ifdef CONFIG_BCM47XX
++#include <asm/paccess.h>
++#include <linux/ssb/ssb.h>
++#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
++
++#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
++#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
++#else
++#define BCM4710_DUMMY_RREG()
++
++#define BCM4710_FILL_TLB(addr)
++#define BCM4710_PROTECTED_FILL_TLB(addr)
++#endif
++
+ /*
+ * This macro return a properly sign-extended address suitable as base address
+ * for indexed cache operations. Two issues here:
+@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
+ static inline void flush_dcache_line_indexed(unsigned long addr)
+ {
+ __dflush_prologue
++ BCM4710_DUMMY_RREG();
+ cache_op(Index_Writeback_Inv_D, addr);
+ __dflush_epilogue
+ }
+@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
+ static inline void flush_dcache_line(unsigned long addr)
+ {
+ __dflush_prologue
++ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Writeback_Inv_D, addr);
+ __dflush_epilogue
+ }
+@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
+ static inline void invalidate_dcache_line(unsigned long addr)
+ {
+ __dflush_prologue
++ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Invalidate_D, addr);
+ __dflush_epilogue
+ }
+@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
+ */
+ static inline void protected_flush_icache_line(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ protected_cache_op(Hit_Invalidate_I, addr);
+ }
+
+@@ -219,6 +237,7 @@ static inline void protected_flush_icach
+ */
+ static inline void protected_writeback_dcache_line(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ protected_cache_op(Hit_Writeback_Inv_D, addr);
+ }
+
+@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
+ : "r" (base), \
+ "i" (op));
+
++static inline void blast_dcache(void)
++{
++ unsigned long start = KSEG0;
++ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
++ unsigned long end = (start + dcache_size);
++
++ do {
++ BCM4710_DUMMY_RREG();
++ cache_op(Index_Writeback_Inv_D, start);
++ start += current_cpu_data.dcache.linesz;
++ } while(start < end);
++}
++
++static inline void blast_dcache_page(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = start + PAGE_SIZE;
++
++ BCM4710_FILL_TLB(start);
++ do {
++ BCM4710_DUMMY_RREG();
++ cache_op(Hit_Writeback_Inv_D, start);
++ start += current_cpu_data.dcache.linesz;
++ } while(start < end);
++}
++
++static inline void blast_dcache_page_indexed(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = start + PAGE_SIZE;
++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++ unsigned long ws_end = current_cpu_data.dcache.ways <<
++ current_cpu_data.dcache.waybit;
++ unsigned long ws, addr;
++ for (ws = 0; ws < ws_end; ws += ws_inc) {
++ start = page + ws;
++ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
++ BCM4710_DUMMY_RREG();
++ cache_op(Index_Writeback_Inv_D, addr);
++ }
++ }
++}
++
++
+ /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
+-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
++#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
+ static inline void blast_##pfx##cache##lsize(void) \
+ { \
+ unsigned long start = INDEX_BASE; \
+@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
+ \
+ __##pfx##flush_prologue \
+ \
++ war \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+ for (addr = start; addr < end; addr += lsize * 32) \
+ cache##lsize##_unroll32(addr|ws, indexop); \
+@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
+ \
+ __##pfx##flush_prologue \
+ \
++ war \
+ do { \
+ cache##lsize##_unroll32(start, hitop); \
+ start += lsize * 32; \
+@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
+ current_cpu_data.desc.waybit; \
+ unsigned long ws, addr; \
+ \
++ war \
++ \
+ __##pfx##flush_prologue \
+ \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+@@ -393,36 +460,38 @@ static inline void blast_##pfx##cache##l
+ __##pfx##flush_epilogue \
+ }
+
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
+-
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
++
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
+
+ /* build blast_xxx_range, protected_blast_xxx_range */
+-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
+ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
+ unsigned long end) \
+ { \
+ unsigned long lsize = cpu_##desc##_line_size(); \
+ unsigned long addr = start & ~(lsize - 1); \
+ unsigned long aend = (end - 1) & ~(lsize - 1); \
++ war \
+ \
+ __##pfx##flush_prologue \
+ \
+ while (1) { \
++ war2 \
+ prot##cache_op(hitop, addr); \
+ if (addr == aend) \
+ break; \
+@@ -432,13 +501,13 @@ static inline void prot##blast_##pfx##ca
+ __##pfx##flush_epilogue \
+ }
+
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
+-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
+ /* blast_inv_dcache_range */
+-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
+-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
+
+ #endif /* _ASM_R4KCACHE_H */
+--- a/arch/mips/include/asm/stackframe.h
++++ b/arch/mips/include/asm/stackframe.h
+@@ -449,6 +449,10 @@
+ .macro RESTORE_SP_AND_RET
+ LONG_L sp, PT_R29(sp)
+ .set mips3
++#ifdef CONFIG_BCM47XX
++ nop
++ nop
++#endif
+ eret
+ .set mips0
+ .endm
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
+@@ -51,6 +51,10 @@ NESTED(except_vec1_generic, 0, sp)
+ NESTED(except_vec3_generic, 0, sp)
+ .set push
+ .set noat
++#ifdef CONFIG_BCM47XX
++ nop
++ nop
++#endif
+ #if R5432_CP0_INTERRUPT_WAR
+ mfc0 k0, CP0_INDEX
+ #endif
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -34,6 +34,9 @@
+ #include <asm/cacheflush.h> /* for run_uncached() */
+ #include <asm/traps.h>
+
++/* For enabling BCM4710 cache workarounds */
++int bcm4710 = 0;
++
+ /*
+ * Special Variant of smp_call_function for use by cache functions:
+ *
+@@ -110,6 +113,9 @@ static void __cpuinit r4k_blast_dcache_p
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache_page = blast_dcache_page;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache_page = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -126,6 +132,9 @@ static void __cpuinit r4k_blast_dcache_p
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache_page_indexed = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -142,6 +151,9 @@ static void __cpuinit r4k_blast_dcache_s
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache = blast_dcache;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -671,6 +683,8 @@ static void local_r4k_flush_cache_sigtra
+ unsigned long addr = (unsigned long) arg;
+
+ R4600_HIT_CACHEOP_WAR_IMPL;
++ BCM4710_PROTECTED_FILL_TLB(addr);
++ BCM4710_PROTECTED_FILL_TLB(addr + 4);
+ if (dc_lsize)
+ protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+ if (!cpu_icache_snoops_remote_store && scache_size)
+@@ -1355,6 +1369,17 @@ static void __cpuinit coherency_setup(vo
+ * silly idea of putting something else there ...
+ */
+ switch (current_cpu_type()) {
++ case CPU_BMIPS3300:
++ {
++ u32 cm;
++ cm = read_c0_diag();
++ /* Enable icache */
++ cm |= (1 << 31);
++ /* Enable dcache */
++ cm |= (1 << 30);
++ write_c0_diag(cm);
++ }
++ break;
+ case CPU_R4000PC:
+ case CPU_R4000SC:
+ case CPU_R4000MC:
+@@ -1416,6 +1441,15 @@ void __cpuinit r4k_cache_init(void)
+ extern void build_copy_page(void);
+ struct cpuinfo_mips *c = ¤t_cpu_data;
+
++ /* Check if special workarounds are required */
++#ifdef CONFIG_BCM47XX
++ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
++ printk("Enabling BCM4710A0 cache workarounds.\n");
++ bcm4710 = 1;
++ } else
++#endif
++ bcm4710 = 0;
++
+ probe_pcache();
+ setup_scache();
+
+@@ -1476,6 +1510,14 @@ void __cpuinit r4k_cache_init(void)
+ #if !defined(CONFIG_MIPS_CMP)
+ local_r4k___flush_cache_all(NULL);
+ #endif
++#ifdef CONFIG_BCM47XX
++ {
++ static void (*_coherency_setup)(void);
++ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
++ _coherency_setup();
++ }
++#else
+ coherency_setup();
++#endif
+ board_cache_error_setup = r4k_cache_error_setup;
+ }
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -1314,6 +1314,9 @@ static void __cpuinit build_r4000_tlb_re
+ /* No need for uasm_i_nop */
+ }
+
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(&p);
++#endif
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
+ #else
+@@ -1845,6 +1848,9 @@ build_r4000_tlbchange_handler_head(u32 *
+ {
+ struct work_registers wr = build_get_work_registers(p);
+
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++#endif
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
+ #else
--- /dev/null
+--- a/arch/mips/include/asm/cpu-features.h
++++ b/arch/mips/include/asm/cpu-features.h
+@@ -110,6 +110,9 @@
+ #ifndef cpu_has_pindexed_dcache
+ #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+ #endif
++#ifndef cpu_use_kmap_coherent
++#define cpu_use_kmap_coherent 1
++#endif
+
+ /*
+ * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
+@@ -0,0 +1,13 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
++ */
++#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
++#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
++
++#define cpu_use_kmap_coherent 0
++
++#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -506,7 +506,7 @@ static inline void local_r4k_flush_cache
+ */
+ map_coherent = (cpu_has_dc_aliases &&
+ page_mapped(page) && !Page_dcache_dirty(page));
+- if (map_coherent)
++ if (map_coherent && cpu_use_kmap_coherent)
+ vaddr = kmap_coherent(page, addr);
+ else
+ vaddr = kmap_atomic(page);
+@@ -529,7 +529,7 @@ static inline void local_r4k_flush_cache
+ }
+
+ if (vaddr) {
+- if (map_coherent)
++ if (map_coherent && cpu_use_kmap_coherent)
+ kunmap_coherent();
+ else
+ kunmap_atomic(vaddr);
+--- a/arch/mips/mm/init.c
++++ b/arch/mips/mm/init.c
+@@ -208,7 +208,7 @@ void copy_user_highpage(struct page *to,
+ void *vfrom, *vto;
+
+ vto = kmap_atomic(to);
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ page_mapped(from) && !Page_dcache_dirty(from)) {
+ vfrom = kmap_coherent(from, vaddr);
+ copy_page(vto, vfrom);
+@@ -230,7 +230,7 @@ void copy_to_user_page(struct vm_area_st
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
+ {
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ page_mapped(page) && !Page_dcache_dirty(page)) {
+ void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ memcpy(vto, src, len);
+@@ -248,7 +248,7 @@ void copy_from_user_page(struct vm_area_
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
+ {
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ page_mapped(page) && !Page_dcache_dirty(page)) {
+ void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ memcpy(dst, vfrom, len);
--- /dev/null
+--- a/arch/mips/kernel/cpu-probe.c
++++ b/arch/mips/kernel/cpu-probe.c
+@@ -210,9 +210,6 @@ void __init check_wait(void)
+ break;
+
+ case CPU_74K:
+- cpu_wait = r4k_wait;
+- if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
+- cpu_wait = r4k_wait_irqoff;
+ break;
+
+ case CPU_TX49XX:
--- /dev/null
+--- a/arch/mips/bcm47xx/sprom.c
++++ b/arch/mips/bcm47xx/sprom.c
+@@ -652,12 +652,10 @@ static void bcm47xx_fill_sprom_ethernet(
+ static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
+ bool fallback)
+ {
+- nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0,
+- fallback);
++ nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0, true);
+ nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0,
+ fallback);
+- nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0,
+- fallback);
++ nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0, true);
+ nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo,
+ &sprom->boardflags_hi, fallback);
+ nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo,
--- /dev/null
+--- a/arch/mips/bcm47xx/sprom.c
++++ b/arch/mips/bcm47xx/sprom.c
+@@ -71,7 +71,7 @@ static void nvram_read_ ## type (const c
+ fallback); \
+ if (err < 0) \
+ return; \
+- err = kstrto ## type (buf, 0, &var); \
++ err = kstrto ## type(strim(buf), 0, &var); \
+ if (err) { \
+ pr_warn("can not parse nvram name %s%s%s with value %s got %i\n", \
+ prefix, name, postfix, buf, err); \
+@@ -99,7 +99,7 @@ static void nvram_read_u32_2(const char
+ err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback);
+ if (err < 0)
+ return;
+- err = kstrtou32(buf, 0, &val);
++ err = kstrtou32(strim(buf), 0, &val);
+ if (err) {
+ pr_warn("can not parse nvram name %s%s with value %s got %i\n",
+ prefix, name, buf, err);
+@@ -120,7 +120,7 @@ static void nvram_read_leddc(const char
+ err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback);
+ if (err < 0)
+ return;
+- err = kstrtou32(buf, 0, &val);
++ err = kstrtou32(strim(buf), 0, &val);
+ if (err) {
+ pr_warn("can not parse nvram name %s%s with value %s got %i\n",
+ prefix, name, buf, err);
--- /dev/null
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -410,10 +410,34 @@ static void b44_wap54g10_workaround(stru
+ error:
+ pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
+ }
++
++static void b44_bcm47xx_workarounds(struct b44 *bp)
++{
++ char buf[20];
++ struct ssb_device *sdev = bp->sdev;
++
++ /* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */
++ if (sdev->bus->sprom.board_num == 100) {
++ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
++ } else {
++ /* WL-HDD */
++ if (bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf)) >= 0 &&
++ !strncmp(buf, "WL300-", strlen("WL300-"))) {
++ if (sdev->bus->sprom.et0phyaddr == 0 &&
++ sdev->bus->sprom.et1phyaddr == 1)
++ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
++ }
++ }
++ return;
++}
+ #else
+ static inline void b44_wap54g10_workaround(struct b44 *bp)
+ {
+ }
++
++static inline void b44_bcm47xx_workarounds(struct b44 *bp)
++{
++}
+ #endif
+
+ static int b44_setup_phy(struct b44 *bp)
+@@ -422,6 +446,7 @@ static int b44_setup_phy(struct b44 *bp)
+ int err;
+
+ b44_wap54g10_workaround(bp);
++ b44_bcm47xx_workarounds(bp);
+
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
+ return 0;
+@@ -2104,6 +2129,8 @@ static int b44_get_invariants(struct b44
+ * valid PHY address. */
+ bp->phy_addr &= 0x1F;
+
++ b44_bcm47xx_workarounds(bp);
++
+ memcpy(bp->dev->dev_addr, addr, 6);
+
+ if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
--- /dev/null
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -187,10 +187,11 @@ static int b44_wait_bit(struct b44 *bp,
+ udelay(10);
+ }
+ if (i == timeout) {
++#if 0
+ if (net_ratelimit())
+ netdev_err(bp->dev, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
+ bit, reg, clear ? "clear" : "set");
+-
++#endif
+ return -ENODEV;
+ }
+ return 0;
--- /dev/null
+--- a/drivers/bcma/core.c
++++ b/drivers/bcma/core.c
+@@ -43,6 +43,7 @@ int bcma_core_enable(struct bcma_device
+ bcma_aread32(core, BCMA_IOCTL);
+
+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
++ bcma_aread32(core, BCMA_RESET_CTL);
+ udelay(1);
+
+ bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
--- /dev/null
+--- a/arch/mips/bcm47xx/Makefile
++++ b/arch/mips/bcm47xx/Makefile
+@@ -4,4 +4,5 @@
+ #
+
+ obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
++obj-y += board.o
+ obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
+--- /dev/null
++++ b/arch/mips/bcm47xx/board.c
+@@ -0,0 +1,219 @@
++#include <linux/export.h>
++#include <linux/string.h>
++#include <bcm47xx_board.h>
++#include <bcm47xx_nvram.h>
++
++struct bcm47xx_board_type {
++ const enum bcm47xx_board board;
++ const char *name;
++};
++
++struct bcm47xx_board_type_list {
++ struct bcm47xx_board_type board;
++ const char *value1;
++ const char *value2;
++};
++
++static const struct bcm47xx_board_type *bcm47xx_board = NULL;
++
++static const struct bcm47xx_board_type_list bcm47xx_board_list_model_name[] = {
++ {{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130",},
++ {{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330",},
++ { {0}, 0},
++};
++
++static const struct bcm47xx_board_type_list bcm47xx_board_list_model_no[] = {
++ {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700",},
++ { {0}, 0},
++};
++
++static const struct bcm47xx_board_type_list bcm47xx_board_list_hardware_version[] = {
++ {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-",},
++ {{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-",},
++ {{BCM47XX_BOARD_ASUS_WL500GPV1, "Asus WL500GP V1"}, "WL500gp-",},
++ {{BCM47XX_BOARD_ASUS_WL500GPV2, "Asus WL500GP V2"}, "WL500GPV2-",},
++ {{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-",},
++ {{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-",},
++ {{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301",},
++ { {0}, 0},
++};
++
++static const struct bcm47xx_board_type_list bcm47xx_board_list_productid[] = {
++ {{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U",},
++ {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D",},
++ {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RT-N10U",},
++ {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12",},
++ {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RT-N12B1",},
++ {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RT-N12C1",},
++ {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RT-N12D1",},
++ {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RT-N12HP",},
++ {{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U",},
++ {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16",},
++ {{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53",},
++ {{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U",},
++ { {0}, 0},
++};
++
++static const struct bcm47xx_board_type_list bcm47xx_board_list_ModelId[] = {
++ {{BCM47XX_BOARD_DELL_TM2300, "Dell WX-5565"}, "WX-5565",},
++ {{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G",},
++ {{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP",},
++ {{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G",},
++ { {0}, 0},
++};
++
++static const struct bcm47xx_board_type_list bcm47xx_board_list_melco_id[] = {
++ {{BCM47XX_BOARD_BUFFALO_WBR2_G54, "Buffalo WBR2-G54"}, "29bb0332",},
++ {{BCM47XX_BOARD_BUFFALO_WHR2_A54G54, "Buffalo WHR2-A54G54"}, "290441dd",},
++ {{BCM47XX_BOARD_BUFFALO_WHR_G125, "Buffalo WHR-G125"}, "32093",},
++ {{BCM47XX_BOARD_BUFFALO_WHR_G54S, "Buffalo WHR-G54S"}, "30182",},
++ {{BCM47XX_BOARD_BUFFALO_WHR_HP_G54, "Buffalo WHR-HP-G54"}, "30189",},
++ {{BCM47XX_BOARD_BUFFALO_WLA2_G54L, "Buffalo WLA2-G54L"}, "29129",},
++ {{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120",},
++ {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083",},
++ {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103",},
++ { {0}, 0},
++};
++
++static const struct bcm47xx_board_type_list bcm47xx_board_list_boot_hw[] = {
++ {{BCM47XX_BOARD_CISCO_M10V1, "Cisco M10"}, "M10", "1.0"}, /* like WRT160N v3.0 */
++ {{BCM47XX_BOARD_CISCO_M20V1, "Cisco M20"}, "M20", "1.0"}, /* like WRT310N v2.0 */
++ {{BCM47XX_BOARD_LINKSYS_E1000V1, "Linksys E1000 V1"}, "E100", "1.0"}, /* like WRT160N v3.0 */
++ {{BCM47XX_BOARD_LINKSYS_E1000V2, "Linksys E1000 V2"}, "E1000", "2.0"},
++ {{BCM47XX_BOARD_LINKSYS_E2000V1, "Linksys E2000 V1"}, "Linksys E2000", "1.0"},
++ {{BCM47XX_BOARD_LINKSYS_E3000V1, "Linksys E3000 V1"}, "E300", "1.0"}, /* like WRT610N v2.0 */
++ {{BCM47XX_BOARD_LINKSYS_E3200V1, "Linksys E3200 V1"}, "E3200", "1.0"},
++ {{BCM47XX_BOARD_LINKSYS_E4200V1, "Linksys E4200 V1"}, "E4200", "1.0"},
++ {{BCM47XX_BOARD_LINKSYS_WRT150NV11, "Linksys WRT150N V1.1"}, "WRT150N", "1.1"},
++ {{BCM47XX_BOARD_LINKSYS_WRT150NV1, "Linksys WRT150N V1"}, "WRT150N", "1"},
++ {{BCM47XX_BOARD_LINKSYS_WRT160NV1, "Linksys WRT160N V1"}, "WRT160N", "1.0"},
++ {{BCM47XX_BOARD_LINKSYS_WRT160NV3, "Linksys WRT160N V3"}, "WRT160N", "3.0"},
++ {{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"},
++ {{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"},
++ {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
++ {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
++ {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
++ { {0}, 0},
++};
++
++static const struct bcm47xx_board_type_list bcm47xx_board_list_board_id[] = {
++ {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, "Netgear WNDR3400 Vcna"}, "U12H155T01_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNDR3700V3, "Netgear WNDR3700 V3"}, "U12H194T00_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNDR4000, "Netgear WNDR4000"}, "U12H181T00_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNDR4500, "Netgear WNDR4500"}, "U12H189T00_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR",},
++ {{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR",},
++ { {0}, 0},
++};
++
++static const struct bcm47xx_board_type bcm47xx_board_unknown[] = {
++ {BCM47XX_BOARD_UNKNOWN, "Unknown Board"},
++};
++
++static inline int startswith(char *source, char *cmp)
++{
++ return !strncmp(source, cmp, strlen(cmp));
++}
++
++static const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
++{
++ char buf1[30];
++ char buf2[30];
++ const struct bcm47xx_board_type_list *e;
++
++ if (bcm47xx_nvram_getenv("model_name", buf1, sizeof(buf1)) >= 0) {
++ for (e = bcm47xx_board_list_model_name; e->value1; e++) {
++ if (!strcmp(buf1, e->value1))
++ return &e->board;
++ }
++ }
++
++ if (bcm47xx_nvram_getenv("model_no", buf1, sizeof(buf1)) >= 0) {
++ for (e = bcm47xx_board_list_model_no; e->value1; e++) {
++ if (strstarts(buf1, e->value1))
++ return &e->board;
++ }
++ }
++
++ if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0) {
++ for (e = bcm47xx_board_list_hardware_version; e->value1; e++) {
++ if (strstarts(buf1, e->value1))
++ return &e->board;
++ }
++ }
++
++ if (bcm47xx_nvram_getenv("productid", buf1, sizeof(buf1)) >= 0) {
++ for (e = bcm47xx_board_list_productid; e->value1; e++) {
++ if (!strcmp(buf1, e->value1))
++ return &e->board;
++ }
++ }
++
++ if (bcm47xx_nvram_getenv("ModelId", buf1, sizeof(buf1)) >= 0) {
++ for (e = bcm47xx_board_list_ModelId; e->value1; e++) {
++ if (!strcmp(buf1, e->value1))
++ return &e->board;
++ }
++ }
++
++ if (bcm47xx_nvram_getenv("melco_id", buf1, sizeof(buf1)) >= 0 ||
++ bcm47xx_nvram_getenv("buf1falo_id", buf1, sizeof(buf1)) >= 0) {
++ /* buffalo hardware, check id for specific hardware matches */
++ for (e = bcm47xx_board_list_melco_id; e->value1; e++) {
++ if (!strcmp(buf1, e->value1))
++ return &e->board;
++ }
++ }
++
++ if (bcm47xx_nvram_getenv("boot_hw_model", buf1, sizeof(buf1)) >= 0 &&
++ bcm47xx_nvram_getenv("boot_hw_ver", buf2, sizeof(buf2)) >= 0) {
++ for (e = bcm47xx_board_list_boot_hw; e->value1; e++) {
++ if (!strcmp(buf1, e->value1) && !strcmp(buf2, e->value2))
++ return &e->board;
++ }
++ }
++
++ if (bcm47xx_nvram_getenv("board_id", buf1, sizeof(buf1)) >= 0) {
++ for (e = bcm47xx_board_list_board_id; e->value1; e++) {
++ if (!strcmp(buf1, e->value1))
++ return &e->board;
++ }
++ }
++ return bcm47xx_board_unknown;
++}
++
++static void bcm47xx_board_detect(void)
++{
++ char buf[15];
++
++ if (bcm47xx_board != NULL)
++ return;
++ /* check if the nvram is available */
++ if (bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf)) == -ENXIO)
++ return;
++
++ bcm47xx_board = bcm47xx_board_get_nvram();
++ pr_info("Found board: \"%s\"\n", bcm47xx_board->name);
++}
++
++enum bcm47xx_board bcm47xx_board_get(void)
++{
++ bcm47xx_board_detect();
++ return bcm47xx_board->board;
++}
++EXPORT_SYMBOL(bcm47xx_board_get);
++
++const char *bcm47xx_board_get_name(void)
++{
++ bcm47xx_board_detect();
++ return bcm47xx_board->name;
++}
++EXPORT_SYMBOL(bcm47xx_board_get_name);
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+@@ -0,0 +1,89 @@
++#ifndef __BCM47XX_BOARD_H
++#define __BCM47XX_BOARD_H
++
++enum bcm47xx_board {
++ BCM47XX_BOARD_ASUS_RTAC66U,
++ BCM47XX_BOARD_ASUS_RTN10D,
++ BCM47XX_BOARD_ASUS_RTN10U,
++ BCM47XX_BOARD_ASUS_RTN12,
++ BCM47XX_BOARD_ASUS_RTN12B1,
++ BCM47XX_BOARD_ASUS_RTN12C1,
++ BCM47XX_BOARD_ASUS_RTN12D1,
++ BCM47XX_BOARD_ASUS_RTN12HP,
++ BCM47XX_BOARD_ASUS_RTN15U,
++ BCM47XX_BOARD_ASUS_RTN16,
++ BCM47XX_BOARD_ASUS_RTN53,
++ BCM47XX_BOARD_ASUS_RTN66U,
++ BCM47XX_BOARD_ASUS_WL330GE,
++ BCM47XX_BOARD_ASUS_WL500GPV1,
++ BCM47XX_BOARD_ASUS_WL500GPV2,
++ BCM47XX_BOARD_ASUS_WL520GC,
++ BCM47XX_BOARD_ASUS_WL520GU,
++ BCM47XX_BOARD_ASUS_WL700GE,
++
++ BCM47XX_BOARD_BELKIN_F7D4301,
++
++ BCM47XX_BOARD_BUFFALO_WBR2_G54,
++ BCM47XX_BOARD_BUFFALO_WHR2_A54G54,
++ BCM47XX_BOARD_BUFFALO_WHR_G125,
++ BCM47XX_BOARD_BUFFALO_WHR_G54S,
++ BCM47XX_BOARD_BUFFALO_WHR_HP_G54,
++ BCM47XX_BOARD_BUFFALO_WLA2_G54L,
++ BCM47XX_BOARD_BUFFALO_WZR_G300N,
++ BCM47XX_BOARD_BUFFALO_WZR_RS_G54,
++ BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP,
++
++ BCM47XX_BOARD_CISCO_M10V1,
++ BCM47XX_BOARD_CISCO_M20V1,
++
++ BCM47XX_BOARD_DELL_TM2300,
++
++ BCM47XX_BOARD_DLINK_DIR130,
++ BCM47XX_BOARD_DLINK_DIR330,
++
++ BCM47XX_BOARD_LINKSYS_E1000V1,
++ BCM47XX_BOARD_LINKSYS_E1000V2,
++ BCM47XX_BOARD_LINKSYS_E2000V1,
++ BCM47XX_BOARD_LINKSYS_E3000V1,
++ BCM47XX_BOARD_LINKSYS_E3200V1,
++ BCM47XX_BOARD_LINKSYS_E4200V1,
++ BCM47XX_BOARD_LINKSYS_WRT150NV1,
++ BCM47XX_BOARD_LINKSYS_WRT150NV11,
++ BCM47XX_BOARD_LINKSYS_WRT160NV1,
++ BCM47XX_BOARD_LINKSYS_WRT160NV3,
++ BCM47XX_BOARD_LINKSYS_WRT300NV11,
++ BCM47XX_BOARD_LINKSYS_WRT310NV2,
++ BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
++ BCM47XX_BOARD_LINKSYS_WRT610NV1,
++ BCM47XX_BOARD_LINKSYS_WRT610NV2,
++
++ BCM47XX_BOARD_MOTOROLA_WE800G,
++ BCM47XX_BOARD_MOTOROLA_WR850GP,
++ BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
++
++ BCM47XX_BOARD_NETGEAR_WGR614V8,
++ BCM47XX_BOARD_NETGEAR_WGR614V9,
++ BCM47XX_BOARD_NETGEAR_WNDR3300,
++ BCM47XX_BOARD_NETGEAR_WNDR3400V1,
++ BCM47XX_BOARD_NETGEAR_WNDR3400VCNA,
++ BCM47XX_BOARD_NETGEAR_WNDR3700V3,
++ BCM47XX_BOARD_NETGEAR_WNDR4000,
++ BCM47XX_BOARD_NETGEAR_WNDR4500,
++ BCM47XX_BOARD_NETGEAR_WNR2000,
++ BCM47XX_BOARD_NETGEAR_WNR3500L,
++ BCM47XX_BOARD_NETGEAR_WNR3500U,
++ BCM47XX_BOARD_NETGEAR_WNR3500V2,
++ BCM47XX_BOARD_NETGEAR_WNR3500V2VC,
++ BCM47XX_BOARD_NETGEAR_WNR834BV2,
++
++ /* TODO */
++ BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE,
++
++ BCM47XX_BOARD_UNKNOWN,
++ BCM47XX_BOARD_NON,
++};
++
++extern enum bcm47xx_board bcm47xx_board_get(void);
++extern const char *bcm47xx_board_get_name(void);
++
++#endif /* __BCM47XX_BOARD_H */
--- /dev/null
+--- a/arch/mips/bcm47xx/prom.c
++++ b/arch/mips/bcm47xx/prom.c
+@@ -32,10 +32,35 @@
+ #include <asm/bootinfo.h>
+ #include <asm/fw/cfe/cfe_api.h>
+ #include <asm/fw/cfe/cfe_error.h>
++#include <bcm47xx.h>
++#include <bcm47xx_board.h>
++
++static u16 get_chip_id(void)
++{
++ switch (bcm47xx_bus_type) {
++#ifdef CONFIG_BCM47XX_SSB
++ case BCM47XX_BUS_TYPE_SSB:
++ return bcm47xx_bus.ssb.chip_id;
++#endif
++#ifdef CONFIG_BCM47XX_BCMA
++ case BCM47XX_BUS_TYPE_BCMA:
++ return bcm47xx_bus.bcma.bus.chipinfo.id;
++#endif
++ }
++ return 0;
++}
+
+ const char *get_system_type(void)
+ {
+- return "Broadcom BCM47XX";
++ static char buf[128];
++ u16 chip_id = get_chip_id();
++
++ snprintf(buf, sizeof(buf),
++ (chip_id > 0x9999) ? "Broadcom BCM%d (%s)" :
++ "Broadcom BCM%04X (%s)",
++ chip_id, bcm47xx_board_get_name());
++
++ return buf;
+ }
+
+ static __init int prom_init_cfe(void)
--- /dev/null
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -26,6 +26,7 @@ struct ssb_sprom_core_pwr_info {
+
+ struct ssb_sprom {
+ u8 revision;
++ u8 country_code; /* Country Code */
+ u8 il0mac[6]; /* MAC address for 802.11b/g */
+ u8 et0mac[6]; /* MAC address for Ethernet */
+ u8 et1mac[6]; /* MAC address for 802.11a */
+@@ -36,7 +37,6 @@ struct ssb_sprom {
+ u16 board_rev; /* Board revision number from SPROM. */
+ u16 board_num; /* Board number from SPROM. */
+ u16 board_type; /* Board type from SPROM. */
+- u8 country_code; /* Country Code */
+ char alpha2[2]; /* Country Code as two chars like EU or US */
+ u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
+ u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
--- /dev/null
+This prevents the options from being delete with make kernel_oldconfig.
+---
+ drivers/ssb/Kconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/bcma/Kconfig
++++ b/drivers/bcma/Kconfig
+@@ -37,6 +37,7 @@ config BCMA_DRIVER_PCI_HOSTMODE
+ config BCMA_HOST_SOC
+ bool
+ depends on BCMA_DRIVER_MIPS
++ select USB_HCD_BCMA if USB_EHCI_HCD || USB_OHCI_HCD
+
+ config BCMA_DRIVER_MIPS
+ bool "BCMA Broadcom MIPS core driver"
+--- a/drivers/ssb/Kconfig
++++ b/drivers/ssb/Kconfig
+@@ -146,6 +146,7 @@ config SSB_SFLASH
+ config SSB_EMBEDDED
+ bool
+ depends on SSB_DRIVER_MIPS
++ select USB_HCD_SSB if USB_EHCI_HCD || USB_OHCI_HCD
+ default y
+
+ config SSB_DRIVER_EXTIF
--- /dev/null
+--- a/arch/mips/include/asm/cacheflush.h
++++ b/arch/mips/include/asm/cacheflush.h
+@@ -32,7 +32,7 @@
+ extern void (*flush_cache_all)(void);
+ extern void (*__flush_cache_all)(void);
+ extern void (*flush_cache_mm)(struct mm_struct *mm);
+-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
++#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+ extern void (*flush_cache_range)(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end);
+ extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
--- /dev/null
+--- a/arch/mips/include/asm/page.h
++++ b/arch/mips/include/asm/page.h
+@@ -46,6 +46,7 @@
+ #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
+
+ #include <linux/pfn.h>
++#include <asm/cpu-features.h>
+ #include <asm/io.h>
+
+ extern void build_clear_page(void);
+@@ -81,13 +82,16 @@ static inline void clear_user_page(void
+ flush_data_cache_page((unsigned long)addr);
+ }
+
+-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+- struct page *to);
+-struct vm_area_struct;
+-extern void copy_user_highpage(struct page *to, struct page *from,
+- unsigned long vaddr, struct vm_area_struct *vma);
++static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
++ struct page *to)
++{
++ extern void (*flush_data_cache_page)(unsigned long addr);
+
+-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
++ copy_page(vto, vfrom);
++ if (!cpu_has_ic_fills_f_dc ||
++ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
++ flush_data_cache_page((unsigned long)vto);
++}
+
+ /*
+ * These are used to make use of C type-checking..
+--- a/arch/mips/mm/init.c
++++ b/arch/mips/mm/init.c
+@@ -202,30 +202,6 @@ void kunmap_coherent(void)
+ preempt_check_resched();
+ }
+
+-void copy_user_highpage(struct page *to, struct page *from,
+- unsigned long vaddr, struct vm_area_struct *vma)
+-{
+- void *vfrom, *vto;
+-
+- vto = kmap_atomic(to);
+- if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+- page_mapped(from) && !Page_dcache_dirty(from)) {
+- vfrom = kmap_coherent(from, vaddr);
+- copy_page(vto, vfrom);
+- kunmap_coherent();
+- } else {
+- vfrom = kmap_atomic(from);
+- copy_page(vto, vfrom);
+- kunmap_atomic(vfrom);
+- }
+- if ((!cpu_has_ic_fills_f_dc) ||
+- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+- flush_data_cache_page((unsigned long)vto);
+- kunmap_atomic(vto);
+- /* Make sure this page is cleared on other CPU's too before using it */
+- smp_wmb();
+-}
+-
+ void copy_to_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
--- /dev/null
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -198,3 +198,30 @@ int bcm47xx_nvram_getenv(char *name, cha
+ return -ENOENT;
+ }
+ EXPORT_SYMBOL(bcm47xx_nvram_getenv);
++
++char *nvram_get(const char *name)
++{
++ char *var, *value, *end, *eq;
++
++ if (!name)
++ return NULL;
++
++ if (!nvram_buf[0])
++ nvram_init();
++
++ /* Look for name=value and return value */
++ var = &nvram_buf[sizeof(struct nvram_header)];
++ end = nvram_buf + sizeof(nvram_buf) - 2;
++ end[0] = end[1] = '\0';
++ for (; *var; var = value + strlen(value) + 1) {
++ eq = strchr(var, '=');
++ if (!eq)
++ break;
++ value = eq + 1;
++ if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
++ return value;
++ }
++
++ return NULL;
++}
++EXPORT_SYMBOL(nvram_get);
+--- a/arch/mips/bcm47xx/Makefile
++++ b/arch/mips/bcm47xx/Makefile
+@@ -5,4 +5,5 @@
+
+ obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
+ obj-y += board.o
++obj-y += gpio.o
+ obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
+--- /dev/null
++++ b/arch/mips/bcm47xx/gpio.c
+@@ -0,0 +1,119 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
++ * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de>
++ *
++ * Parts of this file are based on Atheros AR71XX/AR724X/AR913X GPIO
++ */
++
++#include <linux/export.h>
++#include <linux/gpio.h>
++#include <linux/ssb/ssb_embedded.h>
++#include <linux/bcma/bcma.h>
++
++#include <bcm47xx.h>
++
++/* low level BCM47xx gpio api */
++u32 bcm47xx_gpio_in(u32 mask)
++{
++ switch (bcm47xx_bus_type) {
++#ifdef CONFIG_BCM47XX_SSB
++ case BCM47XX_BUS_TYPE_SSB:
++ return ssb_gpio_in(&bcm47xx_bus.ssb, mask);
++#endif
++#ifdef CONFIG_BCM47XX_BCMA
++ case BCM47XX_BUS_TYPE_BCMA:
++ return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, mask);
++#endif
++ }
++ return -EINVAL;
++}
++EXPORT_SYMBOL(bcm47xx_gpio_in);
++
++u32 bcm47xx_gpio_out(u32 mask, u32 value)
++{
++ switch (bcm47xx_bus_type) {
++#ifdef CONFIG_BCM47XX_SSB
++ case BCM47XX_BUS_TYPE_SSB:
++ return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value);
++#endif
++#ifdef CONFIG_BCM47XX_BCMA
++ case BCM47XX_BUS_TYPE_BCMA:
++ return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask,
++ value);
++#endif
++ }
++ return -EINVAL;
++}
++EXPORT_SYMBOL(bcm47xx_gpio_out);
++
++u32 bcm47xx_gpio_outen(u32 mask, u32 value)
++{
++ switch (bcm47xx_bus_type) {
++#ifdef CONFIG_BCM47XX_SSB
++ case BCM47XX_BUS_TYPE_SSB:
++ return ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value);
++#endif
++#ifdef CONFIG_BCM47XX_BCMA
++ case BCM47XX_BUS_TYPE_BCMA:
++ return bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc,
++ mask, value);
++#endif
++ }
++ return -EINVAL;
++}
++EXPORT_SYMBOL(bcm47xx_gpio_outen);
++
++u32 bcm47xx_gpio_control(u32 mask, u32 value)
++{
++ switch (bcm47xx_bus_type) {
++#ifdef CONFIG_BCM47XX_SSB
++ case BCM47XX_BUS_TYPE_SSB:
++ return ssb_gpio_control(&bcm47xx_bus.ssb, mask, value);
++#endif
++#ifdef CONFIG_BCM47XX_BCMA
++ case BCM47XX_BUS_TYPE_BCMA:
++ return bcma_chipco_gpio_control(&bcm47xx_bus.bcma.bus.drv_cc,
++ mask, value);
++#endif
++ }
++ return -EINVAL;
++}
++EXPORT_SYMBOL(bcm47xx_gpio_control);
++
++u32 bcm47xx_gpio_intmask(u32 mask, u32 value)
++{
++ switch (bcm47xx_bus_type) {
++#ifdef CONFIG_BCM47XX_SSB
++ case BCM47XX_BUS_TYPE_SSB:
++ return ssb_gpio_intmask(&bcm47xx_bus.ssb, mask, value);
++#endif
++#ifdef CONFIG_BCM47XX_BCMA
++ case BCM47XX_BUS_TYPE_BCMA:
++ return bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc,
++ mask, value);
++#endif
++ }
++ return -EINVAL;
++}
++EXPORT_SYMBOL(bcm47xx_gpio_intmask);
++
++u32 bcm47xx_gpio_polarity(u32 mask, u32 value)
++{
++ switch (bcm47xx_bus_type) {
++#ifdef CONFIG_BCM47XX_SSB
++ case BCM47XX_BUS_TYPE_SSB:
++ return ssb_gpio_polarity(&bcm47xx_bus.ssb, mask, value);
++#endif
++#ifdef CONFIG_BCM47XX_BCMA
++ case BCM47XX_BUS_TYPE_BCMA:
++ return bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc,
++ mask, value);
++#endif
++ }
++ return -EINVAL;
++}
++EXPORT_SYMBOL(bcm47xx_gpio_polarity);
+--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
++++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
+@@ -14,4 +14,11 @@ static inline int irq_to_gpio(unsigned i
+ return -EINVAL;
+ }
+
++u32 bcm47xx_gpio_in(u32 mask);
++u32 bcm47xx_gpio_out(u32 mask, u32 value);
++u32 bcm47xx_gpio_outen(u32 mask, u32 value);
++u32 bcm47xx_gpio_control(u32 mask, u32 value);
++u32 bcm47xx_gpio_intmask(u32 mask, u32 value);
++u32 bcm47xx_gpio_polarity(u32 mask, u32 value);
++
+ #endif
--- /dev/null
+--- a/arch/mips/bcm47xx/time.c
++++ b/arch/mips/bcm47xx/time.c
+@@ -27,10 +27,14 @@
+ #include <linux/ssb/ssb.h>
+ #include <asm/time.h>
+ #include <bcm47xx.h>
++#include <bcm47xx_nvram.h>
+
+ void __init plat_time_init(void)
+ {
+ unsigned long hz = 0;
++ u16 chip_id = 0;
++ char buf[10];
++ int len;
+
+ /*
+ * Use deterministic values for initial counter interrupt
+@@ -43,15 +47,26 @@ void __init plat_time_init(void)
+ #ifdef CONFIG_BCM47XX_SSB
+ case BCM47XX_BUS_TYPE_SSB:
+ hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
++ chip_id = bcm47xx_bus.ssb.chip_id;
+ break;
+ #endif
+ #ifdef CONFIG_BCM47XX_BCMA
+ case BCM47XX_BUS_TYPE_BCMA:
+ hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
++ chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
+ break;
+ #endif
+ }
+
++ if (chip_id == 0x5354) {
++ len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
++ if (len >= 0 && !strncmp(buf, "200", 4))
++ hz = 100000000;
++ len = bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf));
++ if (len >= 0 && !strncmp(buf, "WL520G", 6))
++ hz = 100000000;
++
++ }
+ if (!hz)
+ hz = 100000000;
+
--- /dev/null
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -971,6 +971,7 @@ config ATH79_WDT
+ config BCM47XX_WDT
+ tristate "Broadcom BCM47xx Watchdog Timer"
+ depends on BCM47XX
++ select WATCHDOG_CORE
+ help
+ Hardware driver for the Broadcom BCM47xx Watchdog Timer.
+
+--- a/drivers/watchdog/bcm47xx_wdt.c
++++ b/drivers/watchdog/bcm47xx_wdt.c
+@@ -14,15 +14,12 @@
+
+ #include <linux/bitops.h>
+ #include <linux/errno.h>
+-#include <linux/fs.h>
+ #include <linux/init.h>
+ #include <linux/kernel.h>
+-#include <linux/miscdevice.h>
+ #include <linux/module.h>
+ #include <linux/moduleparam.h>
+ #include <linux/reboot.h>
+ #include <linux/types.h>
+-#include <linux/uaccess.h>
+ #include <linux/watchdog.h>
+ #include <linux/timer.h>
+ #include <linux/jiffies.h>
+@@ -41,15 +38,11 @@ module_param(wdt_time, int, 0);
+ MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default="
+ __MODULE_STRING(WDT_DEFAULT_TIME) ")");
+
+-#ifdef CONFIG_WATCHDOG_NOWAYOUT
+ module_param(nowayout, bool, 0);
+ MODULE_PARM_DESC(nowayout,
+ "Watchdog cannot be stopped once started (default="
+ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+-#endif
+
+-static unsigned long bcm47xx_wdt_busy;
+-static char expect_release;
+ static struct timer_list wdt_timer;
+ static atomic_t ticks;
+
+@@ -97,29 +90,31 @@ static void bcm47xx_timer_tick(unsigned
+ }
+ }
+
+-static inline void bcm47xx_wdt_pet(void)
++static int bcm47xx_wdt_keepalive(struct watchdog_device *wdd)
+ {
+ atomic_set(&ticks, wdt_time);
++
++ return 0;
+ }
+
+-static void bcm47xx_wdt_start(void)
++static int bcm47xx_wdt_start(struct watchdog_device *wdd)
+ {
+ bcm47xx_wdt_pet();
+ bcm47xx_timer_tick(0);
++
++ return 0;
+ }
+
+-static void bcm47xx_wdt_pause(void)
++static int bcm47xx_wdt_stop(struct watchdog_device *wdd)
+ {
+ del_timer_sync(&wdt_timer);
+ bcm47xx_wdt_hw_stop();
+-}
+
+-static void bcm47xx_wdt_stop(void)
+-{
+- bcm47xx_wdt_pause();
++ return 0;
+ }
+
+-static int bcm47xx_wdt_settimeout(int new_time)
++static int bcm47xx_wdt_set_timeout(struct watchdog_device *wdd,
++ unsigned int new_time)
+ {
+ if ((new_time <= 0) || (new_time > WDT_MAX_TIME))
+ return -EINVAL;
+@@ -128,51 +123,6 @@ static int bcm47xx_wdt_settimeout(int ne
+ return 0;
+ }
+
+-static int bcm47xx_wdt_open(struct inode *inode, struct file *file)
+-{
+- if (test_and_set_bit(0, &bcm47xx_wdt_busy))
+- return -EBUSY;
+-
+- bcm47xx_wdt_start();
+- return nonseekable_open(inode, file);
+-}
+-
+-static int bcm47xx_wdt_release(struct inode *inode, struct file *file)
+-{
+- if (expect_release == 42) {
+- bcm47xx_wdt_stop();
+- } else {
+- pr_crit("Unexpected close, not stopping watchdog!\n");
+- bcm47xx_wdt_start();
+- }
+-
+- clear_bit(0, &bcm47xx_wdt_busy);
+- expect_release = 0;
+- return 0;
+-}
+-
+-static ssize_t bcm47xx_wdt_write(struct file *file, const char __user *data,
+- size_t len, loff_t *ppos)
+-{
+- if (len) {
+- if (!nowayout) {
+- size_t i;
+-
+- expect_release = 0;
+-
+- for (i = 0; i != len; i++) {
+- char c;
+- if (get_user(c, data + i))
+- return -EFAULT;
+- if (c == 'V')
+- expect_release = 42;
+- }
+- }
+- bcm47xx_wdt_pet();
+- }
+- return len;
+-}
+-
+ static const struct watchdog_info bcm47xx_wdt_info = {
+ .identity = DRV_NAME,
+ .options = WDIOF_SETTIMEOUT |
+@@ -180,80 +130,25 @@ static const struct watchdog_info bcm47x
+ WDIOF_MAGICCLOSE,
+ };
+
+-static long bcm47xx_wdt_ioctl(struct file *file,
+- unsigned int cmd, unsigned long arg)
+-{
+- void __user *argp = (void __user *)arg;
+- int __user *p = argp;
+- int new_value, retval = -EINVAL;
+-
+- switch (cmd) {
+- case WDIOC_GETSUPPORT:
+- return copy_to_user(argp, &bcm47xx_wdt_info,
+- sizeof(bcm47xx_wdt_info)) ? -EFAULT : 0;
+-
+- case WDIOC_GETSTATUS:
+- case WDIOC_GETBOOTSTATUS:
+- return put_user(0, p);
+-
+- case WDIOC_SETOPTIONS:
+- if (get_user(new_value, p))
+- return -EFAULT;
+-
+- if (new_value & WDIOS_DISABLECARD) {
+- bcm47xx_wdt_stop();
+- retval = 0;
+- }
+-
+- if (new_value & WDIOS_ENABLECARD) {
+- bcm47xx_wdt_start();
+- retval = 0;
+- }
+-
+- return retval;
+-
+- case WDIOC_KEEPALIVE:
+- bcm47xx_wdt_pet();
+- return 0;
+-
+- case WDIOC_SETTIMEOUT:
+- if (get_user(new_value, p))
+- return -EFAULT;
+-
+- if (bcm47xx_wdt_settimeout(new_value))
+- return -EINVAL;
+-
+- bcm47xx_wdt_pet();
+-
+- case WDIOC_GETTIMEOUT:
+- return put_user(wdt_time, p);
+-
+- default:
+- return -ENOTTY;
+- }
+-}
+-
+ static int bcm47xx_wdt_notify_sys(struct notifier_block *this,
+- unsigned long code, void *unused)
++ unsigned long code, void *unused)
+ {
+ if (code == SYS_DOWN || code == SYS_HALT)
+ bcm47xx_wdt_stop();
+ return NOTIFY_DONE;
+ }
+
+-static const struct file_operations bcm47xx_wdt_fops = {
++static struct watchdog_ops bcm47xx_wdt_ops = {
+ .owner = THIS_MODULE,
+- .llseek = no_llseek,
+- .unlocked_ioctl = bcm47xx_wdt_ioctl,
+- .open = bcm47xx_wdt_open,
+- .release = bcm47xx_wdt_release,
+- .write = bcm47xx_wdt_write,
++ .start = bcm47xx_wdt_start,
++ .stop = bcm47xx_wdt_stop,
++ .ping = bcm47xx_wdt_keepalive,
++ .set_timeout = bcm47xx_wdt_set_timeout,
+ };
+
+-static struct miscdevice bcm47xx_wdt_miscdev = {
+- .minor = WATCHDOG_MINOR,
+- .name = "watchdog",
+- .fops = &bcm47xx_wdt_fops,
++static struct watchdog_device bcm47xx_wdt_wdd = {
++ .info = &bcm47xx_wdt_info,
++ .ops = &bcm47xx_wdt_ops,
+ };
+
+ static struct notifier_block bcm47xx_wdt_notifier = {
+@@ -274,12 +169,13 @@ static int __init bcm47xx_wdt_init(void)
+ pr_info("wdt_time value must be 0 < wdt_time < %d, using %d\n",
+ (WDT_MAX_TIME + 1), wdt_time);
+ }
++ watchdog_set_nowayout(&bcm47xx_wdt_wdd, nowayout);
+
+ ret = register_reboot_notifier(&bcm47xx_wdt_notifier);
+ if (ret)
+ return ret;
+
+- ret = misc_register(&bcm47xx_wdt_miscdev);
++ ret = watchdog_register_device(&bcm47xx_wdt_wdd);
+ if (ret) {
+ unregister_reboot_notifier(&bcm47xx_wdt_notifier);
+ return ret;
+@@ -292,10 +188,7 @@ static int __init bcm47xx_wdt_init(void)
+
+ static void __exit bcm47xx_wdt_exit(void)
+ {
+- if (!nowayout)
+- bcm47xx_wdt_stop();
+-
+- misc_deregister(&bcm47xx_wdt_miscdev);
++ watchdog_unregister_device(&bcm47xx_wdt_wdd);
+
+ unregister_reboot_notifier(&bcm47xx_wdt_notifier);
+ }
+@@ -306,4 +199,3 @@ module_exit(bcm47xx_wdt_exit);
+ MODULE_AUTHOR("Aleksandar Radovanovic");
+ MODULE_DESCRIPTION("Watchdog driver for Broadcom BCM47xx");
+ MODULE_LICENSE("GPL");
+-MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
--- /dev/null
+--- a/drivers/watchdog/bcm47xx_wdt.c
++++ b/drivers/watchdog/bcm47xx_wdt.c
+@@ -3,6 +3,7 @@
+ *
+ * Copyright (C) 2008 Aleksandar Radovanovic <biblbroks@sezampro.rs>
+ * Copyright (C) 2009 Matthieu CASTET <castet.matthieu@free.fr>
++ * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+@@ -12,19 +13,19 @@
+
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
++#include <linux/bcm47xx_wdt.h>
+ #include <linux/bitops.h>
+ #include <linux/errno.h>
+ #include <linux/init.h>
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/moduleparam.h>
++#include <linux/platform_device.h>
+ #include <linux/reboot.h>
+ #include <linux/types.h>
+ #include <linux/watchdog.h>
+ #include <linux/timer.h>
+ #include <linux/jiffies.h>
+-#include <linux/ssb/ssb_embedded.h>
+-#include <asm/mach-bcm47xx/bcm47xx.h>
+
+ #define DRV_NAME "bcm47xx_wdt"
+
+@@ -43,48 +44,19 @@ MODULE_PARM_DESC(nowayout,
+ "Watchdog cannot be stopped once started (default="
+ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+-static struct timer_list wdt_timer;
+-static atomic_t ticks;
+-
+-static inline void bcm47xx_wdt_hw_start(void)
++static inline struct bcm47xx_wdt *bcm47xx_wdt_get(struct watchdog_device *wdd)
+ {
+- /* this is 2,5s on 100Mhz clock and 2s on 133 Mhz */
+- switch (bcm47xx_bus_type) {
+-#ifdef CONFIG_BCM47XX_SSB
+- case BCM47XX_BUS_TYPE_SSB:
+- ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0xfffffff);
+- break;
+-#endif
+-#ifdef CONFIG_BCM47XX_BCMA
+- case BCM47XX_BUS_TYPE_BCMA:
+- bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc,
+- 0xfffffff);
+- break;
+-#endif
+- }
++ return container_of(wdd, struct bcm47xx_wdt, wdd);
+ }
+
+-static inline int bcm47xx_wdt_hw_stop(void)
++static void bcm47xx_timer_tick(unsigned long data)
+ {
+- switch (bcm47xx_bus_type) {
+-#ifdef CONFIG_BCM47XX_SSB
+- case BCM47XX_BUS_TYPE_SSB:
+- return ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
+-#endif
+-#ifdef CONFIG_BCM47XX_BCMA
+- case BCM47XX_BUS_TYPE_BCMA:
+- bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 0);
+- return 0;
+-#endif
+- }
+- return -EINVAL;
+-}
++ struct bcm47xx_wdt *wdt = (struct bcm47xx_wdt *)data;
++ u32 next_tick = min(wdt->wdd.timeout * 1000, wdt->max_timer_ms);
+
+-static void bcm47xx_timer_tick(unsigned long unused)
+-{
+- if (!atomic_dec_and_test(&ticks)) {
+- bcm47xx_wdt_hw_start();
+- mod_timer(&wdt_timer, jiffies + HZ);
++ if (!atomic_dec_and_test(&wdt->soft_ticks)) {
++ wdt->timer_set_ms(wdt, next_tick);
++ mod_timer(&wdt->soft_timer, jiffies + HZ);
+ } else {
+ pr_crit("Watchdog will fire soon!!!\n");
+ }
+@@ -92,23 +64,29 @@ static void bcm47xx_timer_tick(unsigned
+
+ static int bcm47xx_wdt_keepalive(struct watchdog_device *wdd)
+ {
+- atomic_set(&ticks, wdt_time);
++ struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
++
++ atomic_set(&wdt->soft_ticks, wdd->timeout);
+
+ return 0;
+ }
+
+ static int bcm47xx_wdt_start(struct watchdog_device *wdd)
+ {
+- bcm47xx_wdt_pet();
+- bcm47xx_timer_tick(0);
++ struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
++
++ bcm47xx_wdt_keepalive(wdd);
++ bcm47xx_timer_tick((unsigned long)wdt);
+
+ return 0;
+ }
+
+ static int bcm47xx_wdt_stop(struct watchdog_device *wdd)
+ {
+- del_timer_sync(&wdt_timer);
+- bcm47xx_wdt_hw_stop();
++ struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
++
++ del_timer_sync(&wdt->soft_timer);
++ wdt->timer_set(wdt, 0);
+
+ return 0;
+ }
+@@ -116,10 +94,13 @@ static int bcm47xx_wdt_stop(struct watch
+ static int bcm47xx_wdt_set_timeout(struct watchdog_device *wdd,
+ unsigned int new_time)
+ {
+- if ((new_time <= 0) || (new_time > WDT_MAX_TIME))
++ if (new_time < 1 || new_time > WDT_MAX_TIME) {
++ pr_warn("timeout value must be 1<=x<=%d, using %d\n",
++ WDT_MAX_TIME, new_time);
+ return -EINVAL;
++ }
+
+- wdt_time = new_time;
++ wdd->timeout = new_time;
+ return 0;
+ }
+
+@@ -133,8 +114,11 @@ static const struct watchdog_info bcm47x
+ static int bcm47xx_wdt_notify_sys(struct notifier_block *this,
+ unsigned long code, void *unused)
+ {
++ struct bcm47xx_wdt *wdt;
++
++ wdt = container_of(this, struct bcm47xx_wdt, notifier);
+ if (code == SYS_DOWN || code == SYS_HALT)
+- bcm47xx_wdt_stop();
++ wdt->wdd.ops->stop(&wdt->wdd);
+ return NOTIFY_DONE;
+ }
+
+@@ -146,56 +130,72 @@ static struct watchdog_ops bcm47xx_wdt_o
+ .set_timeout = bcm47xx_wdt_set_timeout,
+ };
+
+-static struct watchdog_device bcm47xx_wdt_wdd = {
+- .info = &bcm47xx_wdt_info,
+- .ops = &bcm47xx_wdt_ops,
+-};
+-
+-static struct notifier_block bcm47xx_wdt_notifier = {
+- .notifier_call = bcm47xx_wdt_notify_sys,
+-};
+-
+-static int __init bcm47xx_wdt_init(void)
++static int bcm47xx_wdt_probe(struct platform_device *pdev)
+ {
+ int ret;
++ struct bcm47xx_wdt *wdt = dev_get_platdata(&pdev->dev);
+
+- if (bcm47xx_wdt_hw_stop() < 0)
+- return -ENODEV;
++ if (!wdt)
++ return -ENXIO;
+
+- setup_timer(&wdt_timer, bcm47xx_timer_tick, 0L);
++ setup_timer(&wdt->soft_timer, bcm47xx_timer_tick,
++ (long unsigned int)wdt);
+
+- if (bcm47xx_wdt_settimeout(wdt_time)) {
+- bcm47xx_wdt_settimeout(WDT_DEFAULT_TIME);
+- pr_info("wdt_time value must be 0 < wdt_time < %d, using %d\n",
+- (WDT_MAX_TIME + 1), wdt_time);
+- }
+- watchdog_set_nowayout(&bcm47xx_wdt_wdd, nowayout);
++ wdt->wdd.ops = &bcm47xx_wdt_ops;
++ wdt->wdd.info = &bcm47xx_wdt_info;
++ wdt->wdd.timeout = WDT_DEFAULT_TIME;
++ ret = wdt->wdd.ops->set_timeout(&wdt->wdd, timeout);
++ if (ret)
++ goto err_timer;
++ watchdog_set_nowayout(&wdt->wdd, nowayout);
++
++ wdt->notifier.notifier_call = &bcm47xx_wdt_notify_sys;
+
+- ret = register_reboot_notifier(&bcm47xx_wdt_notifier);
++ ret = register_reboot_notifier(&wdt->notifier);
+ if (ret)
+- return ret;
++ goto err_timer;
+
+- ret = watchdog_register_device(&bcm47xx_wdt_wdd);
+- if (ret) {
+- unregister_reboot_notifier(&bcm47xx_wdt_notifier);
+- return ret;
+- }
++ ret = watchdog_register_device(&wdt->wdd);
++ if (ret)
++ goto err_notifier;
+
+ pr_info("BCM47xx Watchdog Timer enabled (%d seconds%s)\n",
+ wdt_time, nowayout ? ", nowayout" : "");
+ return 0;
++
++err_notifier:
++ unregister_reboot_notifier(&wdt->notifier);
++err_timer:
++ del_timer_sync(&wdt->soft_timer);
++
++ return ret;
+ }
+
+-static void __exit bcm47xx_wdt_exit(void)
++static int bcm47xx_wdt_remove(struct platform_device *pdev)
+ {
+- watchdog_unregister_device(&bcm47xx_wdt_wdd);
++ struct bcm47xx_wdt *wdt = dev_get_platdata(&pdev->dev);
++
++ if (!wdt)
++ return -ENXIO;
++
++ watchdog_unregister_device(&wdt->wdd);
++ unregister_reboot_notifier(&wdt->notifier);
+
+- unregister_reboot_notifier(&bcm47xx_wdt_notifier);
++ return 0;
+ }
+
+-module_init(bcm47xx_wdt_init);
+-module_exit(bcm47xx_wdt_exit);
++static struct platform_driver bcm47xx_wdt_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "bcm47xx-wdt",
++ },
++ .probe = bcm47xx_wdt_probe,
++ .remove = bcm47xx_wdt_remove,
++};
++
++module_platform_driver(bcm47xx_wdt_driver);
+
+ MODULE_AUTHOR("Aleksandar Radovanovic");
++MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
+ MODULE_DESCRIPTION("Watchdog driver for Broadcom BCM47xx");
+ MODULE_LICENSE("GPL");
+--- a/include/linux/bcm47xx_wdt.h
++++ b/include/linux/bcm47xx_wdt.h
+@@ -1,7 +1,10 @@
+ #ifndef LINUX_BCM47XX_WDT_H_
+ #define LINUX_BCM47XX_WDT_H_
+
++#include <linux/notifier.h>
++#include <linux/timer.h>
+ #include <linux/types.h>
++#include <linux/watchdog.h>
+
+
+ struct bcm47xx_wdt {
+@@ -10,6 +13,12 @@ struct bcm47xx_wdt {
+ u32 max_timer_ms;
+
+ void *driver_data;
++
++ struct watchdog_device wdd;
++ struct notifier_block notifier;
++
++ struct timer_list soft_timer;
++ atomic_t soft_ticks;
+ };
+
+ static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
--- /dev/null
+--- a/drivers/watchdog/bcm47xx_wdt.c
++++ b/drivers/watchdog/bcm47xx_wdt.c
+@@ -30,7 +30,7 @@
+ #define DRV_NAME "bcm47xx_wdt"
+
+ #define WDT_DEFAULT_TIME 30 /* seconds */
+-#define WDT_MAX_TIME 255 /* seconds */
++#define WDT_SOFTTIMER_MAX 255 /* seconds */
+
+ static int wdt_time = WDT_DEFAULT_TIME;
+ static bool nowayout = WATCHDOG_NOWAYOUT;
+@@ -49,7 +49,7 @@ static inline struct bcm47xx_wdt *bcm47x
+ return container_of(wdd, struct bcm47xx_wdt, wdd);
+ }
+
+-static void bcm47xx_timer_tick(unsigned long data)
++static void bcm47xx_wdt_soft_timer_tick(unsigned long data)
+ {
+ struct bcm47xx_wdt *wdt = (struct bcm47xx_wdt *)data;
+ u32 next_tick = min(wdt->wdd.timeout * 1000, wdt->max_timer_ms);
+@@ -62,7 +62,7 @@ static void bcm47xx_timer_tick(unsigned
+ }
+ }
+
+-static int bcm47xx_wdt_keepalive(struct watchdog_device *wdd)
++static int bcm47xx_wdt_soft_keepalive(struct watchdog_device *wdd)
+ {
+ struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
+
+@@ -71,17 +71,17 @@ static int bcm47xx_wdt_keepalive(struct
+ return 0;
+ }
+
+-static int bcm47xx_wdt_start(struct watchdog_device *wdd)
++static int bcm47xx_wdt_soft_start(struct watchdog_device *wdd)
+ {
+ struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
+
+- bcm47xx_wdt_keepalive(wdd);
+- bcm47xx_timer_tick((unsigned long)wdt);
++ bcm47xx_wdt_soft_keepalive(wdd);
++ bcm47xx_wdt_soft_timer_tick((unsigned long)wdt);
+
+ return 0;
+ }
+
+-static int bcm47xx_wdt_stop(struct watchdog_device *wdd)
++static int bcm47xx_wdt_soft_stop(struct watchdog_device *wdd)
+ {
+ struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
+
+@@ -91,12 +91,12 @@ static int bcm47xx_wdt_stop(struct watch
+ return 0;
+ }
+
+-static int bcm47xx_wdt_set_timeout(struct watchdog_device *wdd,
+- unsigned int new_time)
++static int bcm47xx_wdt_soft_set_timeout(struct watchdog_device *wdd,
++ unsigned int new_time)
+ {
+- if (new_time < 1 || new_time > WDT_MAX_TIME) {
++ if (new_time < 1 || new_time > WDT_SOFTTIMER_MAX) {
+ pr_warn("timeout value must be 1<=x<=%d, using %d\n",
+- WDT_MAX_TIME, new_time);
++ WDT_SOFTTIMER_MAX, new_time);
+ return -EINVAL;
+ }
+
+@@ -122,12 +122,12 @@ static int bcm47xx_wdt_notify_sys(struct
+ return NOTIFY_DONE;
+ }
+
+-static struct watchdog_ops bcm47xx_wdt_ops = {
++static struct watchdog_ops bcm47xx_wdt_soft_ops = {
+ .owner = THIS_MODULE,
+- .start = bcm47xx_wdt_start,
+- .stop = bcm47xx_wdt_stop,
+- .ping = bcm47xx_wdt_keepalive,
+- .set_timeout = bcm47xx_wdt_set_timeout,
++ .start = bcm47xx_wdt_soft_start,
++ .stop = bcm47xx_wdt_soft_stop,
++ .ping = bcm47xx_wdt_soft_keepalive,
++ .set_timeout = bcm47xx_wdt_soft_set_timeout,
+ };
+
+ static int bcm47xx_wdt_probe(struct platform_device *pdev)
+@@ -138,10 +138,10 @@ static int bcm47xx_wdt_probe(struct plat
+ if (!wdt)
+ return -ENXIO;
+
+- setup_timer(&wdt->soft_timer, bcm47xx_timer_tick,
++ setup_timer(&wdt->soft_timer, bcm47xx_wdt_soft_timer_tick,
+ (long unsigned int)wdt);
+
+- wdt->wdd.ops = &bcm47xx_wdt_ops;
++ wdt->wdd.ops = &bcm47xx_wdt_soft_ops;
+ wdt->wdd.info = &bcm47xx_wdt_info;
+ wdt->wdd.timeout = WDT_DEFAULT_TIME;
+ ret = wdt->wdd.ops->set_timeout(&wdt->wdd, timeout);
--- /dev/null
+--- a/drivers/watchdog/bcm47xx_wdt.c
++++ b/drivers/watchdog/bcm47xx_wdt.c
+@@ -32,11 +32,11 @@
+ #define WDT_DEFAULT_TIME 30 /* seconds */
+ #define WDT_SOFTTIMER_MAX 255 /* seconds */
+
+-static int wdt_time = WDT_DEFAULT_TIME;
++static int timeout = WDT_DEFAULT_TIME;
+ static bool nowayout = WATCHDOG_NOWAYOUT;
+
+-module_param(wdt_time, int, 0);
+-MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default="
++module_param(timeout, int, 0);
++MODULE_PARM_DESC(timeout, "Watchdog time in seconds. (default="
+ __MODULE_STRING(WDT_DEFAULT_TIME) ")");
+
+ module_param(nowayout, bool, 0);
+@@ -160,7 +160,7 @@ static int bcm47xx_wdt_probe(struct plat
+ goto err_notifier;
+
+ pr_info("BCM47xx Watchdog Timer enabled (%d seconds%s)\n",
+- wdt_time, nowayout ? ", nowayout" : "");
++ timeout, nowayout ? ", nowayout" : "");
+ return 0;
+
+ err_notifier:
--- /dev/null
+--- a/drivers/watchdog/bcm47xx_wdt.c
++++ b/drivers/watchdog/bcm47xx_wdt.c
+@@ -31,6 +31,7 @@
+
+ #define WDT_DEFAULT_TIME 30 /* seconds */
+ #define WDT_SOFTTIMER_MAX 255 /* seconds */
++#define WDT_SOFTTIMER_THRESHOLD 60 /* seconds */
+
+ static int timeout = WDT_DEFAULT_TIME;
+ static bool nowayout = WATCHDOG_NOWAYOUT;
+@@ -49,6 +50,53 @@ static inline struct bcm47xx_wdt *bcm47x
+ return container_of(wdd, struct bcm47xx_wdt, wdd);
+ }
+
++static int bcm47xx_wdt_hard_keepalive(struct watchdog_device *wdd)
++{
++ struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
++
++ wdt->timer_set_ms(wdt, wdd->timeout * 1000);
++
++ return 0;
++}
++
++static int bcm47xx_wdt_hard_start(struct watchdog_device *wdd)
++{
++ return 0;
++}
++
++static int bcm47xx_wdt_hard_stop(struct watchdog_device *wdd)
++{
++ struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
++
++ wdt->timer_set(wdt, 0);
++
++ return 0;
++}
++
++static int bcm47xx_wdt_hard_set_timeout(struct watchdog_device *wdd,
++ unsigned int new_time)
++{
++ struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
++ u32 max_timer = wdt->max_timer_ms;
++
++ if (new_time < 1 || new_time > max_timer / 1000) {
++ pr_warn("timeout value must be 1<=x<=%d, using %d\n",
++ max_timer / 1000, new_time);
++ return -EINVAL;
++ }
++
++ wdd->timeout = new_time;
++ return 0;
++}
++
++static struct watchdog_ops bcm47xx_wdt_hard_ops = {
++ .owner = THIS_MODULE,
++ .start = bcm47xx_wdt_hard_start,
++ .stop = bcm47xx_wdt_hard_stop,
++ .ping = bcm47xx_wdt_hard_keepalive,
++ .set_timeout = bcm47xx_wdt_hard_set_timeout,
++};
++
+ static void bcm47xx_wdt_soft_timer_tick(unsigned long data)
+ {
+ struct bcm47xx_wdt *wdt = (struct bcm47xx_wdt *)data;
+@@ -133,15 +181,22 @@ static struct watchdog_ops bcm47xx_wdt_s
+ static int bcm47xx_wdt_probe(struct platform_device *pdev)
+ {
+ int ret;
++ bool soft;
+ struct bcm47xx_wdt *wdt = dev_get_platdata(&pdev->dev);
+
+ if (!wdt)
+ return -ENXIO;
+
+- setup_timer(&wdt->soft_timer, bcm47xx_wdt_soft_timer_tick,
+- (long unsigned int)wdt);
++ soft = wdt->max_timer_ms < WDT_SOFTTIMER_THRESHOLD * 1000;
++
++ if (soft) {
++ wdt->wdd.ops = &bcm47xx_wdt_soft_ops;
++ setup_timer(&wdt->soft_timer, bcm47xx_wdt_soft_timer_tick,
++ (long unsigned int)wdt);
++ } else {
++ wdt->wdd.ops = &bcm47xx_wdt_hard_ops;
++ }
+
+- wdt->wdd.ops = &bcm47xx_wdt_soft_ops;
+ wdt->wdd.info = &bcm47xx_wdt_info;
+ wdt->wdd.timeout = WDT_DEFAULT_TIME;
+ ret = wdt->wdd.ops->set_timeout(&wdt->wdd, timeout);
+@@ -159,14 +214,16 @@ static int bcm47xx_wdt_probe(struct plat
+ if (ret)
+ goto err_notifier;
+
+- pr_info("BCM47xx Watchdog Timer enabled (%d seconds%s)\n",
+- timeout, nowayout ? ", nowayout" : "");
++ dev_info(&pdev->dev, "BCM47xx Watchdog Timer enabled (%d seconds%s%s)\n",
++ timeout, nowayout ? ", nowayout" : "",
++ soft ? ", Software Timer" : "");
+ return 0;
+
+ err_notifier:
+ unregister_reboot_notifier(&wdt->notifier);
+ err_timer:
+- del_timer_sync(&wdt->soft_timer);
++ if (soft)
++ del_timer_sync(&wdt->soft_timer);
+
+ return ret;
+ }
--- /dev/null
+--- a/include/linux/ide.h
++++ b/include/linux/ide.h
+@@ -195,7 +195,11 @@ static inline void ide_std_init_ports(st
+ hw->io_ports.ctl_addr = ctl_addr;
+ }
+
++#if defined CONFIG_BCM47XX
++# define MAX_HWIFS 2
++#else
+ #define MAX_HWIFS 10
++#endif
+
+ /*
+ * Now for the data we need to maintain per-drive: ide_drive_t
--- /dev/null
+--- a/drivers/net/ethernet/broadcom/tg3.c
++++ b/drivers/net/ethernet/broadcom/tg3.c
+@@ -44,6 +44,7 @@
+ #include <linux/prefetch.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/firmware.h>
++#include <linux/ssb/ssb_driver_gige.h>
+ #include <linux/hwmon.h>
+ #include <linux/hwmon-sysfs.h>
+
+@@ -263,6 +264,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_t
+ TG3_DRV_DATA_FLAG_5705_10_100},
+ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
+ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
+ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
+ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
+ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
+@@ -570,7 +572,9 @@ static void _tw32_flush(struct tg3 *tp,
+ static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
+ {
+ tp->write32_mbox(tp, off, val);
+- if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
++ if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
++ (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
++ !tg3_flag(tp, ICH_WORKAROUND)))
+ tp->read32_mbox(tp, off);
+ }
+
+@@ -580,7 +584,8 @@ static void tg3_write32_tx_mbox(struct t
+ writel(val, mbox);
+ if (tg3_flag(tp, TXD_MBOX_HWBUG))
+ writel(val, mbox);
+- if (tg3_flag(tp, MBOX_WRITE_REORDER))
++ if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
++ tg3_flag(tp, FLUSH_POSTED_WRITES))
+ readl(mbox);
+ }
+
+@@ -1088,7 +1093,8 @@ static void tg3_switch_clocks(struct tg3
+
+ #define PHY_BUSY_LOOPS 5000
+
+-static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
++static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
++ u32 *val)
+ {
+ u32 frame_val;
+ unsigned int loops;
+@@ -1104,7 +1110,7 @@ static int tg3_readphy(struct tg3 *tp, i
+
+ *val = 0x0;
+
+- frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
++ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
+ MI_COM_PHY_ADDR_MASK);
+ frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
+ MI_COM_REG_ADDR_MASK);
+@@ -1141,7 +1147,13 @@ static int tg3_readphy(struct tg3 *tp, i
+ return ret;
+ }
+
+-static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
++static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
++{
++ return __tg3_readphy(tp, tp->phy_addr, reg, val);
++}
++
++static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
++ u32 val)
+ {
+ u32 frame_val;
+ unsigned int loops;
+@@ -1159,7 +1171,7 @@ static int tg3_writephy(struct tg3 *tp,
+
+ tg3_ape_lock(tp, tp->phy_ape_lock);
+
+- frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
++ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
+ MI_COM_PHY_ADDR_MASK);
+ frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
+ MI_COM_REG_ADDR_MASK);
+@@ -1194,6 +1206,11 @@ static int tg3_writephy(struct tg3 *tp,
+ return ret;
+ }
+
++static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
++{
++ return __tg3_writephy(tp, tp->phy_addr, reg, val);
++}
++
+ static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
+ {
+ int err;
+@@ -1778,6 +1795,11 @@ static int tg3_poll_fw(struct tg3 *tp)
+ int i;
+ u32 val;
+
++ if (tg3_flag(tp, IS_SSB_CORE)) {
++ /* We don't use firmware. */
++ return 0;
++ }
++
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+ /* Wait up to 20ms for init done. */
+ for (i = 0; i < 200; i++) {
+@@ -3447,6 +3469,13 @@ static int tg3_halt_cpu(struct tg3 *tp,
+ tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
+ udelay(10);
+ } else {
++ /*
++ * There is only an Rx CPU for the 5750 derivative in the
++ * BCM4785.
++ */
++ if (tg3_flag(tp, IS_SSB_CORE))
++ return 0;
++
+ for (i = 0; i < 10000; i++) {
+ tw32(offset + CPU_STATE, 0xffffffff);
+ tw32(offset + CPU_MODE, CPU_MODE_HALT);
+@@ -3914,8 +3943,9 @@ static int tg3_power_down_prepare(struct
+ tg3_frob_aux_power(tp, true);
+
+ /* Workaround for unstable PLL clock */
+- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
+- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
++ if ((!tg3_flag(tp, IS_SSB_CORE)) &&
++ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
++ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
+ u32 val = tr32(0x7d00);
+
+ val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
+@@ -4435,6 +4465,15 @@ relink:
+ if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
+ tg3_phy_copper_begin(tp);
+
++ if (tg3_flag(tp, ROBOSWITCH)) {
++ current_link_up = 1;
++ /* FIXME: when BCM5325 switch is used use 100 MBit/s */
++ current_speed = SPEED_1000;
++ current_duplex = DUPLEX_FULL;
++ tp->link_config.active_speed = current_speed;
++ tp->link_config.active_duplex = current_duplex;
++ }
++
+ tg3_readphy(tp, MII_BMSR, &bmsr);
+ if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
+ (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
+@@ -4453,6 +4492,26 @@ relink:
+ else
+ tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
+
++ /* In order for the 5750 core in BCM4785 chip to work properly
++ * in RGMII mode, the Led Control Register must be set up.
++ */
++ if (tg3_flag(tp, RGMII_MODE)) {
++ u32 led_ctrl = tr32(MAC_LED_CTRL);
++ led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
++
++ if (tp->link_config.active_speed == SPEED_10)
++ led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
++ else if (tp->link_config.active_speed == SPEED_100)
++ led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
++ LED_CTRL_100MBPS_ON);
++ else if (tp->link_config.active_speed == SPEED_1000)
++ led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
++ LED_CTRL_1000MBPS_ON);
++
++ tw32(MAC_LED_CTRL, led_ctrl);
++ udelay(40);
++ }
++
+ tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
+ if (tp->link_config.active_duplex == DUPLEX_HALF)
+ tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
+@@ -8431,6 +8490,16 @@ static int tg3_chip_reset(struct tg3 *tp
+ tw32(0x5000, 0x400);
+ }
+
++ if (tg3_flag(tp, IS_SSB_CORE)) {
++ /*
++ * BCM4785: In order to avoid repercussions from using
++ * potentially defective internal ROM, stop the Rx RISC CPU,
++ * which is not required.
++ */
++ tg3_stop_fw(tp);
++ tg3_halt_cpu(tp, RX_CPU_BASE);
++ }
++
+ tw32(GRC_MODE, tp->grc_mode);
+
+ if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
+@@ -10064,6 +10133,11 @@ static void tg3_timer(unsigned long __op
+ tg3_flag(tp, 57765_CLASS))
+ tg3_chk_missed_msi(tp);
+
++ if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
++ /* BCM4785: Flush posted writes from GbE to host memory. */
++ tr32(HOSTCC_MODE);
++ }
++
+ if (!tg3_flag(tp, TAGGED_STATUS)) {
+ /* All of this garbage is because when using non-tagged
+ * IRQ status the mailbox/status_block protocol the chip
+@@ -12937,7 +13011,8 @@ static int tg3_ioctl(struct net_device *
+ return -EAGAIN;
+
+ spin_lock_bh(&tp->lock);
+- err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
++ err = __tg3_readphy(tp, data->phy_id & 0x1f,
++ data->reg_num & 0x1f, &mii_regval);
+ spin_unlock_bh(&tp->lock);
+
+ data->val_out = mii_regval;
+@@ -12953,7 +13028,8 @@ static int tg3_ioctl(struct net_device *
+ return -EAGAIN;
+
+ spin_lock_bh(&tp->lock);
+- err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
++ err = __tg3_writephy(tp, data->phy_id & 0x1f,
++ data->reg_num & 0x1f, data->val_in);
+ spin_unlock_bh(&tp->lock);
+
+ return err;
+@@ -13806,6 +13882,14 @@ static void tg3_get_5720_nvram_info(stru
+ /* Chips other than 5700/5701 use the NVRAM for fetching info. */
+ static void tg3_nvram_init(struct tg3 *tp)
+ {
++ if (tg3_flag(tp, IS_SSB_CORE)) {
++ /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
++ tg3_flag_clear(tp, NVRAM);
++ tg3_flag_clear(tp, NVRAM_BUFFERED);
++ tg3_flag_set(tp, NO_NVRAM);
++ return;
++ }
++
+ tw32_f(GRC_EEPROM_ADDR,
+ (EEPROM_ADDR_FSM_RESET |
+ (EEPROM_DEFAULT_CLOCK_PERIOD <<
+@@ -14298,10 +14382,19 @@ static int tg3_phy_probe(struct tg3 *tp)
+ * subsys device table.
+ */
+ p = tg3_lookup_by_subsys(tp);
+- if (!p)
++ if (p) {
++ tp->phy_id = p->phy_id;
++ } else if (!tg3_flag(tp, IS_SSB_CORE)) {
++ /* For now we saw the IDs 0xbc050cd0,
++ * 0xbc050f80 and 0xbc050c30 on devices
++ * connected to an BCM4785 and there are
++ * probably more. Just assume that the phy is
++ * supported when it is connected to a SSB core
++ * for now.
++ */
+ return -ENODEV;
++ }
+
+- tp->phy_id = p->phy_id;
+ if (!tp->phy_id ||
+ tp->phy_id == TG3_PHY_ID_BCM8002)
+ tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
+@@ -15346,6 +15439,11 @@ static int tg3_get_invariants(struct tg3
+ }
+ }
+
++ if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
++ tp->write32_tx_mbox = tg3_write_flush_reg32;
++ tp->write32_rx_mbox = tg3_write_flush_reg32;
++ }
++
+ /* Get eeprom hw config before calling tg3_set_power_state().
+ * In particular, the TG3_FLAG_IS_NIC flag must be
+ * determined before calling tg3_set_power_state() so that
+@@ -15679,12 +15777,19 @@ static int tg3_get_device_address(struct
+ struct net_device *dev = tp->dev;
+ u32 hi, lo, mac_offset;
+ int addr_ok = 0;
++ int err;
+
+ #ifdef CONFIG_SPARC
+ if (!tg3_get_macaddr_sparc(tp))
+ return 0;
+ #endif
+
++ if (tg3_flag(tp, IS_SSB_CORE)) {
++ err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
++ if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
++ return 0;
++ }
++
+ mac_offset = 0x7c;
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
+ tg3_flag(tp, 5780_CLASS)) {
+@@ -16045,6 +16150,8 @@ static int tg3_test_dma(struct tg3 *tp)
+ tp->dma_rwctrl |= 0x001b000f;
+ }
+ }
++ if (tg3_flag(tp, ONE_DMA_AT_ONCE))
++ tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
+
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
+@@ -16389,6 +16496,18 @@ static int tg3_init_one(struct pci_dev *
+ else
+ tp->msg_enable = TG3_DEF_MSG_ENABLE;
+
++ if (pdev_is_ssb_gige_core(pdev)) {
++ tg3_flag_set(tp, IS_SSB_CORE);
++ if (ssb_gige_must_flush_posted_writes(pdev))
++ tg3_flag_set(tp, FLUSH_POSTED_WRITES);
++ if (ssb_gige_one_dma_at_once(pdev))
++ tg3_flag_set(tp, ONE_DMA_AT_ONCE);
++ if (ssb_gige_have_roboswitch(pdev))
++ tg3_flag_set(tp, ROBOSWITCH);
++ if (ssb_gige_is_rgmii(pdev))
++ tg3_flag_set(tp, RGMII_MODE);
++ }
++
+ /* The word/byte swap controls here control register access byte
+ * swapping. DMA data byte swapping is controlled in the GRC_MODE
+ * setting below.
+--- a/drivers/net/ethernet/broadcom/tg3.h
++++ b/drivers/net/ethernet/broadcom/tg3.h
+@@ -3030,6 +3030,11 @@ enum TG3_FLAGS {
+ TG3_FLAG_57765_PLUS,
+ TG3_FLAG_57765_CLASS,
+ TG3_FLAG_5717_PLUS,
++ TG3_FLAG_IS_SSB_CORE,
++ TG3_FLAG_FLUSH_POSTED_WRITES,
++ TG3_FLAG_ROBOSWITCH,
++ TG3_FLAG_ONE_DMA_AT_ONCE,
++ TG3_FLAG_RGMII_MODE,
+
+ /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
+ TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2127,6 +2127,7 @@
+ #define PCI_DEVICE_ID_TIGON3_5754M 0x1672
+ #define PCI_DEVICE_ID_TIGON3_5755M 0x1673
+ #define PCI_DEVICE_ID_TIGON3_5756 0x1674
++#define PCI_DEVICE_ID_TIGON3_5750 0x1676
+ #define PCI_DEVICE_ID_TIGON3_5751 0x1677
+ #define PCI_DEVICE_ID_TIGON3_5715 0x1678
+ #define PCI_DEVICE_ID_TIGON3_5715S 0x1679
+--- a/include/linux/ssb/ssb_driver_gige.h
++++ b/include/linux/ssb/ssb_driver_gige.h
+@@ -97,21 +97,16 @@ static inline bool ssb_gige_must_flush_p
+ return 0;
+ }
+
+-#ifdef CONFIG_BCM47XX
+-#include <bcm47xx_nvram.h>
+ /* Get the device MAC address */
+-static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
+-{
+- char buf[20];
+- if (bcm47xx_nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
+- return;
+- bcm47xx_nvram_parse_macaddr(buf, macaddr);
+-}
+-#else
+-static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
++static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
+ {
++ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
++ if (!dev)
++ return -ENODEV;
++
++ memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
++ return 0;
+ }
+-#endif
+
+ extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
+ struct pci_dev *pdev);
+@@ -175,6 +170,10 @@ static inline bool ssb_gige_must_flush_p
+ {
+ return 0;
+ }
++static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
++{
++ return -ENODEV;
++}
+
+ #endif /* CONFIG_SSB_DRIVER_GIGE */
+ #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
--- /dev/null
+commit fa0879e37b59e8e3f130a30a9e6fa515717c5bdd
+Author: Stefan Hajnoczi <stefanha@gmail.com>
+Date: Mon Jan 21 01:17:22 2013 +0000
+
+ net: split eth_mac_addr for better error handling
+
+ When we set mac address, software mac address in system and hardware mac
+ address all need to be updated. Current eth_mac_addr() doesn't allow
+ callers to implement error handling nicely.
+
+ This patch split eth_mac_addr() to prepare part and real commit part,
+ then we can prepare first, and try to change hardware address, then do
+ the real commit if hardware address is set successfully.
+
+ Signed-off-by: Stefan Hajnoczi <stefanha@gmail.com>
+ Signed-off-by: Amos Kong <akong@redhat.com>
+ Signed-off-by: David S. Miller <davem@davemloft.net>
+
+--- a/include/linux/etherdevice.h
++++ b/include/linux/etherdevice.h
+@@ -40,6 +40,8 @@ extern int eth_header_cache(const struct
+ extern void eth_header_cache_update(struct hh_cache *hh,
+ const struct net_device *dev,
+ const unsigned char *haddr);
++extern int eth_prepare_mac_addr_change(struct net_device *dev, void *p);
++extern void eth_commit_mac_addr_change(struct net_device *dev, void *p);
+ extern int eth_mac_addr(struct net_device *dev, void *p);
+ extern int eth_change_mtu(struct net_device *dev, int new_mtu);
+ extern int eth_validate_addr(struct net_device *dev);
+--- a/net/ethernet/eth.c
++++ b/net/ethernet/eth.c
+@@ -278,16 +278,11 @@ void eth_header_cache_update(struct hh_c
+ EXPORT_SYMBOL(eth_header_cache_update);
+
+ /**
+- * eth_mac_addr - set new Ethernet hardware address
++ * eth_prepare_mac_addr_change - prepare for mac change
+ * @dev: network device
+ * @p: socket address
+- *
+- * Change hardware address of device.
+- *
+- * This doesn't change hardware matching, so needs to be overridden
+- * for most real devices.
+ */
+-int eth_mac_addr(struct net_device *dev, void *p)
++int eth_prepare_mac_addr_change(struct net_device *dev, void *p)
+ {
+ struct sockaddr *addr = p;
+
+@@ -295,9 +290,43 @@ int eth_mac_addr(struct net_device *dev,
+ return -EBUSY;
+ if (!is_valid_ether_addr(addr->sa_data))
+ return -EADDRNOTAVAIL;
++ return 0;
++}
++EXPORT_SYMBOL(eth_prepare_mac_addr_change);
++
++/**
++ * eth_commit_mac_addr_change - commit mac change
++ * @dev: network device
++ * @p: socket address
++ */
++void eth_commit_mac_addr_change(struct net_device *dev, void *p)
++{
++ struct sockaddr *addr = p;
++
+ memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
+ /* if device marked as NET_ADDR_RANDOM, reset it */
+ dev->addr_assign_type &= ~NET_ADDR_RANDOM;
++}
++EXPORT_SYMBOL(eth_commit_mac_addr_change);
++
++/**
++ * eth_mac_addr - set new Ethernet hardware address
++ * @dev: network device
++ * @p: socket address
++ *
++ * Change hardware address of device.
++ *
++ * This doesn't change hardware matching, so needs to be overridden
++ * for most real devices.
++ */
++int eth_mac_addr(struct net_device *dev, void *p)
++{
++ int ret;
++
++ ret = eth_prepare_mac_addr_change(dev, p);
++ if (ret < 0)
++ return ret;
++ eth_commit_mac_addr_change(dev, p);
+ return 0;
+ }
+ EXPORT_SYMBOL(eth_mac_addr);
--- /dev/null
+From dd4544f05469aaaeee891d7dc54d66430344321e Mon Sep 17 00:00:00 2001
+From: =?utf8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Tue, 8 Jan 2013 20:06:23 +0000
+Subject: [PATCH] bgmac: driver for GBit MAC core on BCMA bus
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf8
+Content-Transfer-Encoding: 8bit
+
+BCMA is a Broadcom specific bus with devices AKA cores. All recent BCMA
+based SoCs have gigabit ethernet provided by the GBit MAC core. This
+patch adds driver for such a cores registering itself as a netdev. It
+has been tested on a BCM4706 and BCM4718 chipsets.
+
+In the kernel tree there is already b44 driver which has some common
+things with bgmac, however there are many differences that has led to
+the decision or writing a new driver:
+1) GBit MAC cores appear on BCMA bus (not SSB as in case of b44)
+2) There is 64bit DMA engine which differs from 32bit one
+3) There is no CAM (Content Addressable Memory) in GBit MAC
+4) We have 4 TX queues on GBit MAC devices (instead of 1)
+5) Many registers have different addresses/values
+6) RX header flags are also different
+
+The driver in it's state is functional how, however there is of course
+place for improvements:
+1) Supporting more net_device_ops
+2) SUpporting more ethtool_ops
+3) Unaligned addressing in DMA
+4) Writing separated PHY driver
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/bcma/driver_chipcommon_pmu.c | 3 +-
+ drivers/net/ethernet/broadcom/Kconfig | 9 +
+ drivers/net/ethernet/broadcom/Makefile | 1 +
+ drivers/net/ethernet/broadcom/bgmac.c | 1422 +++++++++++++++++++++++++++
+ drivers/net/ethernet/broadcom/bgmac.h | 456 +++++++++
+ include/linux/bcma/bcma_driver_chipcommon.h | 2 +
+ 6 files changed, 1892 insertions(+), 1 deletions(-)
+ create mode 100644 drivers/net/ethernet/broadcom/bgmac.c
+ create mode 100644 drivers/net/ethernet/broadcom/bgmac.h
+
+--- a/drivers/bcma/driver_chipcommon_pmu.c
++++ b/drivers/bcma/driver_chipcommon_pmu.c
+@@ -264,7 +264,7 @@ static u32 bcma_pmu_pll_clock_bcm4706(st
+ }
+
+ /* query bus clock frequency for PMU-enabled chipcommon */
+-static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
++u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
+ {
+ struct bcma_bus *bus = cc->core->bus;
+
+@@ -293,6 +293,7 @@ static u32 bcma_pmu_get_bus_clock(struct
+ }
+ return BCMA_CC_PMU_HT_CLOCK;
+ }
++EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
+
+ /* query cpu clock frequency for PMU-enabled chipcommon */
+ u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
+--- a/drivers/net/ethernet/broadcom/Kconfig
++++ b/drivers/net/ethernet/broadcom/Kconfig
+@@ -121,4 +121,13 @@ config BNX2X
+ To compile this driver as a module, choose M here: the module
+ will be called bnx2x. This is recommended.
+
++config BGMAC
++ tristate "BCMA bus GBit core support"
++ depends on BCMA_HOST_SOC && HAS_DMA
++ ---help---
++ This driver supports GBit MAC and BCM4706 GBit MAC cores on BCMA bus.
++ They can be found on BCM47xx SoCs and provide gigabit ethernet.
++ In case of using this driver on BCM4706 it's also requires to enable
++ BCMA_DRIVER_GMAC_CMN to make it work.
++
+ endif # NET_VENDOR_BROADCOM
+--- a/drivers/net/ethernet/broadcom/Makefile
++++ b/drivers/net/ethernet/broadcom/Makefile
+@@ -9,3 +9,4 @@ obj-$(CONFIG_CNIC) += cnic.o
+ obj-$(CONFIG_BNX2X) += bnx2x/
+ obj-$(CONFIG_SB1250_MAC) += sb1250-mac.o
+ obj-$(CONFIG_TIGON3) += tg3.o
++obj-$(CONFIG_BGMAC) += bgmac.o
+--- /dev/null
++++ b/drivers/net/ethernet/broadcom/bgmac.c
+@@ -0,0 +1,1422 @@
++/*
++ * Driver for (BCM4706)? GBit MAC core on BCMA bus.
++ *
++ * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bgmac.h"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/etherdevice.h>
++#include <linux/mii.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <bcm47xx_nvram.h>
++
++static const struct bcma_device_id bgmac_bcma_tbl[] = {
++ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
++ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
++ BCMA_CORETABLE_END
++};
++MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
++
++static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
++ u32 value, int timeout)
++{
++ u32 val;
++ int i;
++
++ for (i = 0; i < timeout / 10; i++) {
++ val = bcma_read32(core, reg);
++ if ((val & mask) == value)
++ return true;
++ udelay(10);
++ }
++ pr_err("Timeout waiting for reg 0x%X\n", reg);
++ return false;
++}
++
++/**************************************************
++ * DMA
++ **************************************************/
++
++static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
++{
++ u32 val;
++ int i;
++
++ if (!ring->mmio_base)
++ return;
++
++ /* Suspend DMA TX ring first.
++ * bgmac_wait_value doesn't support waiting for any of few values, so
++ * implement whole loop here.
++ */
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
++ BGMAC_DMA_TX_SUSPEND);
++ for (i = 0; i < 10000 / 10; i++) {
++ val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
++ val &= BGMAC_DMA_TX_STAT;
++ if (val == BGMAC_DMA_TX_STAT_DISABLED ||
++ val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
++ val == BGMAC_DMA_TX_STAT_STOPPED) {
++ i = 0;
++ break;
++ }
++ udelay(10);
++ }
++ if (i)
++ bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
++ ring->mmio_base, val);
++
++ /* Remove SUSPEND bit */
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
++ if (!bgmac_wait_value(bgmac->core,
++ ring->mmio_base + BGMAC_DMA_TX_STATUS,
++ BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
++ 10000)) {
++ bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
++ ring->mmio_base);
++ udelay(300);
++ val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
++ if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
++ bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
++ ring->mmio_base);
++ }
++}
++
++static void bgmac_dma_tx_enable(struct bgmac *bgmac,
++ struct bgmac_dma_ring *ring)
++{
++ u32 ctl;
++
++ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
++ ctl |= BGMAC_DMA_TX_ENABLE;
++ ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
++}
++
++static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
++ struct bgmac_dma_ring *ring,
++ struct sk_buff *skb)
++{
++ struct device *dma_dev = bgmac->core->dma_dev;
++ struct net_device *net_dev = bgmac->net_dev;
++ struct bgmac_dma_desc *dma_desc;
++ struct bgmac_slot_info *slot;
++ u32 ctl0, ctl1;
++ int free_slots;
++
++ if (skb->len > BGMAC_DESC_CTL1_LEN) {
++ bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
++ goto err_stop_drop;
++ }
++
++ if (ring->start <= ring->end)
++ free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS;
++ else
++ free_slots = ring->start - ring->end;
++ if (free_slots == 1) {
++ bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
++ netif_stop_queue(net_dev);
++ return NETDEV_TX_BUSY;
++ }
++
++ slot = &ring->slots[ring->end];
++ slot->skb = skb;
++ slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len,
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(dma_dev, slot->dma_addr)) {
++ bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
++ ring->mmio_base);
++ goto err_stop_drop;
++ }
++
++ ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF;
++ if (ring->end == ring->num_slots - 1)
++ ctl0 |= BGMAC_DESC_CTL0_EOT;
++ ctl1 = skb->len & BGMAC_DESC_CTL1_LEN;
++
++ dma_desc = ring->cpu_base;
++ dma_desc += ring->end;
++ dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
++ dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
++ dma_desc->ctl0 = cpu_to_le32(ctl0);
++ dma_desc->ctl1 = cpu_to_le32(ctl1);
++
++ wmb();
++
++ /* Increase ring->end to point empty slot. We tell hardware the first
++ * slot it should *not* read.
++ */
++ if (++ring->end >= BGMAC_TX_RING_SLOTS)
++ ring->end = 0;
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
++ ring->end * sizeof(struct bgmac_dma_desc));
++
++ /* Always keep one slot free to allow detecting bugged calls. */
++ if (--free_slots == 1)
++ netif_stop_queue(net_dev);
++
++ return NETDEV_TX_OK;
++
++err_stop_drop:
++ netif_stop_queue(net_dev);
++ dev_kfree_skb(skb);
++ return NETDEV_TX_OK;
++}
++
++/* Free transmitted packets */
++static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
++{
++ struct device *dma_dev = bgmac->core->dma_dev;
++ int empty_slot;
++ bool freed = false;
++
++ /* The last slot that hardware didn't consume yet */
++ empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
++ empty_slot &= BGMAC_DMA_TX_STATDPTR;
++ empty_slot /= sizeof(struct bgmac_dma_desc);
++
++ while (ring->start != empty_slot) {
++ struct bgmac_slot_info *slot = &ring->slots[ring->start];
++
++ if (slot->skb) {
++ /* Unmap no longer used buffer */
++ dma_unmap_single(dma_dev, slot->dma_addr,
++ slot->skb->len, DMA_TO_DEVICE);
++ slot->dma_addr = 0;
++
++ /* Free memory! :) */
++ dev_kfree_skb(slot->skb);
++ slot->skb = NULL;
++ } else {
++ bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n",
++ ring->start, ring->end);
++ }
++
++ if (++ring->start >= BGMAC_TX_RING_SLOTS)
++ ring->start = 0;
++ freed = true;
++ }
++
++ if (freed && netif_queue_stopped(bgmac->net_dev))
++ netif_wake_queue(bgmac->net_dev);
++}
++
++static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
++{
++ if (!ring->mmio_base)
++ return;
++
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
++ if (!bgmac_wait_value(bgmac->core,
++ ring->mmio_base + BGMAC_DMA_RX_STATUS,
++ BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
++ 10000))
++ bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
++ ring->mmio_base);
++}
++
++static void bgmac_dma_rx_enable(struct bgmac *bgmac,
++ struct bgmac_dma_ring *ring)
++{
++ u32 ctl;
++
++ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
++ ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
++ ctl |= BGMAC_DMA_RX_ENABLE;
++ ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
++ ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
++ ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
++}
++
++static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
++ struct bgmac_slot_info *slot)
++{
++ struct device *dma_dev = bgmac->core->dma_dev;
++ struct bgmac_rx_header *rx;
++
++ /* Alloc skb */
++ slot->skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE);
++ if (!slot->skb) {
++ bgmac_err(bgmac, "Allocation of skb failed!\n");
++ return -ENOMEM;
++ }
++
++ /* Poison - if everything goes fine, hardware will overwrite it */
++ rx = (struct bgmac_rx_header *)slot->skb->data;
++ rx->len = cpu_to_le16(0xdead);
++ rx->flags = cpu_to_le16(0xbeef);
++
++ /* Map skb for the DMA */
++ slot->dma_addr = dma_map_single(dma_dev, slot->skb->data,
++ BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
++ if (dma_mapping_error(dma_dev, slot->dma_addr)) {
++ bgmac_err(bgmac, "DMA mapping error\n");
++ return -ENOMEM;
++ }
++ if (slot->dma_addr & 0xC0000000)
++ bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
++
++ return 0;
++}
++
++static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
++ int weight)
++{
++ u32 end_slot;
++ int handled = 0;
++
++ end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
++ end_slot &= BGMAC_DMA_RX_STATDPTR;
++ end_slot /= sizeof(struct bgmac_dma_desc);
++
++ ring->end = end_slot;
++
++ while (ring->start != ring->end) {
++ struct device *dma_dev = bgmac->core->dma_dev;
++ struct bgmac_slot_info *slot = &ring->slots[ring->start];
++ struct sk_buff *skb = slot->skb;
++ struct sk_buff *new_skb;
++ struct bgmac_rx_header *rx;
++ u16 len, flags;
++
++ /* Unmap buffer to make it accessible to the CPU */
++ dma_sync_single_for_cpu(dma_dev, slot->dma_addr,
++ BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
++
++ /* Get info from the header */
++ rx = (struct bgmac_rx_header *)skb->data;
++ len = le16_to_cpu(rx->len);
++ flags = le16_to_cpu(rx->flags);
++
++ /* Check for poison and drop or pass the packet */
++ if (len == 0xdead && flags == 0xbeef) {
++ bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
++ ring->start);
++ } else {
++ new_skb = netdev_alloc_skb(bgmac->net_dev, len);
++ if (new_skb) {
++ skb_put(new_skb, len);
++ skb_copy_from_linear_data_offset(skb, BGMAC_RX_FRAME_OFFSET,
++ new_skb->data,
++ len);
++ new_skb->protocol =
++ eth_type_trans(new_skb, bgmac->net_dev);
++ netif_receive_skb(new_skb);
++ handled++;
++ } else {
++ bgmac->net_dev->stats.rx_dropped++;
++ bgmac_err(bgmac, "Allocation of skb for copying packet failed!\n");
++ }
++
++ /* Poison the old skb */
++ rx->len = cpu_to_le16(0xdead);
++ rx->flags = cpu_to_le16(0xbeef);
++ }
++
++ /* Make it back accessible to the hardware */
++ dma_sync_single_for_device(dma_dev, slot->dma_addr,
++ BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
++
++ if (++ring->start >= BGMAC_RX_RING_SLOTS)
++ ring->start = 0;
++
++ if (handled >= weight) /* Should never be greater */
++ break;
++ }
++
++ return handled;
++}
++
++/* Does ring support unaligned addressing? */
++static bool bgmac_dma_unaligned(struct bgmac *bgmac,
++ struct bgmac_dma_ring *ring,
++ enum bgmac_dma_ring_type ring_type)
++{
++ switch (ring_type) {
++ case BGMAC_DMA_RING_TX:
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
++ 0xff0);
++ if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
++ return true;
++ break;
++ case BGMAC_DMA_RING_RX:
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
++ 0xff0);
++ if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
++ return true;
++ break;
++ }
++ return false;
++}
++
++static void bgmac_dma_ring_free(struct bgmac *bgmac,
++ struct bgmac_dma_ring *ring)
++{
++ struct device *dma_dev = bgmac->core->dma_dev;
++ struct bgmac_slot_info *slot;
++ int size;
++ int i;
++
++ for (i = 0; i < ring->num_slots; i++) {
++ slot = &ring->slots[i];
++ if (slot->skb) {
++ if (slot->dma_addr)
++ dma_unmap_single(dma_dev, slot->dma_addr,
++ slot->skb->len, DMA_TO_DEVICE);
++ dev_kfree_skb(slot->skb);
++ }
++ }
++
++ if (ring->cpu_base) {
++ /* Free ring of descriptors */
++ size = ring->num_slots * sizeof(struct bgmac_dma_desc);
++ dma_free_coherent(dma_dev, size, ring->cpu_base,
++ ring->dma_base);
++ }
++}
++
++static void bgmac_dma_free(struct bgmac *bgmac)
++{
++ int i;
++
++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
++ bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]);
++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
++ bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]);
++}
++
++static int bgmac_dma_alloc(struct bgmac *bgmac)
++{
++ struct device *dma_dev = bgmac->core->dma_dev;
++ struct bgmac_dma_ring *ring;
++ static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
++ BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
++ int size; /* ring size: different for Tx and Rx */
++ int err;
++ int i;
++
++ BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
++ BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
++
++ if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
++ bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
++ return -ENOTSUPP;
++ }
++
++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
++ ring = &bgmac->tx_ring[i];
++ ring->num_slots = BGMAC_TX_RING_SLOTS;
++ ring->mmio_base = ring_base[i];
++ if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_TX))
++ bgmac_warn(bgmac, "TX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
++ ring->mmio_base);
++
++ /* Alloc ring of descriptors */
++ size = ring->num_slots * sizeof(struct bgmac_dma_desc);
++ ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
++ &ring->dma_base,
++ GFP_KERNEL);
++ if (!ring->cpu_base) {
++ bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
++ ring->mmio_base);
++ goto err_dma_free;
++ }
++ if (ring->dma_base & 0xC0000000)
++ bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
++
++ /* No need to alloc TX slots yet */
++ }
++
++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
++ ring = &bgmac->rx_ring[i];
++ ring->num_slots = BGMAC_RX_RING_SLOTS;
++ ring->mmio_base = ring_base[i];
++ if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_RX))
++ bgmac_warn(bgmac, "RX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
++ ring->mmio_base);
++
++ /* Alloc ring of descriptors */
++ size = ring->num_slots * sizeof(struct bgmac_dma_desc);
++ ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
++ &ring->dma_base,
++ GFP_KERNEL);
++ if (!ring->cpu_base) {
++ bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
++ ring->mmio_base);
++ err = -ENOMEM;
++ goto err_dma_free;
++ }
++ if (ring->dma_base & 0xC0000000)
++ bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
++
++ /* Alloc RX slots */
++ for (i = 0; i < ring->num_slots; i++) {
++ err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[i]);
++ if (err) {
++ bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n");
++ goto err_dma_free;
++ }
++ }
++ }
++
++ return 0;
++
++err_dma_free:
++ bgmac_dma_free(bgmac);
++ return -ENOMEM;
++}
++
++static void bgmac_dma_init(struct bgmac *bgmac)
++{
++ struct bgmac_dma_ring *ring;
++ struct bgmac_dma_desc *dma_desc;
++ u32 ctl0, ctl1;
++ int i;
++
++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
++ ring = &bgmac->tx_ring[i];
++
++ /* We don't implement unaligned addressing, so enable first */
++ bgmac_dma_tx_enable(bgmac, ring);
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
++ lower_32_bits(ring->dma_base));
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
++ upper_32_bits(ring->dma_base));
++
++ ring->start = 0;
++ ring->end = 0; /* Points the slot that should *not* be read */
++ }
++
++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
++ ring = &bgmac->rx_ring[i];
++
++ /* We don't implement unaligned addressing, so enable first */
++ bgmac_dma_rx_enable(bgmac, ring);
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
++ lower_32_bits(ring->dma_base));
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
++ upper_32_bits(ring->dma_base));
++
++ for (i = 0, dma_desc = ring->cpu_base; i < ring->num_slots;
++ i++, dma_desc++) {
++ ctl0 = ctl1 = 0;
++
++ if (i == ring->num_slots - 1)
++ ctl0 |= BGMAC_DESC_CTL0_EOT;
++ ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
++ /* Is there any BGMAC device that requires extension? */
++ /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
++ * B43_DMA64_DCTL1_ADDREXT_MASK;
++ */
++
++ dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[i].dma_addr));
++ dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[i].dma_addr));
++ dma_desc->ctl0 = cpu_to_le32(ctl0);
++ dma_desc->ctl1 = cpu_to_le32(ctl1);
++ }
++
++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
++ ring->num_slots * sizeof(struct bgmac_dma_desc));
++
++ ring->start = 0;
++ ring->end = 0;
++ }
++}
++
++/**************************************************
++ * PHY ops
++ **************************************************/
++
++u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
++{
++ struct bcma_device *core;
++ u16 phy_access_addr;
++ u16 phy_ctl_addr;
++ u32 tmp;
++
++ BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
++ BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
++ BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
++ BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
++ BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
++ BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
++ BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
++ BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
++ BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
++ BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
++ BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
++
++ if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
++ core = bgmac->core->bus->drv_gmac_cmn.core;
++ phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
++ phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
++ } else {
++ core = bgmac->core;
++ phy_access_addr = BGMAC_PHY_ACCESS;
++ phy_ctl_addr = BGMAC_PHY_CNTL;
++ }
++
++ tmp = bcma_read32(core, phy_ctl_addr);
++ tmp &= ~BGMAC_PC_EPA_MASK;
++ tmp |= phyaddr;
++ bcma_write32(core, phy_ctl_addr, tmp);
++
++ tmp = BGMAC_PA_START;
++ tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
++ tmp |= reg << BGMAC_PA_REG_SHIFT;
++ bcma_write32(core, phy_access_addr, tmp);
++
++ if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
++ bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
++ phyaddr, reg);
++ return 0xffff;
++ }
++
++ return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
++}
++
++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
++void bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
++{
++ struct bcma_device *core;
++ u16 phy_access_addr;
++ u16 phy_ctl_addr;
++ u32 tmp;
++
++ if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
++ core = bgmac->core->bus->drv_gmac_cmn.core;
++ phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
++ phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
++ } else {
++ core = bgmac->core;
++ phy_access_addr = BGMAC_PHY_ACCESS;
++ phy_ctl_addr = BGMAC_PHY_CNTL;
++ }
++
++ tmp = bcma_read32(core, phy_ctl_addr);
++ tmp &= ~BGMAC_PC_EPA_MASK;
++ tmp |= phyaddr;
++ bcma_write32(core, phy_ctl_addr, tmp);
++
++ bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
++ if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
++ bgmac_warn(bgmac, "Error setting MDIO int\n");
++
++ tmp = BGMAC_PA_START;
++ tmp |= BGMAC_PA_WRITE;
++ tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
++ tmp |= reg << BGMAC_PA_REG_SHIFT;
++ tmp |= value;
++ bcma_write32(core, phy_access_addr, tmp);
++
++ if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000))
++ bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
++ phyaddr, reg);
++}
++
++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyforce */
++static void bgmac_phy_force(struct bgmac *bgmac)
++{
++ u16 ctl;
++ u16 mask = ~(BGMAC_PHY_CTL_SPEED | BGMAC_PHY_CTL_SPEED_MSB |
++ BGMAC_PHY_CTL_ANENAB | BGMAC_PHY_CTL_DUPLEX);
++
++ if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
++ return;
++
++ if (bgmac->autoneg)
++ return;
++
++ ctl = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL);
++ ctl &= mask;
++ if (bgmac->full_duplex)
++ ctl |= BGMAC_PHY_CTL_DUPLEX;
++ if (bgmac->speed == BGMAC_SPEED_100)
++ ctl |= BGMAC_PHY_CTL_SPEED_100;
++ else if (bgmac->speed == BGMAC_SPEED_1000)
++ ctl |= BGMAC_PHY_CTL_SPEED_1000;
++ bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ctl);
++}
++
++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyadvertise */
++static void bgmac_phy_advertise(struct bgmac *bgmac)
++{
++ u16 adv;
++
++ if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
++ return;
++
++ if (!bgmac->autoneg)
++ return;
++
++ /* Adv selected 10/100 speeds */
++ adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV);
++ adv &= ~(BGMAC_PHY_ADV_10HALF | BGMAC_PHY_ADV_10FULL |
++ BGMAC_PHY_ADV_100HALF | BGMAC_PHY_ADV_100FULL);
++ if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
++ adv |= BGMAC_PHY_ADV_10HALF;
++ if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
++ adv |= BGMAC_PHY_ADV_100HALF;
++ if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
++ adv |= BGMAC_PHY_ADV_10FULL;
++ if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
++ adv |= BGMAC_PHY_ADV_100FULL;
++ bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV, adv);
++
++ /* Adv selected 1000 speeds */
++ adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2);
++ adv &= ~(BGMAC_PHY_ADV2_1000HALF | BGMAC_PHY_ADV2_1000FULL);
++ if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
++ adv |= BGMAC_PHY_ADV2_1000HALF;
++ if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
++ adv |= BGMAC_PHY_ADV2_1000FULL;
++ bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2, adv);
++
++ /* Restart */
++ bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
++ bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) |
++ BGMAC_PHY_CTL_RESTART);
++}
++
++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
++static void bgmac_phy_init(struct bgmac *bgmac)
++{
++ struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
++ struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
++ u8 i;
++
++ if (ci->id == BCMA_CHIP_ID_BCM5356) {
++ for (i = 0; i < 5; i++) {
++ bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
++ bgmac_phy_write(bgmac, i, 0x15, 0x0100);
++ bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
++ bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
++ bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
++ }
++ }
++ if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
++ (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
++ (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
++ bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
++ bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
++ for (i = 0; i < 5; i++) {
++ bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
++ bgmac_phy_write(bgmac, i, 0x16, 0x5284);
++ bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
++ bgmac_phy_write(bgmac, i, 0x17, 0x0010);
++ bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
++ bgmac_phy_write(bgmac, i, 0x16, 0x5296);
++ bgmac_phy_write(bgmac, i, 0x17, 0x1073);
++ bgmac_phy_write(bgmac, i, 0x17, 0x9073);
++ bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
++ bgmac_phy_write(bgmac, i, 0x17, 0x9273);
++ bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
++ }
++ }
++}
++
++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
++static void bgmac_phy_reset(struct bgmac *bgmac)
++{
++ if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
++ return;
++
++ bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
++ BGMAC_PHY_CTL_RESET);
++ udelay(100);
++ if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
++ BGMAC_PHY_CTL_RESET)
++ bgmac_err(bgmac, "PHY reset failed\n");
++ bgmac_phy_init(bgmac);
++}
++
++/**************************************************
++ * Chip ops
++ **************************************************/
++
++/* TODO: can we just drop @force? Can we don't reset MAC at all if there is
++ * nothing to change? Try if after stabilizng driver.
++ */
++static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
++ bool force)
++{
++ u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
++ u32 new_val = (cmdcfg & mask) | set;
++
++ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
++ udelay(2);
++
++ if (new_val != cmdcfg || force)
++ bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
++
++ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
++ udelay(2);
++}
++
++#if 0 /* We don't use that regs yet */
++static void bgmac_chip_stats_update(struct bgmac *bgmac)
++{
++ int i;
++
++ if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
++ for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
++ bgmac->mib_tx_regs[i] =
++ bgmac_read(bgmac,
++ BGMAC_TX_GOOD_OCTETS + (i * 4));
++ for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
++ bgmac->mib_rx_regs[i] =
++ bgmac_read(bgmac,
++ BGMAC_RX_GOOD_OCTETS + (i * 4));
++ }
++
++ /* TODO: what else? how to handle BCM4706? Specs are needed */
++}
++#endif
++
++static void bgmac_clear_mib(struct bgmac *bgmac)
++{
++ int i;
++
++ if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
++ return;
++
++ bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
++ for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
++ bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
++ for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
++ bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
++}
++
++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
++static void bgmac_speed(struct bgmac *bgmac, int speed)
++{
++ u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
++ u32 set = 0;
++
++ if (speed & BGMAC_SPEED_10)
++ set |= BGMAC_CMDCFG_ES_10;
++ if (speed & BGMAC_SPEED_100)
++ set |= BGMAC_CMDCFG_ES_100;
++ if (speed & BGMAC_SPEED_1000)
++ set |= BGMAC_CMDCFG_ES_1000;
++ if (!bgmac->full_duplex)
++ set |= BGMAC_CMDCFG_HD;
++ bgmac_cmdcfg_maskset(bgmac, mask, set, true);
++}
++
++static void bgmac_miiconfig(struct bgmac *bgmac)
++{
++ u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
++ BGMAC_DS_MM_SHIFT;
++ if (imode == 0 || imode == 1) {
++ if (bgmac->autoneg)
++ bgmac_speed(bgmac, BGMAC_SPEED_100);
++ else
++ bgmac_speed(bgmac, bgmac->speed);
++ }
++}
++
++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
++static void bgmac_chip_reset(struct bgmac *bgmac)
++{
++ struct bcma_device *core = bgmac->core;
++ struct bcma_bus *bus = core->bus;
++ struct bcma_chipinfo *ci = &bus->chipinfo;
++ u32 flags = 0;
++ u32 iost;
++ int i;
++
++ if (bcma_core_is_enabled(core)) {
++ if (!bgmac->stats_grabbed) {
++ /* bgmac_chip_stats_update(bgmac); */
++ bgmac->stats_grabbed = true;
++ }
++
++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
++ bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
++
++ bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
++ udelay(1);
++
++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
++ bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
++
++ /* TODO: Clear software multicast filter list */
++ }
++
++ iost = bcma_aread32(core, BCMA_IOST);
++ if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) ||
++ (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
++ (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9))
++ iost &= ~BGMAC_BCMA_IOST_ATTACHED;
++
++ if (iost & BGMAC_BCMA_IOST_ATTACHED) {
++ flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
++ if (!bgmac->has_robosw)
++ flags |= BGMAC_BCMA_IOCTL_SW_RESET;
++ }
++
++ bcma_core_enable(core, flags);
++
++ if (core->id.rev > 2) {
++ bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
++ bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
++ 1000);
++ }
++
++ if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 ||
++ ci->id == BCMA_CHIP_ID_BCM53572) {
++ struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
++ u8 et_swtype = 0;
++ u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
++ BGMAC_CHIPCTL_1_IF_TYPE_RMII;
++ char buf[2];
++
++ if (bcm47xx_nvram_getenv("et_swtype", buf, 1) > 0) {
++ if (kstrtou8(buf, 0, &et_swtype))
++ bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
++ buf);
++ et_swtype &= 0x0f;
++ et_swtype <<= 4;
++ sw_type = et_swtype;
++ } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
++ sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
++ } else if (0) {
++ /* TODO */
++ }
++ bcma_chipco_chipctl_maskset(cc, 1,
++ ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
++ BGMAC_CHIPCTL_1_SW_TYPE_MASK),
++ sw_type);
++ }
++
++ if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
++ bcma_awrite32(core, BCMA_IOCTL,
++ bcma_aread32(core, BCMA_IOCTL) &
++ ~BGMAC_BCMA_IOCTL_SW_RESET);
++
++ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
++ * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
++ * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
++ * be keps until taking MAC out of the reset.
++ */
++ bgmac_cmdcfg_maskset(bgmac,
++ ~(BGMAC_CMDCFG_TE |
++ BGMAC_CMDCFG_RE |
++ BGMAC_CMDCFG_RPI |
++ BGMAC_CMDCFG_TAI |
++ BGMAC_CMDCFG_HD |
++ BGMAC_CMDCFG_ML |
++ BGMAC_CMDCFG_CFE |
++ BGMAC_CMDCFG_RL |
++ BGMAC_CMDCFG_RED |
++ BGMAC_CMDCFG_PE |
++ BGMAC_CMDCFG_TPI |
++ BGMAC_CMDCFG_PAD_EN |
++ BGMAC_CMDCFG_PF),
++ BGMAC_CMDCFG_PROM |
++ BGMAC_CMDCFG_NLC |
++ BGMAC_CMDCFG_CFE |
++ BGMAC_CMDCFG_SR,
++ false);
++
++ bgmac_clear_mib(bgmac);
++ if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
++ bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
++ BCMA_GMAC_CMN_PC_MTE);
++ else
++ bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
++ bgmac_miiconfig(bgmac);
++ bgmac_phy_init(bgmac);
++
++ bgmac->int_status = 0;
++}
++
++static void bgmac_chip_intrs_on(struct bgmac *bgmac)
++{
++ bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
++}
++
++static void bgmac_chip_intrs_off(struct bgmac *bgmac)
++{
++ bgmac_write(bgmac, BGMAC_INT_MASK, 0);
++}
++
++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
++static void bgmac_enable(struct bgmac *bgmac)
++{
++ struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
++ u32 cmdcfg;
++ u32 mode;
++ u32 rxq_ctl;
++ u32 fl_ctl;
++ u16 bp_clk;
++ u8 mdp;
++
++ cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
++ bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
++ BGMAC_CMDCFG_SR, true);
++ udelay(2);
++ cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
++ bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
++
++ mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
++ BGMAC_DS_MM_SHIFT;
++ if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
++ bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
++ if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
++ bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
++ BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
++
++ switch (ci->id) {
++ case BCMA_CHIP_ID_BCM5357:
++ case BCMA_CHIP_ID_BCM4749:
++ case BCMA_CHIP_ID_BCM53572:
++ case BCMA_CHIP_ID_BCM4716:
++ case BCMA_CHIP_ID_BCM47162:
++ fl_ctl = 0x03cb04cb;
++ if (ci->id == BCMA_CHIP_ID_BCM5357 ||
++ ci->id == BCMA_CHIP_ID_BCM4749 ||
++ ci->id == BCMA_CHIP_ID_BCM53572)
++ fl_ctl = 0x2300e1;
++ bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
++ bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
++ break;
++ }
++
++ rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
++ rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
++ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
++ mdp = (bp_clk * 128 / 1000) - 3;
++ rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
++ bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
++}
++
++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
++static void bgmac_chip_init(struct bgmac *bgmac, bool full_init)
++{
++ struct bgmac_dma_ring *ring;
++ u8 *mac = bgmac->net_dev->dev_addr;
++ u32 tmp;
++ int i;
++
++ /* 1 interrupt per received frame */
++ bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
++
++ /* Enable 802.3x tx flow control (honor received PAUSE frames) */
++ bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
++
++ if (bgmac->net_dev->flags & IFF_PROMISC)
++ bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, false);
++ else
++ bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, false);
++
++ /* Set MAC addr */
++ tmp = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
++ bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
++ tmp = (mac[4] << 8) | mac[5];
++ bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
++
++ if (bgmac->loopback)
++ bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, true);
++ else
++ bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, true);
++
++ bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
++
++ if (!bgmac->autoneg) {
++ bgmac_speed(bgmac, bgmac->speed);
++ bgmac_phy_force(bgmac);
++ } else if (bgmac->speed) { /* if there is anything to adv */
++ bgmac_phy_advertise(bgmac);
++ }
++
++ if (full_init) {
++ bgmac_dma_init(bgmac);
++ if (1) /* FIXME: is there any case we don't want IRQs? */
++ bgmac_chip_intrs_on(bgmac);
++ } else {
++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
++ ring = &bgmac->rx_ring[i];
++ bgmac_dma_rx_enable(bgmac, ring);
++ }
++ }
++
++ bgmac_enable(bgmac);
++}
++
++static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
++{
++ struct bgmac *bgmac = netdev_priv(dev_id);
++
++ u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
++ int_status &= bgmac->int_mask;
++
++ if (!int_status)
++ return IRQ_NONE;
++
++ /* Ack */
++ bgmac_write(bgmac, BGMAC_INT_STATUS, int_status);
++
++ /* Disable new interrupts until handling existing ones */
++ bgmac_chip_intrs_off(bgmac);
++
++ bgmac->int_status = int_status;
++
++ napi_schedule(&bgmac->napi);
++
++ return IRQ_HANDLED;
++}
++
++static int bgmac_poll(struct napi_struct *napi, int weight)
++{
++ struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
++ struct bgmac_dma_ring *ring;
++ int handled = 0;
++
++ if (bgmac->int_status & BGMAC_IS_TX0) {
++ ring = &bgmac->tx_ring[0];
++ bgmac_dma_tx_free(bgmac, ring);
++ bgmac->int_status &= ~BGMAC_IS_TX0;
++ }
++
++ if (bgmac->int_status & BGMAC_IS_RX) {
++ ring = &bgmac->rx_ring[0];
++ handled += bgmac_dma_rx_read(bgmac, ring, weight);
++ bgmac->int_status &= ~BGMAC_IS_RX;
++ }
++
++ if (bgmac->int_status) {
++ bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status);
++ bgmac->int_status = 0;
++ }
++
++ if (handled < weight)
++ napi_complete(napi);
++
++ bgmac_chip_intrs_on(bgmac);
++
++ return handled;
++}
++
++/**************************************************
++ * net_device_ops
++ **************************************************/
++
++static int bgmac_open(struct net_device *net_dev)
++{
++ struct bgmac *bgmac = netdev_priv(net_dev);
++ int err = 0;
++
++ bgmac_chip_reset(bgmac);
++ /* Specs say about reclaiming rings here, but we do that in DMA init */
++ bgmac_chip_init(bgmac, true);
++
++ err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
++ KBUILD_MODNAME, net_dev);
++ if (err < 0) {
++ bgmac_err(bgmac, "IRQ request error: %d!\n", err);
++ goto err_out;
++ }
++ napi_enable(&bgmac->napi);
++
++ netif_carrier_on(net_dev);
++
++err_out:
++ return err;
++}
++
++static int bgmac_stop(struct net_device *net_dev)
++{
++ struct bgmac *bgmac = netdev_priv(net_dev);
++
++ netif_carrier_off(net_dev);
++
++ napi_disable(&bgmac->napi);
++ bgmac_chip_intrs_off(bgmac);
++ free_irq(bgmac->core->irq, net_dev);
++
++ bgmac_chip_reset(bgmac);
++
++ return 0;
++}
++
++static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
++ struct net_device *net_dev)
++{
++ struct bgmac *bgmac = netdev_priv(net_dev);
++ struct bgmac_dma_ring *ring;
++
++ /* No QOS support yet */
++ ring = &bgmac->tx_ring[0];
++ return bgmac_dma_tx_add(bgmac, ring, skb);
++}
++
++static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
++{
++ struct bgmac *bgmac = netdev_priv(net_dev);
++ struct mii_ioctl_data *data = if_mii(ifr);
++
++ switch (cmd) {
++ case SIOCGMIIPHY:
++ data->phy_id = bgmac->phyaddr;
++ /* fallthru */
++ case SIOCGMIIREG:
++ if (!netif_running(net_dev))
++ return -EAGAIN;
++ data->val_out = bgmac_phy_read(bgmac, data->phy_id,
++ data->reg_num & 0x1f);
++ return 0;
++ case SIOCSMIIREG:
++ if (!netif_running(net_dev))
++ return -EAGAIN;
++ bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
++ data->val_in);
++ return 0;
++ default:
++ return -EOPNOTSUPP;
++ }
++}
++
++static const struct net_device_ops bgmac_netdev_ops = {
++ .ndo_open = bgmac_open,
++ .ndo_stop = bgmac_stop,
++ .ndo_start_xmit = bgmac_start_xmit,
++ .ndo_set_mac_address = eth_mac_addr, /* generic, sets dev_addr */
++ .ndo_do_ioctl = bgmac_ioctl,
++};
++
++/**************************************************
++ * ethtool_ops
++ **************************************************/
++
++static int bgmac_get_settings(struct net_device *net_dev,
++ struct ethtool_cmd *cmd)
++{
++ struct bgmac *bgmac = netdev_priv(net_dev);
++
++ cmd->supported = SUPPORTED_10baseT_Half |
++ SUPPORTED_10baseT_Full |
++ SUPPORTED_100baseT_Half |
++ SUPPORTED_100baseT_Full |
++ SUPPORTED_1000baseT_Half |
++ SUPPORTED_1000baseT_Full |
++ SUPPORTED_Autoneg;
++
++ if (bgmac->autoneg) {
++ WARN_ON(cmd->advertising);
++ if (bgmac->full_duplex) {
++ if (bgmac->speed & BGMAC_SPEED_10)
++ cmd->advertising |= ADVERTISED_10baseT_Full;
++ if (bgmac->speed & BGMAC_SPEED_100)
++ cmd->advertising |= ADVERTISED_100baseT_Full;
++ if (bgmac->speed & BGMAC_SPEED_1000)
++ cmd->advertising |= ADVERTISED_1000baseT_Full;
++ } else {
++ if (bgmac->speed & BGMAC_SPEED_10)
++ cmd->advertising |= ADVERTISED_10baseT_Half;
++ if (bgmac->speed & BGMAC_SPEED_100)
++ cmd->advertising |= ADVERTISED_100baseT_Half;
++ if (bgmac->speed & BGMAC_SPEED_1000)
++ cmd->advertising |= ADVERTISED_1000baseT_Half;
++ }
++ } else {
++ switch (bgmac->speed) {
++ case BGMAC_SPEED_10:
++ ethtool_cmd_speed_set(cmd, SPEED_10);
++ break;
++ case BGMAC_SPEED_100:
++ ethtool_cmd_speed_set(cmd, SPEED_100);
++ break;
++ case BGMAC_SPEED_1000:
++ ethtool_cmd_speed_set(cmd, SPEED_1000);
++ break;
++ }
++ }
++
++ cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
++
++ cmd->autoneg = bgmac->autoneg;
++
++ return 0;
++}
++
++#if 0
++static int bgmac_set_settings(struct net_device *net_dev,
++ struct ethtool_cmd *cmd)
++{
++ struct bgmac *bgmac = netdev_priv(net_dev);
++
++ return -1;
++}
++#endif
++
++static void bgmac_get_drvinfo(struct net_device *net_dev,
++ struct ethtool_drvinfo *info)
++{
++ strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
++ strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
++}
++
++static const struct ethtool_ops bgmac_ethtool_ops = {
++ .get_settings = bgmac_get_settings,
++ .get_drvinfo = bgmac_get_drvinfo,
++};
++
++/**************************************************
++ * BCMA bus ops
++ **************************************************/
++
++/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
++static int bgmac_probe(struct bcma_device *core)
++{
++ struct net_device *net_dev;
++ struct bgmac *bgmac;
++ struct ssb_sprom *sprom = &core->bus->sprom;
++ u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
++ int err;
++
++ /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
++ if (core->core_unit > 1) {
++ pr_err("Unsupported core_unit %d\n", core->core_unit);
++ return -ENOTSUPP;
++ }
++
++ /* Allocation and references */
++ net_dev = alloc_etherdev(sizeof(*bgmac));
++ if (!net_dev)
++ return -ENOMEM;
++ net_dev->netdev_ops = &bgmac_netdev_ops;
++ net_dev->irq = core->irq;
++ SET_ETHTOOL_OPS(net_dev, &bgmac_ethtool_ops);
++ bgmac = netdev_priv(net_dev);
++ bgmac->net_dev = net_dev;
++ bgmac->core = core;
++ bcma_set_drvdata(core, bgmac);
++
++ /* Defaults */
++ bgmac->autoneg = true;
++ bgmac->full_duplex = true;
++ bgmac->speed = BGMAC_SPEED_10 | BGMAC_SPEED_100 | BGMAC_SPEED_1000;
++ memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
++
++ /* On BCM4706 we need common core to access PHY */
++ if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
++ !core->bus->drv_gmac_cmn.core) {
++ bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
++ err = -ENODEV;
++ goto err_netdev_free;
++ }
++ bgmac->cmn = core->bus->drv_gmac_cmn.core;
++
++ bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
++ sprom->et0phyaddr;
++ bgmac->phyaddr &= BGMAC_PHY_MASK;
++ if (bgmac->phyaddr == BGMAC_PHY_MASK) {
++ bgmac_err(bgmac, "No PHY found\n");
++ err = -ENODEV;
++ goto err_netdev_free;
++ }
++ bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
++ bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
++
++ if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
++ bgmac_err(bgmac, "PCI setup not implemented\n");
++ err = -ENOTSUPP;
++ goto err_netdev_free;
++ }
++
++ bgmac_chip_reset(bgmac);
++
++ err = bgmac_dma_alloc(bgmac);
++ if (err) {
++ bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
++ goto err_netdev_free;
++ }
++
++ bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
++ if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
++ bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
++
++ /* TODO: reset the external phy. Specs are needed */
++ bgmac_phy_reset(bgmac);
++
++ bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
++ BGMAC_BFL_ENETROBO);
++ if (bgmac->has_robosw)
++ bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
++
++ if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
++ bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
++
++ err = register_netdev(bgmac->net_dev);
++ if (err) {
++ bgmac_err(bgmac, "Cannot register net device\n");
++ err = -ENOTSUPP;
++ goto err_dma_free;
++ }
++
++ netif_carrier_off(net_dev);
++
++ netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
++
++ return 0;
++
++err_dma_free:
++ bgmac_dma_free(bgmac);
++
++err_netdev_free:
++ bcma_set_drvdata(core, NULL);
++ free_netdev(net_dev);
++
++ return err;
++}
++
++static void bgmac_remove(struct bcma_device *core)
++{
++ struct bgmac *bgmac = bcma_get_drvdata(core);
++
++ netif_napi_del(&bgmac->napi);
++ unregister_netdev(bgmac->net_dev);
++ bgmac_dma_free(bgmac);
++ bcma_set_drvdata(core, NULL);
++ free_netdev(bgmac->net_dev);
++}
++
++static struct bcma_driver bgmac_bcma_driver = {
++ .name = KBUILD_MODNAME,
++ .id_table = bgmac_bcma_tbl,
++ .probe = bgmac_probe,
++ .remove = bgmac_remove,
++};
++
++static int __init bgmac_init(void)
++{
++ int err;
++
++ err = bcma_driver_register(&bgmac_bcma_driver);
++ if (err)
++ return err;
++ pr_info("Broadcom 47xx GBit MAC driver loaded\n");
++
++ return 0;
++}
++
++static void __exit bgmac_exit(void)
++{
++ bcma_driver_unregister(&bgmac_bcma_driver);
++}
++
++module_init(bgmac_init)
++module_exit(bgmac_exit)
++
++MODULE_AUTHOR("Rafał Miłecki");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/net/ethernet/broadcom/bgmac.h
+@@ -0,0 +1,456 @@
++#ifndef _BGMAC_H
++#define _BGMAC_H
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#define bgmac_err(bgmac, fmt, ...) \
++ dev_err(&(bgmac)->core->dev, fmt, ##__VA_ARGS__)
++#define bgmac_warn(bgmac, fmt, ...) \
++ dev_warn(&(bgmac)->core->dev, fmt, ##__VA_ARGS__)
++#define bgmac_info(bgmac, fmt, ...) \
++ dev_info(&(bgmac)->core->dev, fmt, ##__VA_ARGS__)
++#define bgmac_dbg(bgmac, fmt, ...) \
++ dev_dbg(&(bgmac)->core->dev, fmt, ##__VA_ARGS__)
++
++#include <linux/bcma/bcma.h>
++#include <linux/netdevice.h>
++
++#define BGMAC_DEV_CTL 0x000
++#define BGMAC_DC_TSM 0x00000002
++#define BGMAC_DC_CFCO 0x00000004
++#define BGMAC_DC_RLSS 0x00000008
++#define BGMAC_DC_MROR 0x00000010
++#define BGMAC_DC_FCM_MASK 0x00000060
++#define BGMAC_DC_FCM_SHIFT 5
++#define BGMAC_DC_NAE 0x00000080
++#define BGMAC_DC_TF 0x00000100
++#define BGMAC_DC_RDS_MASK 0x00030000
++#define BGMAC_DC_RDS_SHIFT 16
++#define BGMAC_DC_TDS_MASK 0x000c0000
++#define BGMAC_DC_TDS_SHIFT 18
++#define BGMAC_DEV_STATUS 0x004 /* Configuration of the interface */
++#define BGMAC_DS_RBF 0x00000001
++#define BGMAC_DS_RDF 0x00000002
++#define BGMAC_DS_RIF 0x00000004
++#define BGMAC_DS_TBF 0x00000008
++#define BGMAC_DS_TDF 0x00000010
++#define BGMAC_DS_TIF 0x00000020
++#define BGMAC_DS_PO 0x00000040
++#define BGMAC_DS_MM_MASK 0x00000300 /* Mode of the interface */
++#define BGMAC_DS_MM_SHIFT 8
++#define BGMAC_BIST_STATUS 0x00c
++#define BGMAC_INT_STATUS 0x020 /* Interrupt status */
++#define BGMAC_IS_MRO 0x00000001
++#define BGMAC_IS_MTO 0x00000002
++#define BGMAC_IS_TFD 0x00000004
++#define BGMAC_IS_LS 0x00000008
++#define BGMAC_IS_MDIO 0x00000010
++#define BGMAC_IS_MR 0x00000020
++#define BGMAC_IS_MT 0x00000040
++#define BGMAC_IS_TO 0x00000080
++#define BGMAC_IS_DESC_ERR 0x00000400 /* Descriptor error */
++#define BGMAC_IS_DATA_ERR 0x00000800 /* Data error */
++#define BGMAC_IS_DESC_PROT_ERR 0x00001000 /* Descriptor protocol error */
++#define BGMAC_IS_RX_DESC_UNDERF 0x00002000 /* Receive descriptor underflow */
++#define BGMAC_IS_RX_F_OVERF 0x00004000 /* Receive FIFO overflow */
++#define BGMAC_IS_TX_F_UNDERF 0x00008000 /* Transmit FIFO underflow */
++#define BGMAC_IS_RX 0x00010000 /* Interrupt for RX queue 0 */
++#define BGMAC_IS_TX0 0x01000000 /* Interrupt for TX queue 0 */
++#define BGMAC_IS_TX1 0x02000000 /* Interrupt for TX queue 1 */
++#define BGMAC_IS_TX2 0x04000000 /* Interrupt for TX queue 2 */
++#define BGMAC_IS_TX3 0x08000000 /* Interrupt for TX queue 3 */
++#define BGMAC_IS_TX_MASK 0x0f000000
++#define BGMAC_IS_INTMASK 0x0f01fcff
++#define BGMAC_IS_ERRMASK 0x0000fc00
++#define BGMAC_INT_MASK 0x024 /* Interrupt mask */
++#define BGMAC_GP_TIMER 0x028
++#define BGMAC_INT_RECV_LAZY 0x100
++#define BGMAC_IRL_TO_MASK 0x00ffffff
++#define BGMAC_IRL_FC_MASK 0xff000000
++#define BGMAC_IRL_FC_SHIFT 24 /* Shift the number of interrupts triggered per received frame */
++#define BGMAC_FLOW_CTL_THRESH 0x104 /* Flow control thresholds */
++#define BGMAC_WRRTHRESH 0x108
++#define BGMAC_GMAC_IDLE_CNT_THRESH 0x10c
++#define BGMAC_PHY_ACCESS 0x180 /* PHY access address */
++#define BGMAC_PA_DATA_MASK 0x0000ffff
++#define BGMAC_PA_ADDR_MASK 0x001f0000
++#define BGMAC_PA_ADDR_SHIFT 16
++#define BGMAC_PA_REG_MASK 0x1f000000
++#define BGMAC_PA_REG_SHIFT 24
++#define BGMAC_PA_WRITE 0x20000000
++#define BGMAC_PA_START 0x40000000
++#define BGMAC_PHY_CNTL 0x188 /* PHY control address */
++#define BGMAC_PC_EPA_MASK 0x0000001f
++#define BGMAC_PC_MCT_MASK 0x007f0000
++#define BGMAC_PC_MCT_SHIFT 16
++#define BGMAC_PC_MTE 0x00800000
++#define BGMAC_TXQ_CTL 0x18c
++#define BGMAC_TXQ_CTL_DBT_MASK 0x00000fff
++#define BGMAC_TXQ_CTL_DBT_SHIFT 0
++#define BGMAC_RXQ_CTL 0x190
++#define BGMAC_RXQ_CTL_DBT_MASK 0x00000fff
++#define BGMAC_RXQ_CTL_DBT_SHIFT 0
++#define BGMAC_RXQ_CTL_PTE 0x00001000
++#define BGMAC_RXQ_CTL_MDP_MASK 0x3f000000
++#define BGMAC_RXQ_CTL_MDP_SHIFT 24
++#define BGMAC_GPIO_SELECT 0x194
++#define BGMAC_GPIO_OUTPUT_EN 0x198
++/* For 0x1e0 see BCMA_CLKCTLST */
++#define BGMAC_HW_WAR 0x1e4
++#define BGMAC_PWR_CTL 0x1e8
++#define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */
++#define BGMAC_DMA_BASE1 0x240 /* Tx controller only */
++#define BGMAC_DMA_BASE2 0x280 /* Tx controller only */
++#define BGMAC_DMA_BASE3 0x2C0 /* Tx controller only */
++#define BGMAC_TX_GOOD_OCTETS 0x300
++#define BGMAC_TX_GOOD_OCTETS_HIGH 0x304
++#define BGMAC_TX_GOOD_PKTS 0x308
++#define BGMAC_TX_OCTETS 0x30c
++#define BGMAC_TX_OCTETS_HIGH 0x310
++#define BGMAC_TX_PKTS 0x314
++#define BGMAC_TX_BROADCAST_PKTS 0x318
++#define BGMAC_TX_MULTICAST_PKTS 0x31c
++#define BGMAC_TX_LEN_64 0x320
++#define BGMAC_TX_LEN_65_TO_127 0x324
++#define BGMAC_TX_LEN_128_TO_255 0x328
++#define BGMAC_TX_LEN_256_TO_511 0x32c
++#define BGMAC_TX_LEN_512_TO_1023 0x330
++#define BGMAC_TX_LEN_1024_TO_1522 0x334
++#define BGMAC_TX_LEN_1523_TO_2047 0x338
++#define BGMAC_TX_LEN_2048_TO_4095 0x33c
++#define BGMAC_TX_LEN_4095_TO_8191 0x340
++#define BGMAC_TX_LEN_8192_TO_MAX 0x344
++#define BGMAC_TX_JABBER_PKTS 0x348 /* Error */
++#define BGMAC_TX_OVERSIZE_PKTS 0x34c /* Error */
++#define BGMAC_TX_FRAGMENT_PKTS 0x350
++#define BGMAC_TX_UNDERRUNS 0x354 /* Error */
++#define BGMAC_TX_TOTAL_COLS 0x358
++#define BGMAC_TX_SINGLE_COLS 0x35c
++#define BGMAC_TX_MULTIPLE_COLS 0x360
++#define BGMAC_TX_EXCESSIVE_COLS 0x364 /* Error */
++#define BGMAC_TX_LATE_COLS 0x368 /* Error */
++#define BGMAC_TX_DEFERED 0x36c
++#define BGMAC_TX_CARRIER_LOST 0x370
++#define BGMAC_TX_PAUSE_PKTS 0x374
++#define BGMAC_TX_UNI_PKTS 0x378
++#define BGMAC_TX_Q0_PKTS 0x37c
++#define BGMAC_TX_Q0_OCTETS 0x380
++#define BGMAC_TX_Q0_OCTETS_HIGH 0x384
++#define BGMAC_TX_Q1_PKTS 0x388
++#define BGMAC_TX_Q1_OCTETS 0x38c
++#define BGMAC_TX_Q1_OCTETS_HIGH 0x390
++#define BGMAC_TX_Q2_PKTS 0x394
++#define BGMAC_TX_Q2_OCTETS 0x398
++#define BGMAC_TX_Q2_OCTETS_HIGH 0x39c
++#define BGMAC_TX_Q3_PKTS 0x3a0
++#define BGMAC_TX_Q3_OCTETS 0x3a4
++#define BGMAC_TX_Q3_OCTETS_HIGH 0x3a8
++#define BGMAC_RX_GOOD_OCTETS 0x3b0
++#define BGMAC_RX_GOOD_OCTETS_HIGH 0x3b4
++#define BGMAC_RX_GOOD_PKTS 0x3b8
++#define BGMAC_RX_OCTETS 0x3bc
++#define BGMAC_RX_OCTETS_HIGH 0x3c0
++#define BGMAC_RX_PKTS 0x3c4
++#define BGMAC_RX_BROADCAST_PKTS 0x3c8
++#define BGMAC_RX_MULTICAST_PKTS 0x3cc
++#define BGMAC_RX_LEN_64 0x3d0
++#define BGMAC_RX_LEN_65_TO_127 0x3d4
++#define BGMAC_RX_LEN_128_TO_255 0x3d8
++#define BGMAC_RX_LEN_256_TO_511 0x3dc
++#define BGMAC_RX_LEN_512_TO_1023 0x3e0
++#define BGMAC_RX_LEN_1024_TO_1522 0x3e4
++#define BGMAC_RX_LEN_1523_TO_2047 0x3e8
++#define BGMAC_RX_LEN_2048_TO_4095 0x3ec
++#define BGMAC_RX_LEN_4095_TO_8191 0x3f0
++#define BGMAC_RX_LEN_8192_TO_MAX 0x3f4
++#define BGMAC_RX_JABBER_PKTS 0x3f8 /* Error */
++#define BGMAC_RX_OVERSIZE_PKTS 0x3fc /* Error */
++#define BGMAC_RX_FRAGMENT_PKTS 0x400
++#define BGMAC_RX_MISSED_PKTS 0x404 /* Error */
++#define BGMAC_RX_CRC_ALIGN_ERRS 0x408 /* Error */
++#define BGMAC_RX_UNDERSIZE 0x40c /* Error */
++#define BGMAC_RX_CRC_ERRS 0x410 /* Error */
++#define BGMAC_RX_ALIGN_ERRS 0x414 /* Error */
++#define BGMAC_RX_SYMBOL_ERRS 0x418 /* Error */
++#define BGMAC_RX_PAUSE_PKTS 0x41c
++#define BGMAC_RX_NONPAUSE_PKTS 0x420
++#define BGMAC_RX_SACHANGES 0x424
++#define BGMAC_RX_UNI_PKTS 0x428
++#define BGMAC_UNIMAC_VERSION 0x800
++#define BGMAC_HDBKP_CTL 0x804
++#define BGMAC_CMDCFG 0x808 /* Configuration */
++#define BGMAC_CMDCFG_TE 0x00000001 /* Set to activate TX */
++#define BGMAC_CMDCFG_RE 0x00000002 /* Set to activate RX */
++#define BGMAC_CMDCFG_ES_MASK 0x0000000c /* Ethernet speed see gmac_speed */
++#define BGMAC_CMDCFG_ES_10 0x00000000
++#define BGMAC_CMDCFG_ES_100 0x00000004
++#define BGMAC_CMDCFG_ES_1000 0x00000008
++#define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
++#define BGMAC_CMDCFG_PAD_EN 0x00000020
++#define BGMAC_CMDCFG_CF 0x00000040
++#define BGMAC_CMDCFG_PF 0x00000080
++#define BGMAC_CMDCFG_RPI 0x00000100 /* Unset to enable 802.3x tx flow control */
++#define BGMAC_CMDCFG_TAI 0x00000200
++#define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
++#define BGMAC_CMDCFG_HD_SHIFT 10
++#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
++#define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
++#define BGMAC_CMDCFG_AE 0x00400000
++#define BGMAC_CMDCFG_CFE 0x00800000
++#define BGMAC_CMDCFG_NLC 0x01000000
++#define BGMAC_CMDCFG_RL 0x02000000
++#define BGMAC_CMDCFG_RED 0x04000000
++#define BGMAC_CMDCFG_PE 0x08000000
++#define BGMAC_CMDCFG_TPI 0x10000000
++#define BGMAC_CMDCFG_AT 0x20000000
++#define BGMAC_MACADDR_HIGH 0x80c /* High 4 octets of own mac address */
++#define BGMAC_MACADDR_LOW 0x810 /* Low 2 octets of own mac address */
++#define BGMAC_RXMAX_LENGTH 0x814 /* Max receive frame length with vlan tag */
++#define BGMAC_PAUSEQUANTA 0x818
++#define BGMAC_MAC_MODE 0x844
++#define BGMAC_OUTERTAG 0x848
++#define BGMAC_INNERTAG 0x84c
++#define BGMAC_TXIPG 0x85c
++#define BGMAC_PAUSE_CTL 0xb30
++#define BGMAC_TX_FLUSH 0xb34
++#define BGMAC_RX_STATUS 0xb38
++#define BGMAC_TX_STATUS 0xb3c
++
++#define BGMAC_PHY_CTL 0x00
++#define BGMAC_PHY_CTL_SPEED_MSB 0x0040
++#define BGMAC_PHY_CTL_DUPLEX 0x0100 /* duplex mode */
++#define BGMAC_PHY_CTL_RESTART 0x0200 /* restart autonegotiation */
++#define BGMAC_PHY_CTL_ANENAB 0x1000 /* enable autonegotiation */
++#define BGMAC_PHY_CTL_SPEED 0x2000
++#define BGMAC_PHY_CTL_LOOP 0x4000 /* loopback */
++#define BGMAC_PHY_CTL_RESET 0x8000 /* reset */
++/* Helpers */
++#define BGMAC_PHY_CTL_SPEED_10 0
++#define BGMAC_PHY_CTL_SPEED_100 BGMAC_PHY_CTL_SPEED
++#define BGMAC_PHY_CTL_SPEED_1000 BGMAC_PHY_CTL_SPEED_MSB
++#define BGMAC_PHY_ADV 0x04
++#define BGMAC_PHY_ADV_10HALF 0x0020 /* advertise 10MBits/s half duplex */
++#define BGMAC_PHY_ADV_10FULL 0x0040 /* advertise 10MBits/s full duplex */
++#define BGMAC_PHY_ADV_100HALF 0x0080 /* advertise 100MBits/s half duplex */
++#define BGMAC_PHY_ADV_100FULL 0x0100 /* advertise 100MBits/s full duplex */
++#define BGMAC_PHY_ADV2 0x09
++#define BGMAC_PHY_ADV2_1000HALF 0x0100 /* advertise 1000MBits/s half duplex */
++#define BGMAC_PHY_ADV2_1000FULL 0x0200 /* advertise 1000MBits/s full duplex */
++
++/* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
++#define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */
++#define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */
++
++/* BCMA GMAC core specific IO status (BCMA_IOST) flags */
++#define BGMAC_BCMA_IOST_ATTACHED 0x00000800
++
++#define BGMAC_NUM_MIB_TX_REGS \
++ (((BGMAC_TX_Q3_OCTETS_HIGH - BGMAC_TX_GOOD_OCTETS) / 4) + 1)
++#define BGMAC_NUM_MIB_RX_REGS \
++ (((BGMAC_RX_UNI_PKTS - BGMAC_RX_GOOD_OCTETS) / 4) + 1)
++
++#define BGMAC_DMA_TX_CTL 0x00
++#define BGMAC_DMA_TX_ENABLE 0x00000001
++#define BGMAC_DMA_TX_SUSPEND 0x00000002
++#define BGMAC_DMA_TX_LOOPBACK 0x00000004
++#define BGMAC_DMA_TX_FLUSH 0x00000010
++#define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
++#define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
++#define BGMAC_DMA_TX_ADDREXT_SHIFT 16
++#define BGMAC_DMA_TX_INDEX 0x04
++#define BGMAC_DMA_TX_RINGLO 0x08
++#define BGMAC_DMA_TX_RINGHI 0x0C
++#define BGMAC_DMA_TX_STATUS 0x10
++#define BGMAC_DMA_TX_STATDPTR 0x00001FFF
++#define BGMAC_DMA_TX_STAT 0xF0000000
++#define BGMAC_DMA_TX_STAT_DISABLED 0x00000000
++#define BGMAC_DMA_TX_STAT_ACTIVE 0x10000000
++#define BGMAC_DMA_TX_STAT_IDLEWAIT 0x20000000
++#define BGMAC_DMA_TX_STAT_STOPPED 0x30000000
++#define BGMAC_DMA_TX_STAT_SUSP 0x40000000
++#define BGMAC_DMA_TX_ERROR 0x14
++#define BGMAC_DMA_TX_ERRDPTR 0x0001FFFF
++#define BGMAC_DMA_TX_ERR 0xF0000000
++#define BGMAC_DMA_TX_ERR_NOERR 0x00000000
++#define BGMAC_DMA_TX_ERR_PROT 0x10000000
++#define BGMAC_DMA_TX_ERR_UNDERRUN 0x20000000
++#define BGMAC_DMA_TX_ERR_TRANSFER 0x30000000
++#define BGMAC_DMA_TX_ERR_DESCREAD 0x40000000
++#define BGMAC_DMA_TX_ERR_CORE 0x50000000
++#define BGMAC_DMA_RX_CTL 0x20
++#define BGMAC_DMA_RX_ENABLE 0x00000001
++#define BGMAC_DMA_RX_FRAME_OFFSET_MASK 0x000000FE
++#define BGMAC_DMA_RX_FRAME_OFFSET_SHIFT 1
++#define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
++#define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
++#define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
++#define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
++#define BGMAC_DMA_RX_ADDREXT_SHIFT 16
++#define BGMAC_DMA_RX_INDEX 0x24
++#define BGMAC_DMA_RX_RINGLO 0x28
++#define BGMAC_DMA_RX_RINGHI 0x2C
++#define BGMAC_DMA_RX_STATUS 0x30
++#define BGMAC_DMA_RX_STATDPTR 0x00001FFF
++#define BGMAC_DMA_RX_STAT 0xF0000000
++#define BGMAC_DMA_RX_STAT_DISABLED 0x00000000
++#define BGMAC_DMA_RX_STAT_ACTIVE 0x10000000
++#define BGMAC_DMA_RX_STAT_IDLEWAIT 0x20000000
++#define BGMAC_DMA_RX_STAT_STOPPED 0x30000000
++#define BGMAC_DMA_RX_STAT_SUSP 0x40000000
++#define BGMAC_DMA_RX_ERROR 0x34
++#define BGMAC_DMA_RX_ERRDPTR 0x0001FFFF
++#define BGMAC_DMA_RX_ERR 0xF0000000
++#define BGMAC_DMA_RX_ERR_NOERR 0x00000000
++#define BGMAC_DMA_RX_ERR_PROT 0x10000000
++#define BGMAC_DMA_RX_ERR_UNDERRUN 0x20000000
++#define BGMAC_DMA_RX_ERR_TRANSFER 0x30000000
++#define BGMAC_DMA_RX_ERR_DESCREAD 0x40000000
++#define BGMAC_DMA_RX_ERR_CORE 0x50000000
++
++#define BGMAC_DESC_CTL0_EOT 0x10000000 /* End of ring */
++#define BGMAC_DESC_CTL0_IOC 0x20000000 /* IRQ on complete */
++#define BGMAC_DESC_CTL0_SOF 0x40000000 /* Start of frame */
++#define BGMAC_DESC_CTL0_EOF 0x80000000 /* End of frame */
++#define BGMAC_DESC_CTL1_LEN 0x00001FFF
++
++#define BGMAC_PHY_NOREGS 0x1E
++#define BGMAC_PHY_MASK 0x1F
++
++#define BGMAC_MAX_TX_RINGS 4
++#define BGMAC_MAX_RX_RINGS 1
++
++#define BGMAC_TX_RING_SLOTS 128
++#define BGMAC_RX_RING_SLOTS 512 - 1 /* Why -1? Well, Broadcom does that... */
++
++#define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */
++#define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */
++#define BGMAC_RX_MAX_FRAME_SIZE 1536 /* Copied from b44/tg3 */
++#define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE)
++
++#define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */
++#define BGMAC_BFL_ENETADM 0x0080 /* has ADMtek switch */
++#define BGMAC_BFL_ENETVLAN 0x0100 /* can do vlan */
++
++#define BGMAC_CHIPCTL_1_IF_TYPE_MASK 0x00000030
++#define BGMAC_CHIPCTL_1_IF_TYPE_RMII 0x00000000
++#define BGMAC_CHIPCTL_1_IF_TYPE_MI 0x00000010
++#define BGMAC_CHIPCTL_1_IF_TYPE_RGMII 0x00000020
++#define BGMAC_CHIPCTL_1_SW_TYPE_MASK 0x000000C0
++#define BGMAC_CHIPCTL_1_SW_TYPE_EPHY 0x00000000
++#define BGMAC_CHIPCTL_1_SW_TYPE_EPHYMII 0x00000040
++#define BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII 0x00000080
++#define BGMAC_CHIPCTL_1_SW_TYPE_RGMI 0x000000C0
++#define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000
++
++#define BGMAC_SPEED_10 0x0001
++#define BGMAC_SPEED_100 0x0002
++#define BGMAC_SPEED_1000 0x0004
++
++#define BGMAC_WEIGHT 64
++
++#define ETHER_MAX_LEN 1518
++
++struct bgmac_slot_info {
++ struct sk_buff *skb;
++ dma_addr_t dma_addr;
++};
++
++struct bgmac_dma_desc {
++ __le32 ctl0;
++ __le32 ctl1;
++ __le32 addr_low;
++ __le32 addr_high;
++} __packed;
++
++enum bgmac_dma_ring_type {
++ BGMAC_DMA_RING_TX,
++ BGMAC_DMA_RING_RX,
++};
++
++/**
++ * bgmac_dma_ring - contains info about DMA ring (either TX or RX one)
++ * @start: index of the first slot containing data
++ * @end: index of a slot that can *not* be read (yet)
++ *
++ * Be really aware of the specific @end meaning. It's an index of a slot *after*
++ * the one containing data that can be read. If @start equals @end the ring is
++ * empty.
++ */
++struct bgmac_dma_ring {
++ u16 num_slots;
++ u16 start;
++ u16 end;
++
++ u16 mmio_base;
++ struct bgmac_dma_desc *cpu_base;
++ dma_addr_t dma_base;
++
++ struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS];
++};
++
++struct bgmac_rx_header {
++ __le16 len;
++ __le16 flags;
++ __le16 pad[12];
++};
++
++struct bgmac {
++ struct bcma_device *core;
++ struct bcma_device *cmn; /* Reference to CMN core for BCM4706 */
++ struct net_device *net_dev;
++ struct napi_struct napi;
++
++ /* DMA */
++ struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS];
++ struct bgmac_dma_ring rx_ring[BGMAC_MAX_RX_RINGS];
++
++ /* Stats */
++ bool stats_grabbed;
++ u32 mib_tx_regs[BGMAC_NUM_MIB_TX_REGS];
++ u32 mib_rx_regs[BGMAC_NUM_MIB_RX_REGS];
++
++ /* Int */
++ u32 int_mask;
++ u32 int_status;
++
++ /* Speed-related */
++ int speed;
++ bool autoneg;
++ bool full_duplex;
++
++ u8 phyaddr;
++ bool has_robosw;
++
++ bool loopback;
++};
++
++static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset)
++{
++ return bcma_read32(bgmac->core, offset);
++}
++
++static inline void bgmac_write(struct bgmac *bgmac, u16 offset, u32 value)
++{
++ bcma_write32(bgmac->core, offset, value);
++}
++
++static inline void bgmac_maskset(struct bgmac *bgmac, u16 offset, u32 mask,
++ u32 set)
++{
++ bgmac_write(bgmac, offset, (bgmac_read(bgmac, offset) & mask) | set);
++}
++
++static inline void bgmac_mask(struct bgmac *bgmac, u16 offset, u32 mask)
++{
++ bgmac_maskset(bgmac, offset, mask, 0);
++}
++
++static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set)
++{
++ bgmac_maskset(bgmac, offset, ~0, set);
++}
++
++u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg);
++void bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value);
++
++#endif /* _BGMAC_H */
+--- a/include/linux/bcma/bcma_driver_chipcommon.h
++++ b/include/linux/bcma/bcma_driver_chipcommon.h
+@@ -623,4 +623,6 @@ extern void bcma_chipco_regctl_maskset(s
+ u32 offset, u32 mask, u32 set);
+ extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
+
++extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
++
+ #endif /* LINUX_BCMA_DRIVER_CC_H_ */
--- /dev/null
+--- a/drivers/net/ethernet/broadcom/bgmac.c
++++ b/drivers/net/ethernet/broadcom/bgmac.c
+@@ -301,7 +301,7 @@ static int bgmac_dma_rx_read(struct bgma
+ bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
+ ring->start);
+ } else {
+- new_skb = netdev_alloc_skb(bgmac->net_dev, len);
++ new_skb = netdev_alloc_skb_ip_align(bgmac->net_dev, len);
+ if (new_skb) {
+ skb_put(new_skb, len);
+ skb_copy_from_linear_data_offset(skb, BGMAC_RX_FRAME_OFFSET,
+@@ -535,7 +535,7 @@ static void bgmac_dma_init(struct bgmac
+ * PHY ops
+ **************************************************/
+
+-u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
++static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
+ {
+ struct bcma_device *core;
+ u16 phy_access_addr;
+@@ -584,7 +584,7 @@ u16 bgmac_phy_read(struct bgmac *bgmac,
+ }
+
+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
+-void bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
++static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
+ {
+ struct bcma_device *core;
+ u16 phy_access_addr;
+@@ -617,9 +617,13 @@ void bgmac_phy_write(struct bgmac *bgmac
+ tmp |= value;
+ bcma_write32(core, phy_access_addr, tmp);
+
+- if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000))
++ if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
+ bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
+ phyaddr, reg);
++ return -ETIMEDOUT;
++ }
++
++ return 0;
+ }
+
+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyforce */
+@@ -761,6 +765,26 @@ static void bgmac_cmdcfg_maskset(struct
+ udelay(2);
+ }
+
++static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
++{
++ u32 tmp;
++
++ tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
++ bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
++ tmp = (addr[4] << 8) | addr[5];
++ bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
++}
++
++static void bgmac_set_rx_mode(struct net_device *net_dev)
++{
++ struct bgmac *bgmac = netdev_priv(net_dev);
++
++ if (net_dev->flags & IFF_PROMISC)
++ bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
++ else
++ bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
++}
++
+ #if 0 /* We don't use that regs yet */
+ static void bgmac_chip_stats_update(struct bgmac *bgmac)
+ {
+@@ -889,8 +913,10 @@ static void bgmac_chip_reset(struct bgma
+ sw_type = et_swtype;
+ } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
+ sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
+- } else if (0) {
+- /* TODO */
++ } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
++ (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
++ sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
++ BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
+ }
+ bcma_chipco_chipctl_maskset(cc, 1,
+ ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
+@@ -948,6 +974,7 @@ static void bgmac_chip_intrs_on(struct b
+ static void bgmac_chip_intrs_off(struct bgmac *bgmac)
+ {
+ bgmac_write(bgmac, BGMAC_INT_MASK, 0);
++ bgmac_read(bgmac, BGMAC_INT_MASK);
+ }
+
+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
+@@ -1004,8 +1031,6 @@ static void bgmac_enable(struct bgmac *b
+ static void bgmac_chip_init(struct bgmac *bgmac, bool full_init)
+ {
+ struct bgmac_dma_ring *ring;
+- u8 *mac = bgmac->net_dev->dev_addr;
+- u32 tmp;
+ int i;
+
+ /* 1 interrupt per received frame */
+@@ -1014,21 +1039,14 @@ static void bgmac_chip_init(struct bgmac
+ /* Enable 802.3x tx flow control (honor received PAUSE frames) */
+ bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
+
+- if (bgmac->net_dev->flags & IFF_PROMISC)
+- bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, false);
+- else
+- bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, false);
++ bgmac_set_rx_mode(bgmac->net_dev);
+
+- /* Set MAC addr */
+- tmp = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+- bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
+- tmp = (mac[4] << 8) | mac[5];
+- bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
++ bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
+
+ if (bgmac->loopback)
+- bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, true);
++ bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
+ else
+- bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, true);
++ bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
+
+ bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
+
+@@ -1160,6 +1178,19 @@ static netdev_tx_t bgmac_start_xmit(stru
+ return bgmac_dma_tx_add(bgmac, ring, skb);
+ }
+
++static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
++{
++ struct bgmac *bgmac = netdev_priv(net_dev);
++ int ret;
++
++ ret = eth_prepare_mac_addr_change(net_dev, addr);
++ if (ret < 0)
++ return ret;
++ bgmac_write_mac_address(bgmac, (u8 *)addr);
++ eth_commit_mac_addr_change(net_dev, addr);
++ return 0;
++}
++
+ static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
+ {
+ struct bgmac *bgmac = netdev_priv(net_dev);
+@@ -1190,7 +1221,9 @@ static const struct net_device_ops bgmac
+ .ndo_open = bgmac_open,
+ .ndo_stop = bgmac_stop,
+ .ndo_start_xmit = bgmac_start_xmit,
+- .ndo_set_mac_address = eth_mac_addr, /* generic, sets dev_addr */
++ .ndo_set_rx_mode = bgmac_set_rx_mode,
++ .ndo_set_mac_address = bgmac_set_mac_address,
++ .ndo_validate_addr = eth_validate_addr,
+ .ndo_do_ioctl = bgmac_ioctl,
+ };
+
+@@ -1290,6 +1323,12 @@ static int bgmac_probe(struct bcma_devic
+ return -ENOTSUPP;
+ }
+
++ if (!is_valid_ether_addr(mac)) {
++ dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
++ eth_random_addr(mac);
++ dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
++ }
++
+ /* Allocation and references */
+ net_dev = alloc_etherdev(sizeof(*bgmac));
+ if (!net_dev)
+--- a/drivers/net/ethernet/broadcom/bgmac.h
++++ b/drivers/net/ethernet/broadcom/bgmac.h
+@@ -339,7 +339,7 @@
+ #define BGMAC_CHIPCTL_1_SW_TYPE_EPHY 0x00000000
+ #define BGMAC_CHIPCTL_1_SW_TYPE_EPHYMII 0x00000040
+ #define BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII 0x00000080
+-#define BGMAC_CHIPCTL_1_SW_TYPE_RGMI 0x000000C0
++#define BGMAC_CHIPCTL_1_SW_TYPE_RGMII 0x000000C0
+ #define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000
+
+ #define BGMAC_SPEED_10 0x0001
+@@ -450,7 +450,4 @@ static inline void bgmac_set(struct bgma
+ bgmac_maskset(bgmac, offset, ~0, set);
+ }
+
+-u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg);
+-void bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value);
+-
+ #endif /* _BGMAC_H */
--- /dev/null
+--- a/arch/mips/bcm47xx/Makefile
++++ b/arch/mips/bcm47xx/Makefile
+@@ -6,4 +6,3 @@
+ obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
+ obj-y += board.o
+ obj-y += gpio.o
+-obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
+--- a/arch/mips/bcm47xx/wgt634u.c
++++ /dev/null
+@@ -1,174 +0,0 @@
+-/*
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License. See the file "COPYING" in the main directory of this archive
+- * for more details.
+- *
+- * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
+- */
+-
+-#include <linux/platform_device.h>
+-#include <linux/module.h>
+-#include <linux/leds.h>
+-#include <linux/mtd/physmap.h>
+-#include <linux/ssb/ssb.h>
+-#include <linux/ssb/ssb_embedded.h>
+-#include <linux/interrupt.h>
+-#include <linux/reboot.h>
+-#include <linux/gpio.h>
+-#include <asm/mach-bcm47xx/bcm47xx.h>
+-
+-/* GPIO definitions for the WGT634U */
+-#define WGT634U_GPIO_LED 3
+-#define WGT634U_GPIO_RESET 2
+-#define WGT634U_GPIO_TP1 7
+-#define WGT634U_GPIO_TP2 6
+-#define WGT634U_GPIO_TP3 5
+-#define WGT634U_GPIO_TP4 4
+-#define WGT634U_GPIO_TP5 1
+-
+-static struct gpio_led wgt634u_leds[] = {
+- {
+- .name = "power",
+- .gpio = WGT634U_GPIO_LED,
+- .active_low = 1,
+- .default_trigger = "heartbeat",
+- },
+-};
+-
+-static struct gpio_led_platform_data wgt634u_led_data = {
+- .num_leds = ARRAY_SIZE(wgt634u_leds),
+- .leds = wgt634u_leds,
+-};
+-
+-static struct platform_device wgt634u_gpio_leds = {
+- .name = "leds-gpio",
+- .id = -1,
+- .dev = {
+- .platform_data = &wgt634u_led_data,
+- }
+-};
+-
+-
+-/* 8MiB flash. The struct mtd_partition matches original Netgear WGT634U
+- firmware. */
+-static struct mtd_partition wgt634u_partitions[] = {
+- {
+- .name = "cfe",
+- .offset = 0,
+- .size = 0x60000, /* 384k */
+- .mask_flags = MTD_WRITEABLE /* force read-only */
+- },
+- {
+- .name = "config",
+- .offset = 0x60000,
+- .size = 0x20000 /* 128k */
+- },
+- {
+- .name = "linux",
+- .offset = 0x80000,
+- .size = 0x140000 /* 1280k */
+- },
+- {
+- .name = "jffs",
+- .offset = 0x1c0000,
+- .size = 0x620000 /* 6272k */
+- },
+- {
+- .name = "nvram",
+- .offset = 0x7e0000,
+- .size = 0x20000 /* 128k */
+- },
+-};
+-
+-static struct physmap_flash_data wgt634u_flash_data = {
+- .parts = wgt634u_partitions,
+- .nr_parts = ARRAY_SIZE(wgt634u_partitions)
+-};
+-
+-static struct resource wgt634u_flash_resource = {
+- .flags = IORESOURCE_MEM,
+-};
+-
+-static struct platform_device wgt634u_flash = {
+- .name = "physmap-flash",
+- .id = 0,
+- .dev = { .platform_data = &wgt634u_flash_data, },
+- .resource = &wgt634u_flash_resource,
+- .num_resources = 1,
+-};
+-
+-/* Platform devices */
+-static struct platform_device *wgt634u_devices[] __initdata = {
+- &wgt634u_flash,
+- &wgt634u_gpio_leds,
+-};
+-
+-static irqreturn_t gpio_interrupt(int irq, void *ignored)
+-{
+- int state;
+-
+- /* Interrupts are shared, check if the current one is
+- a GPIO interrupt. */
+- if (!ssb_chipco_irq_status(&bcm47xx_bus.ssb.chipco,
+- SSB_CHIPCO_IRQ_GPIO))
+- return IRQ_NONE;
+-
+- state = gpio_get_value(WGT634U_GPIO_RESET);
+-
+- /* Interrupt are level triggered, revert the interrupt polarity
+- to clear the interrupt. */
+- ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << WGT634U_GPIO_RESET,
+- state ? 1 << WGT634U_GPIO_RESET : 0);
+-
+- if (!state) {
+- printk(KERN_INFO "Reset button pressed");
+- ctrl_alt_del();
+- }
+-
+- return IRQ_HANDLED;
+-}
+-
+-static int __init wgt634u_init(void)
+-{
+- /* There is no easy way to detect that we are running on a WGT634U
+- * machine. Use the MAC address as an heuristic. Netgear Inc. has
+- * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
+- */
+- u8 *et0mac;
+-
+- if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB)
+- return -ENODEV;
+-
+- et0mac = bcm47xx_bus.ssb.sprom.et0mac;
+-
+- if (et0mac[0] == 0x00 &&
+- ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
+- (et0mac[1] == 0x0f && et0mac[2] == 0xb5))) {
+- struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore;
+-
+- printk(KERN_INFO "WGT634U machine detected.\n");
+-
+- if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET),
+- gpio_interrupt, IRQF_SHARED,
+- "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) {
+- gpio_direction_input(WGT634U_GPIO_RESET);
+- ssb_gpio_intmask(&bcm47xx_bus.ssb,
+- 1 << WGT634U_GPIO_RESET,
+- 1 << WGT634U_GPIO_RESET);
+- ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco,
+- SSB_CHIPCO_IRQ_GPIO,
+- SSB_CHIPCO_IRQ_GPIO);
+- }
+-
+- wgt634u_flash_data.width = mcore->pflash.buswidth;
+- wgt634u_flash_resource.start = mcore->pflash.window;
+- wgt634u_flash_resource.end = mcore->pflash.window
+- + mcore->pflash.window_size
+- - 1;
+- return platform_add_devices(wgt634u_devices,
+- ARRAY_SIZE(wgt634u_devices));
+- } else
+- return -ENODEV;
+-}
+-
+-module_init(wgt634u_init);
--- /dev/null
+The Netgear wgt634u uses a different format for storing the
+configuration. This patch is needed to read out the correct
+configuration. The cfe_env.c file uses a different method way to read
+out the configuration than the in kernel cfe config reader.
+
+--- a/arch/mips/bcm47xx/Makefile
++++ b/arch/mips/bcm47xx/Makefile
+@@ -6,3 +6,4 @@
+ obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
+ obj-y += board.o
+ obj-y += gpio.o
++obj-y += cfe_env.o
+--- /dev/null
++++ b/arch/mips/bcm47xx/cfe_env.c
+@@ -0,0 +1,229 @@
++/*
++ * CFE environment variable access
++ *
++ * Copyright 2001-2003, Broadcom Corporation
++ * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#define NVRAM_SIZE (0x1ff0)
++static char _nvdata[NVRAM_SIZE];
++static char _valuestr[256];
++
++/*
++ * TLV types. These codes are used in the "type-length-value"
++ * encoding of the items stored in the NVRAM device (flash or EEPROM)
++ *
++ * The layout of the flash/nvram is as follows:
++ *
++ * <type> <length> <data ...> <type> <length> <data ...> <type_end>
++ *
++ * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
++ * The "length" field marks the length of the data section, not
++ * including the type and length fields.
++ *
++ * Environment variables are stored as follows:
++ *
++ * <type_env> <length> <flags> <name> = <value>
++ *
++ * If bit 0 (low bit) is set, the length is an 8-bit value.
++ * If bit 0 (low bit) is clear, the length is a 16-bit value
++ *
++ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
++ * indicates the size of the length field.
++ *
++ * Flags are from the constants below:
++ *
++ */
++#define ENV_LENGTH_16BITS 0x00 /* for low bit */
++#define ENV_LENGTH_8BITS 0x01
++
++#define ENV_TYPE_USER 0x80
++
++#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
++#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
++
++/*
++ * The actual TLV types we support
++ */
++
++#define ENV_TLV_TYPE_END 0x00
++#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
++
++/*
++ * Environment variable flags
++ */
++
++#define ENV_FLG_NORMAL 0x00 /* normal read/write */
++#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
++#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
++
++#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
++#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
++
++
++/* *********************************************************************
++ * _nvram_read(buffer,offset,length)
++ *
++ * Read data from the NVRAM device
++ *
++ * Input parameters:
++ * buffer - destination buffer
++ * offset - offset of data to read
++ * length - number of bytes to read
++ *
++ * Return value:
++ * number of bytes read, or <0 if error occured
++ ********************************************************************* */
++static int
++_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
++{
++ int i;
++ if (offset > NVRAM_SIZE)
++ return -1;
++
++ for ( i = 0; i < length; i++) {
++ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
++ }
++ return length;
++}
++
++
++static char*
++_strnchr(const char *dest,int c,size_t cnt)
++{
++ while (*dest && (cnt > 0)) {
++ if (*dest == c) return (char *) dest;
++ dest++;
++ cnt--;
++ }
++ return NULL;
++}
++
++
++
++/*
++ * Core support API: Externally visible.
++ */
++
++/*
++ * Get the value of an NVRAM variable
++ * @param name name of variable to get
++ * @return value of variable or NULL if undefined
++ */
++
++char*
++cfe_env_get(unsigned char *nv_buf, char* name)
++{
++ int size;
++ unsigned char *buffer;
++ unsigned char *ptr;
++ unsigned char *envval;
++ unsigned int reclen;
++ unsigned int rectype;
++ int offset;
++ int flg;
++
++ if (!strcmp(name, "nvram_type"))
++ return "cfe";
++
++ size = NVRAM_SIZE;
++ buffer = &_nvdata[0];
++
++ ptr = buffer;
++ offset = 0;
++
++ /* Read the record type and length */
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
++ goto error;
++ }
++
++ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
++
++ /* Adjust pointer for TLV type */
++ rectype = *(ptr);
++ offset++;
++ size--;
++
++ /*
++ * Read the length. It can be either 1 or 2 bytes
++ * depending on the code
++ */
++ if (rectype & ENV_LENGTH_8BITS) {
++ /* Read the record type and length - 8 bits */
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
++ goto error;
++ }
++ reclen = *(ptr);
++ size--;
++ offset++;
++ }
++ else {
++ /* Read the record type and length - 16 bits, MSB first */
++ if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
++ goto error;
++ }
++ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
++ size -= 2;
++ offset += 2;
++ }
++
++ if (reclen > size)
++ break; /* should not happen, bad NVRAM */
++
++ switch (rectype) {
++ case ENV_TLV_TYPE_ENV:
++ /* Read the TLV data */
++ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
++ goto error;
++ flg = *ptr++;
++ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
++ if (envval) {
++ *envval++ = '\0';
++ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
++ _valuestr[(reclen-1)-(envval-ptr)] = '\0';
++#if 0
++ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
++#endif
++ if(!strcmp(ptr, name)){
++ return _valuestr;
++ }
++ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
++ return _valuestr;
++ }
++ break;
++
++ default:
++ /* Unknown TLV type, skip it. */
++ break;
++ }
++
++ /*
++ * Advance to next TLV
++ */
++
++ size -= (int)reclen;
++ offset += reclen;
++
++ /* Read the next record type */
++ ptr = buffer;
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1)
++ goto error;
++ }
++
++error:
++ return NULL;
++
++}
++
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -22,6 +22,8 @@
+ #include <asm/mach-bcm47xx/bcm47xx.h>
+
+ static char nvram_buf[NVRAM_SPACE];
++static int cfe_env;
++extern char *cfe_env_get(char *nv_buf, const char *name);
+
+ static u32 find_nvram_size(u32 end)
+ {
+@@ -47,6 +49,26 @@ static int nvram_find_and_copy(u32 base,
+ u32 *src, *dst;
+ u32 size;
+
++ cfe_env = 0;
++
++ /* XXX: hack for supporting the CFE environment stuff on WGT634U */
++ if (lim >= 8 * 1024 * 1024) {
++ src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
++ dst = (u32 *) nvram_buf;
++
++ if ((*src & 0xff00ff) == 0x000001) {
++ printk("early_nvram_init: WGT634U NVRAM found.\n");
++
++ for (i = 0; i < 0x1ff0; i++) {
++ if (*src == 0xFFFFFFFF)
++ break;
++ *dst++ = *src++;
++ }
++ cfe_env = 1;
++ return 0;
++ }
++ }
++
+ /* TODO: when nvram is on nand flash check for bad blocks first. */
+ off = FLASH_MIN;
+ while (off <= lim) {
+@@ -181,6 +203,13 @@ int bcm47xx_nvram_getenv(char *name, cha
+ return err;
+ }
+
++ if (cfe_env) {
++ value = cfe_env_get(nvram_buf, name);
++ if (!value)
++ return -ENOENT;
++ return snprintf(val, val_len, "%s", value);
++ }
++
+ /* Look for name=value and return value */
+ var = &nvram_buf[sizeof(struct nvram_header)];
+ end = nvram_buf + sizeof(nvram_buf) - 2;
+@@ -209,6 +238,9 @@ char *nvram_get(const char *name)
+ if (!nvram_buf[0])
+ nvram_init();
+
++ if (cfe_env)
++ return cfe_env_get(nvram_buf, name);
++
+ /* Look for name=value and return value */
+ var = &nvram_buf[sizeof(struct nvram_header)];
+ end = nvram_buf + sizeof(nvram_buf) - 2;
--- /dev/null
+--- a/arch/mips/include/asm/r4kcache.h
++++ b/arch/mips/include/asm/r4kcache.h
+@@ -20,10 +20,28 @@
+ #ifdef CONFIG_BCM47XX
+ #include <asm/paccess.h>
+ #include <linux/ssb/ssb.h>
+-#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
++#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
++
++static inline unsigned long bcm4710_dummy_rreg(void)
++{
++ return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
++}
++
++#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
++
++static inline unsigned long bcm4710_fill_tlb(void *addr)
++{
++ return *(unsigned long *)addr;
++}
++
++#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
++
++static inline void bcm4710_protected_fill_tlb(void *addr)
++{
++ unsigned long x;
++ get_dbe(x, (unsigned long *)addr);;
++}
+
+-#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
+-#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
+ #else
+ #define BCM4710_DUMMY_RREG()
+
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -972,6 +972,9 @@ build_get_pgde32(u32 **p, unsigned int t
+ #endif
+ uasm_i_addu(p, ptr, tmp, ptr);
+ #else
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++#endif
+ UASM_i_LA_mostly(p, ptr, pgdc);
+ #endif
+ uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
+@@ -1314,12 +1317,12 @@ static void __cpuinit build_r4000_tlb_re
+ /* No need for uasm_i_nop */
+ }
+
+-#ifdef CONFIG_BCM47XX
+- uasm_i_nop(&p);
+-#endif
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
+ #else
++# ifdef CONFIG_BCM47XX
++ uasm_i_nop(&p);
++# endif
+ build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
+ #endif
+
+@@ -1331,6 +1334,9 @@ static void __cpuinit build_r4000_tlb_re
+ build_update_entries(&p, K0, K1);
+ build_tlb_write_entry(&p, &l, &r, tlb_random);
+ uasm_l_leave(&l, p);
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(&p);
++#endif
+ uasm_i_eret(&p); /* return from trap */
+ }
+ #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+@@ -1848,12 +1854,12 @@ build_r4000_tlbchange_handler_head(u32 *
+ {
+ struct work_registers wr = build_get_work_registers(p);
+
+-#ifdef CONFIG_BCM47XX
+- uasm_i_nop(p);
+-#endif
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
+ #else
++# ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++# endif
+ build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
+ #endif
+
+@@ -1892,6 +1898,9 @@ build_r4000_tlbchange_handler_tail(u32 *
+ build_tlb_write_entry(p, l, r, tlb_indexed);
+ uasm_l_leave(l, *p);
+ build_restore_work_registers(p);
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++#endif
+ uasm_i_eret(p); /* return from trap */
+
+ #ifdef CONFIG_64BIT
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
+@@ -21,6 +21,19 @@
+ #include <asm/war.h>
+ #include <asm/thread_info.h>
+
++#ifdef CONFIG_BCM47XX
++# ifdef eret
++# undef eret
++# endif
++# define eret \
++ .set push; \
++ .set noreorder; \
++ nop; \
++ nop; \
++ eret; \
++ .set pop;
++#endif
++
+ #define PANIC_PIC(msg) \
+ .set push; \
+ .set reorder; \
+@@ -53,7 +66,6 @@ NESTED(except_vec3_generic, 0, sp)
+ .set noat
+ #ifdef CONFIG_BCM47XX
+ nop
+- nop
+ #endif
+ #if R5432_CP0_INTERRUPT_WAR
+ mfc0 k0, CP0_INDEX
+@@ -78,6 +90,9 @@ NESTED(except_vec3_r4000, 0, sp)
+ .set push
+ .set mips3
+ .set noat
++#ifdef CONFIG_BCM47XX
++ nop
++#endif
+ mfc0 k1, CP0_CAUSE
+ li k0, 31<<2
+ andi k1, k1, 0x7c
--- /dev/null
+--- a/drivers/pcmcia/yenta_socket.c
++++ b/drivers/pcmcia/yenta_socket.c
+@@ -920,6 +920,8 @@ static unsigned int yenta_probe_irq(stru
+ * Probe for usable interrupts using the force
+ * register to generate bogus card status events.
+ */
++#ifndef CONFIG_BCM47XX
++ /* WRT54G3G does not like this */
+ cb_writel(socket, CB_SOCKET_EVENT, -1);
+ cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
+ reg = exca_readb(socket, I365_CSCINT);
+@@ -935,6 +937,7 @@ static unsigned int yenta_probe_irq(stru
+ }
+ cb_writel(socket, CB_SOCKET_MASK, 0);
+ exca_writeb(socket, I365_CSCINT, reg);
++#endif
+
+ mask = probe_irq_mask(val) & 0xffff;
+
+@@ -1019,6 +1022,10 @@ static void yenta_get_socket_capabilitie
+ else
+ socket->socket.irq_mask = 0;
+
++ /* irq mask probing is broken for the WRT54G3G */
++ if (socket->socket.irq_mask == 0)
++ socket->socket.irq_mask = 0x6f8;
++
+ dev_printk(KERN_INFO, &socket->dev->dev,
+ "ISA IRQ mask 0x%04x, PCI irq %d\n",
+ socket->socket.irq_mask, socket->cb_irq);
+@@ -1257,6 +1264,15 @@ static int yenta_probe(struct pci_dev *d
+ dev_printk(KERN_INFO, &dev->dev,
+ "Socket status: %08x\n", cb_readl(socket, CB_SOCKET_STATE));
+
++ /* Generate an interrupt on card insert/remove */
++ config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);
++
++ /* Set up Multifunction Routing Status Register */
++ config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);
++
++ /* Switch interrupts to parallelized */
++ config_writeb(socket, 0x92, 0x64);
++
+ yenta_fixup_parent_bridge(dev->subordinate);
+
+ /* Register it with the pcmcia layer.. */
--- /dev/null
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -376,7 +376,7 @@ static void ssb_pcicore_init_hostmode(st
+ set_io_port_base(ssb_pcicore_controller.io_map_base);
+ /* Give some time to the PCI controller to configure itself with the new
+ * values. Not waiting at this point causes crashes of the machine. */
+- mdelay(10);
++ mdelay(300);
+ register_pci_controller(&ssb_pcicore_controller);
+ }
+
--- /dev/null
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -120,6 +120,10 @@ static int bcm47xx_get_invariants(struct
+ if (bcm47xx_nvram_getenv("cardbus", buf, sizeof(buf)) >= 0)
+ iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10);
+
++ /* Do not indicate cardbus for Netgear WNR834B V1 and V2 */
++ if (iv->boardinfo.type == 0x0472 && iv->has_cardbus_slot)
++ iv->has_cardbus_slot = 0;
++
+ return 0;
+ }
+
--- /dev/null
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -21,7 +21,8 @@
+ #include <bcm47xx_nvram.h>
+ #include <asm/mach-bcm47xx/bcm47xx.h>
+
+-static char nvram_buf[NVRAM_SPACE];
++char nvram_buf[NVRAM_SPACE];
++EXPORT_SYMBOL(nvram_buf);
+ static int cfe_env;
+ extern char *cfe_env_get(char *nv_buf, const char *name);
+
+--- a/arch/mips/mm/cache.c
++++ b/arch/mips/mm/cache.c
+@@ -58,6 +58,7 @@ void (*_dma_cache_wback)(unsigned long s
+ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+
+ EXPORT_SYMBOL(_dma_cache_wback_inv);
++EXPORT_SYMBOL(_dma_cache_inv);
+
+ #endif /* CONFIG_DMA_NONCOHERENT */
+
--- /dev/null
+--- a/drivers/ssb/Kconfig
++++ b/drivers/ssb/Kconfig
+@@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS
+
+ If unsure, say N
+
++config SSB_SFLASH
++ bool "SSB serial flash support"
++ depends on SSB_DRIVER_MIPS && BROKEN
++ default y
++
+ # Assumption: We are on embedded, if we compile the MIPS core.
+ config SSB_EMBEDDED
+ bool
+--- a/drivers/ssb/Makefile
++++ b/drivers/ssb/Makefile
+@@ -11,6 +11,7 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
+ # built-in drivers
+ ssb-y += driver_chipcommon.o
+ ssb-y += driver_chipcommon_pmu.o
++ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
+ ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
+ ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
+ ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
+--- /dev/null
++++ b/drivers/ssb/driver_chipcommon_sflash.c
+@@ -0,0 +1,140 @@
++/*
++ * Sonics Silicon Backplane
++ * ChipCommon serial flash interface
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include <linux/ssb/ssb.h>
++
++#include "ssb_private.h"
++
++struct ssb_sflash_tbl_e {
++ char *name;
++ u32 id;
++ u32 blocksize;
++ u16 numblocks;
++};
++
++static struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
++ { "M25P20", 0x11, 0x10000, 4, },
++ { "M25P40", 0x12, 0x10000, 8, },
++
++ { "M25P16", 0x14, 0x10000, 32, },
++ { "M25P32", 0x15, 0x10000, 64, },
++ { "M25P64", 0x16, 0x10000, 128, },
++ { "M25FL128", 0x17, 0x10000, 256, },
++ { 0 },
++};
++
++static struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
++ { "SST25WF512", 1, 0x1000, 16, },
++ { "SST25VF512", 0x48, 0x1000, 16, },
++ { "SST25WF010", 2, 0x1000, 32, },
++ { "SST25VF010", 0x49, 0x1000, 32, },
++ { "SST25WF020", 3, 0x1000, 64, },
++ { "SST25VF020", 0x43, 0x1000, 64, },
++ { "SST25WF040", 4, 0x1000, 128, },
++ { "SST25VF040", 0x44, 0x1000, 128, },
++ { "SST25VF040B", 0x8d, 0x1000, 128, },
++ { "SST25WF080", 5, 0x1000, 256, },
++ { "SST25VF080B", 0x8e, 0x1000, 256, },
++ { "SST25VF016", 0x41, 0x1000, 512, },
++ { "SST25VF032", 0x4a, 0x1000, 1024, },
++ { "SST25VF064", 0x4b, 0x1000, 2048, },
++ { 0 },
++};
++
++static struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
++ { "AT45DB011", 0xc, 256, 512, },
++ { "AT45DB021", 0x14, 256, 1024, },
++ { "AT45DB041", 0x1c, 256, 2048, },
++ { "AT45DB081", 0x24, 256, 4096, },
++ { "AT45DB161", 0x2c, 512, 4096, },
++ { "AT45DB321", 0x34, 512, 8192, },
++ { "AT45DB642", 0x3c, 1024, 8192, },
++ { 0 },
++};
++
++static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
++{
++ int i;
++ chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
++ SSB_CHIPCO_FLASHCTL_START | opcode);
++ for (i = 0; i < 1000; i++) {
++ if (!(chipco_read32(cc, SSB_CHIPCO_FLASHCTL) &
++ SSB_CHIPCO_FLASHCTL_BUSY))
++ return;
++ cpu_relax();
++ }
++ pr_err("SFLASH control command failed (timeout)!\n");
++}
++
++/* Initialize serial flash access */
++int ssb_sflash_init(struct ssb_chipcommon *cc)
++{
++ struct ssb_sflash_tbl_e *e;
++ u32 id, id2;
++
++ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
++ case SSB_CHIPCO_FLASHT_STSER:
++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
++
++ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
++ id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
++
++ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
++ id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
++
++ switch (id) {
++ case 0xbf:
++ for (e = ssb_sflash_sst_tbl; e->name; e++) {
++ if (e->id == id2)
++ break;
++ }
++ break;
++ case 0x13:
++ return -ENOTSUPP;
++ default:
++ for (e = ssb_sflash_st_tbl; e->name; e++) {
++ if (e->id == id)
++ break;
++ }
++ break;
++ }
++ if (!e->name) {
++ pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n",
++ id, id2);
++ return -ENOTSUPP;
++ }
++
++ break;
++ case SSB_CHIPCO_FLASHT_ATSER:
++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
++ id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
++
++ for (e = ssb_sflash_at_tbl; e->name; e++) {
++ if (e->id == id)
++ break;
++ }
++ if (!e->name) {
++ pr_err("Unsupported Atmel serial flash (id: 0x%X)\n",
++ id);
++ return -ENOTSUPP;
++ }
++
++ break;
++ default:
++ pr_err("Unsupported flash type\n");
++ return -ENOTSUPP;
++ }
++
++ pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
++ e->name, e->blocksize, e->numblocks);
++
++ pr_err("Serial flash support is not implemented yet!\n");
++
++ return -ENOTSUPP;
++}
+--- a/drivers/ssb/driver_gpio.c
++++ b/drivers/ssb/driver_gpio.c
+@@ -74,6 +74,16 @@ static void ssb_gpio_chipco_free(struct
+ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
+ }
+
++static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ return ssb_mips_irq(bus->chipco.dev) + 2;
++ else
++ return -EINVAL;
++}
++
+ static int ssb_gpio_chipco_init(struct ssb_bus *bus)
+ {
+ struct gpio_chip *chip = &bus->gpio;
+@@ -86,6 +96,7 @@ static int ssb_gpio_chipco_init(struct s
+ chip->set = ssb_gpio_chipco_set_value;
+ chip->direction_input = ssb_gpio_chipco_direction_input;
+ chip->direction_output = ssb_gpio_chipco_direction_output;
++ chip->to_irq = ssb_gpio_chipco_to_irq;
+ chip->ngpio = 16;
+ /* There is just one SoC in one device and its GPIO addresses should be
+ * deterministic to address them more easily. The other buses could get
+@@ -134,6 +145,16 @@ static int ssb_gpio_extif_direction_outp
+ return 0;
+ }
+
++static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ return ssb_mips_irq(bus->extif.dev) + 2;
++ else
++ return -EINVAL;
++}
++
+ static int ssb_gpio_extif_init(struct ssb_bus *bus)
+ {
+ struct gpio_chip *chip = &bus->gpio;
+@@ -144,6 +165,7 @@ static int ssb_gpio_extif_init(struct ss
+ chip->set = ssb_gpio_extif_set_value;
+ chip->direction_input = ssb_gpio_extif_direction_input;
+ chip->direction_output = ssb_gpio_extif_direction_output;
++ chip->to_irq = ssb_gpio_extif_to_irq;
+ chip->ngpio = 5;
+ /* There is just one SoC in one device and its GPIO addresses should be
+ * deterministic to address them more easily. The other buses could get
+--- a/drivers/ssb/driver_mipscore.c
++++ b/drivers/ssb/driver_mipscore.c
+@@ -10,6 +10,7 @@
+
+ #include <linux/ssb/ssb.h>
+
++#include <linux/mtd/physmap.h>
+ #include <linux/serial.h>
+ #include <linux/serial_core.h>
+ #include <linux/serial_reg.h>
+@@ -17,6 +18,25 @@
+
+ #include "ssb_private.h"
+
++static const char *part_probes[] = { "bcm47xxpart", NULL };
++
++static struct physmap_flash_data ssb_pflash_data = {
++ .part_probe_types = part_probes,
++};
++
++static struct resource ssb_pflash_resource = {
++ .name = "ssb_pflash",
++ .flags = IORESOURCE_MEM,
++};
++
++struct platform_device ssb_pflash_dev = {
++ .name = "physmap-flash",
++ .dev = {
++ .platform_data = &ssb_pflash_data,
++ },
++ .resource = &ssb_pflash_resource,
++ .num_resources = 1,
++};
+
+ static inline u32 mips_read32(struct ssb_mipscore *mcore,
+ u16 offset)
+@@ -189,34 +209,43 @@ static void ssb_mips_serial_init(struct
+ static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
+ {
+ struct ssb_bus *bus = mcore->dev->bus;
++ struct ssb_pflash *pflash = &mcore->pflash;
+
+ /* When there is no chipcommon on the bus there is 4MB flash */
+ if (!ssb_chipco_available(&bus->chipco)) {
+- mcore->pflash.present = true;
+- mcore->pflash.buswidth = 2;
+- mcore->pflash.window = SSB_FLASH1;
+- mcore->pflash.window_size = SSB_FLASH1_SZ;
+- return;
++ pflash->present = true;
++ pflash->buswidth = 2;
++ pflash->window = SSB_FLASH1;
++ pflash->window_size = SSB_FLASH1_SZ;
++ goto ssb_pflash;
+ }
+
+ /* There is ChipCommon, so use it to read info about flash */
+ switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
+ case SSB_CHIPCO_FLASHT_STSER:
+ case SSB_CHIPCO_FLASHT_ATSER:
+- pr_err("Serial flash not supported\n");
++ pr_debug("Found serial flash\n");
++ ssb_sflash_init(&bus->chipco);
+ break;
+ case SSB_CHIPCO_FLASHT_PARA:
+ pr_debug("Found parallel flash\n");
+- mcore->pflash.present = true;
+- mcore->pflash.window = SSB_FLASH2;
+- mcore->pflash.window_size = SSB_FLASH2_SZ;
++ pflash->present = true;
++ pflash->window = SSB_FLASH2;
++ pflash->window_size = SSB_FLASH2_SZ;
+ if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
+ & SSB_CHIPCO_CFG_DS16) == 0)
+- mcore->pflash.buswidth = 1;
++ pflash->buswidth = 1;
+ else
+- mcore->pflash.buswidth = 2;
++ pflash->buswidth = 2;
+ break;
+ }
++
++ssb_pflash:
++ if (pflash->present) {
++ ssb_pflash_data.width = pflash->buswidth;
++ ssb_pflash_resource.start = pflash->window;
++ ssb_pflash_resource.end = pflash->window + pflash->window_size;
++ }
+ }
+
+ u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -549,6 +549,14 @@ static int ssb_devices_register(struct s
+ dev_idx++;
+ }
+
++#ifdef CONFIG_SSB_DRIVER_MIPS
++ if (bus->mipscore.pflash.present) {
++ err = platform_device_register(&ssb_pflash_dev);
++ if (err)
++ pr_err("Error registering parallel flash\n");
++ }
++#endif
++
+ return 0;
+ error:
+ /* Unwind the already registered devices. */
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -217,6 +217,21 @@ extern u32 ssb_chipco_watchdog_timer_set
+ u32 ticks);
+ extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
+
++/* driver_chipcommon_sflash.c */
++#ifdef CONFIG_SSB_SFLASH
++int ssb_sflash_init(struct ssb_chipcommon *cc);
++#else
++static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
++{
++ pr_err("Serial flash not supported\n");
++ return 0;
++}
++#endif /* CONFIG_SSB_SFLASH */
++
++#ifdef CONFIG_SSB_DRIVER_MIPS
++extern struct platform_device ssb_pflash_dev;
++#endif
++
+ #ifdef CONFIG_SSB_DRIVER_EXTIF
+ extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
+ extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
+--- a/include/linux/ssb/ssb_driver_mips.h
++++ b/include/linux/ssb/ssb_driver_mips.h
+@@ -45,6 +45,11 @@ void ssb_mipscore_init(struct ssb_mipsco
+ {
+ }
+
++static inline unsigned int ssb_mips_irq(struct ssb_device *dev)
++{
++ return 0;
++}
++
+ #endif /* CONFIG_SSB_DRIVER_MIPS */
+
+ #endif /* LINUX_SSB_MIPSCORE_H_ */
--- /dev/null
+--- a/arch/mips/bcm47xx/serial.c
++++ b/arch/mips/bcm47xx/serial.c
+@@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
+
+ p->mapbase = (unsigned int) bcma_port->regs;
+ p->membase = (void *) bcma_port->regs;
+- p->irq = bcma_port->irq + 2;
++ p->irq = bcma_port->irq;
+ p->uartclk = bcma_port->baud_base;
+ p->regshift = bcma_port->reg_shift;
+ p->iotype = UPIO_MEM;
+--- a/drivers/bcma/bcma_private.h
++++ b/drivers/bcma/bcma_private.h
+@@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc
+ int bcma_bus_suspend(struct bcma_bus *bus);
+ int bcma_bus_resume(struct bcma_bus *bus);
+ #endif
++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
++ u8 unit);
+
+ /* scan.c */
+ int bcma_bus_scan(struct bcma_bus *bus);
+@@ -45,6 +47,7 @@ int bcma_sprom_get(struct bcma_bus *bus)
+ /* driver_chipcommon.c */
+ #ifdef CONFIG_BCMA_DRIVER_MIPS
+ void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
++extern struct platform_device bcma_pflash_dev;
+ #endif /* CONFIG_BCMA_DRIVER_MIPS */
+
+ /* driver_chipcommon_pmu.c */
+--- a/drivers/bcma/driver_chipcommon.c
++++ b/drivers/bcma/driver_chipcommon.c
+@@ -329,7 +329,7 @@ void bcma_chipco_serial_init(struct bcma
+ return;
+ }
+
+- irq = bcma_core_mips_irq(cc->core);
++ irq = bcma_core_irq(cc->core);
+
+ /* Determine the registers of the UARTs */
+ cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
+--- a/drivers/bcma/driver_chipcommon_nflash.c
++++ b/drivers/bcma/driver_chipcommon_nflash.c
+@@ -5,11 +5,11 @@
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
++#include "bcma_private.h"
++
+ #include <linux/platform_device.h>
+ #include <linux/bcma/bcma.h>
+
+-#include "bcma_private.h"
+-
+ struct platform_device bcma_nflash_dev = {
+ .name = "bcma_nflash",
+ .num_resources = 0,
+--- a/drivers/bcma/driver_chipcommon_sflash.c
++++ b/drivers/bcma/driver_chipcommon_sflash.c
+@@ -5,11 +5,11 @@
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
++#include "bcma_private.h"
++
+ #include <linux/platform_device.h>
+ #include <linux/bcma/bcma.h>
+
+-#include "bcma_private.h"
+-
+ static struct resource bcma_sflash_resource = {
+ .name = "bcma_sflash",
+ .start = BCMA_SOC_FLASH2,
+--- a/drivers/bcma/driver_gpio.c
++++ b/drivers/bcma/driver_gpio.c
+@@ -73,6 +73,16 @@ static void bcma_gpio_free(struct gpio_c
+ bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
+ }
+
++static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
++{
++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
++
++ if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
++ return bcma_core_irq(cc->core);
++ else
++ return -EINVAL;
++}
++
+ int bcma_gpio_init(struct bcma_drv_cc *cc)
+ {
+ struct gpio_chip *chip = &cc->gpio;
+@@ -85,6 +95,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
+ chip->set = bcma_gpio_set_value;
+ chip->direction_input = bcma_gpio_direction_input;
+ chip->direction_output = bcma_gpio_direction_output;
++ chip->to_irq = bcma_gpio_to_irq;
+ chip->ngpio = 16;
+ /* There is just one SoC in one device and its GPIO addresses should be
+ * deterministic to address them more easily. The other buses could get
+--- a/drivers/bcma/driver_mips.c
++++ b/drivers/bcma/driver_mips.c
+@@ -14,11 +14,33 @@
+
+ #include <linux/bcma/bcma.h>
+
++#include <linux/mtd/physmap.h>
++#include <linux/platform_device.h>
+ #include <linux/serial.h>
+ #include <linux/serial_core.h>
+ #include <linux/serial_reg.h>
+ #include <linux/time.h>
+
++static const char *part_probes[] = { "bcm47xxpart", NULL };
++
++static struct physmap_flash_data bcma_pflash_data = {
++ .part_probe_types = part_probes,
++};
++
++static struct resource bcma_pflash_resource = {
++ .name = "bcma_pflash",
++ .flags = IORESOURCE_MEM,
++};
++
++struct platform_device bcma_pflash_dev = {
++ .name = "physmap-flash",
++ .dev = {
++ .platform_data = &bcma_pflash_data,
++ },
++ .resource = &bcma_pflash_resource,
++ .num_resources = 1,
++};
++
+ /* The 47162a0 hangs when reading MIPS DMP registers registers */
+ static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
+ {
+@@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
+ return dev->core_index;
+ flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
+
+- return flag & 0x1F;
++ if (flag)
++ return flag & 0x1F;
++ else
++ return 0x3f;
+ }
+
+ /* Get the MIPS IRQ assignment for a specified device.
+ * If unassigned, 0 is returned.
++ * If disabled, 5 is returned.
++ * If not supported, 6 is returned.
+ */
+-unsigned int bcma_core_mips_irq(struct bcma_device *dev)
++static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
+ {
+ struct bcma_device *mdev = dev->bus->drv_mips.core;
+ u32 irqflag;
+ unsigned int irq;
+
+ irqflag = bcma_core_mips_irqflag(dev);
++ if (irqflag == 0x3f)
++ return 6;
+
+- for (irq = 1; irq <= 4; irq++)
++ for (irq = 0; irq <= 4; irq++)
+ if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
+ (1 << irqflag))
+ return irq;
+
+- return 0;
++ return 5;
+ }
+-EXPORT_SYMBOL(bcma_core_mips_irq);
++
++unsigned int bcma_core_irq(struct bcma_device *dev)
++{
++ unsigned int mips_irq = bcma_core_mips_irq(dev);
++ return mips_irq <= 4 ? mips_irq + 2 : 0;
++}
++EXPORT_SYMBOL(bcma_core_irq);
+
+ static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
+ {
+@@ -114,7 +149,7 @@ static void bcma_core_mips_set_irq(struc
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
+ bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
+ ~(1 << irqflag));
+- else
++ else if (oldirq != 5)
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
+
+ /* assign the new one */
+@@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struc
+ bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
+ (1 << irqflag));
+ } else {
+- u32 oldirqflag = bcma_read32(mdev,
+- BCMA_MIPS_MIPS74K_INTMASK(irq));
+- if (oldirqflag) {
++ u32 irqinitmask = bcma_read32(mdev,
++ BCMA_MIPS_MIPS74K_INTMASK(irq));
++ if (irqinitmask) {
+ struct bcma_device *core;
+
+ /* backplane irq line is in use, find out who uses
+@@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struc
+ */
+ list_for_each_entry(core, &bus->cores, list) {
+ if ((1 << bcma_core_mips_irqflag(core)) ==
+- oldirqflag) {
++ irqinitmask) {
+ bcma_core_mips_set_irq(core, 0);
+ break;
+ }
+@@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
+ 1 << irqflag);
+ }
+
+- bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
+- dev->id.id, oldirq + 2, irq + 2);
++ bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
++ dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
++}
++
++static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
++ u16 coreid, u8 unit)
++{
++ struct bcma_device *core;
++
++ core = bcma_find_core_unit(bus, coreid, unit);
++ if (!core) {
++ bcma_warn(bus,
++ "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
++ coreid, unit);
++ return;
++ }
++
++ bcma_core_mips_set_irq(core, irq);
+ }
+
+ static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
+ {
+ int i;
+ static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
+- printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
++ printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
+ for (i = 0; i <= 6; i++)
+ printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
+ printk("\n");
+@@ -182,6 +233,7 @@ static void bcma_core_mips_flash_detect(
+ {
+ struct bcma_bus *bus = mcore->core->bus;
+ struct bcma_drv_cc *cc = &bus->drv_cc;
++ struct bcma_pflash *pflash = &cc->pflash;
+
+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
+ case BCMA_CC_FLASHT_STSER:
+@@ -191,15 +243,20 @@ static void bcma_core_mips_flash_detect(
+ break;
+ case BCMA_CC_FLASHT_PARA:
+ bcma_debug(bus, "Found parallel flash\n");
+- cc->pflash.present = true;
+- cc->pflash.window = BCMA_SOC_FLASH2;
+- cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
++ pflash->present = true;
++ pflash->window = BCMA_SOC_FLASH2;
++ pflash->window_size = BCMA_SOC_FLASH2_SZ;
+
+ if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
+ BCMA_CC_FLASH_CFG_DS) == 0)
+- cc->pflash.buswidth = 1;
++ pflash->buswidth = 1;
+ else
+- cc->pflash.buswidth = 2;
++ pflash->buswidth = 2;
++
++ bcma_pflash_data.width = pflash->buswidth;
++ bcma_pflash_resource.start = pflash->window;
++ bcma_pflash_resource.end = pflash->window + pflash->window_size;
++
+ break;
+ default:
+ bcma_err(bus, "Flash type not supported\n");
+@@ -227,6 +284,32 @@ void bcma_core_mips_early_init(struct bc
+ mcore->early_setup_done = true;
+ }
+
++static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
++{
++ struct bcma_device *cpu, *pcie, *i2s;
++
++ /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
++ * (IRQ flags > 7 are ignored when setting the interrupt masks)
++ */
++ if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
++ bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
++ return;
++
++ cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
++ pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
++ i2s = bcma_find_core(bus, BCMA_CORE_I2S);
++ if (cpu && pcie && i2s &&
++ bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
++ bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
++ bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
++ bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
++ bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
++ bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
++ bcma_debug(bus,
++ "Moved i2s interrupt to oob line 7 instead of 8\n");
++ }
++}
++
+ void bcma_core_mips_init(struct bcma_drv_mips *mcore)
+ {
+ struct bcma_bus *bus;
+@@ -236,43 +319,55 @@ void bcma_core_mips_init(struct bcma_drv
+ if (mcore->setup_done)
+ return;
+
+- bcma_info(bus, "Initializing MIPS core...\n");
++ bcma_debug(bus, "Initializing MIPS core...\n");
+
+ bcma_core_mips_early_init(mcore);
+
+- mcore->assigned_irqs = 1;
++ bcma_fix_i2s_irqflag(bus);
+
+- /* Assign IRQs to all cores on the bus */
+- list_for_each_entry(core, &bus->cores, list) {
+- int mips_irq;
+- if (core->irq)
+- continue;
+-
+- mips_irq = bcma_core_mips_irq(core);
+- if (mips_irq > 4)
+- core->irq = 0;
+- else
+- core->irq = mips_irq + 2;
+- if (core->irq > 5)
+- continue;
+- switch (core->id.id) {
+- case BCMA_CORE_PCI:
+- case BCMA_CORE_PCIE:
+- case BCMA_CORE_ETHERNET:
+- case BCMA_CORE_ETHERNET_GBIT:
+- case BCMA_CORE_MAC_GBIT:
+- case BCMA_CORE_80211:
+- case BCMA_CORE_USB20_HOST:
+- /* These devices get their own IRQ line if available,
+- * the rest goes on IRQ0
+- */
+- if (mcore->assigned_irqs <= 4)
+- bcma_core_mips_set_irq(core,
+- mcore->assigned_irqs++);
+- break;
++ switch (bus->chipinfo.id) {
++ case BCMA_CHIP_ID_BCM4716:
++ case BCMA_CHIP_ID_BCM4748:
++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
++ break;
++ case BCMA_CHIP_ID_BCM5356:
++ case BCMA_CHIP_ID_BCM47162:
++ case BCMA_CHIP_ID_BCM53572:
++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
++ break;
++ case BCMA_CHIP_ID_BCM5357:
++ case BCMA_CHIP_ID_BCM4749:
++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
++ break;
++ case BCMA_CHIP_ID_BCM4706:
++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
++ 0);
++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
++ 0);
++ break;
++ default:
++ list_for_each_entry(core, &bus->cores, list) {
++ core->irq = bcma_core_irq(core);
+ }
++ bcma_err(bus,
++ "Unknown device (0x%x) found, can not configure IRQs\n",
++ bus->chipinfo.id);
+ }
+- bcma_info(bus, "IRQ reconfiguration done\n");
++ bcma_debug(bus, "IRQ reconfiguration done\n");
+ bcma_core_mips_dump_irq(bus);
+
+ mcore->setup_done = true;
+--- a/drivers/bcma/driver_pci_host.c
++++ b/drivers/bcma/driver_pci_host.c
+@@ -94,19 +94,19 @@ static int bcma_extpci_read_config(struc
+ if (dev == 0) {
+ /* we support only two functions on device 0 */
+ if (func > 1)
+- return -EINVAL;
++ goto out;
+
+ /* accesses to config registers with offsets >= 256
+ * requires indirect access.
+ */
+ if (off >= PCI_CONFIG_SPACE_SIZE) {
+ addr = (func << 12);
+- addr |= (off & 0x0FFF);
++ addr |= (off & 0x0FFC);
+ val = bcma_pcie_read_config(pc, addr);
+ } else {
+ addr = BCMA_CORE_PCI_PCICFG0;
+ addr |= (func << 8);
+- addr |= (off & 0xfc);
++ addr |= (off & 0xFC);
+ val = pcicore_read32(pc, addr);
+ }
+ } else {
+@@ -119,11 +119,9 @@ static int bcma_extpci_read_config(struc
+ goto out;
+
+ if (mips_busprobe32(val, mmio)) {
+- val = 0xffffffff;
++ val = 0xFFFFFFFF;
+ goto unmap;
+ }
+-
+- val = readl(mmio);
+ }
+ val >>= (8 * (off & 3));
+
+@@ -151,7 +149,7 @@ static int bcma_extpci_write_config(stru
+ const void *buf, int len)
+ {
+ int err = -EINVAL;
+- u32 addr = 0, val = 0;
++ u32 addr, val;
+ void __iomem *mmio = 0;
+ u16 chipid = pc->core->bus->chipinfo.id;
+
+@@ -159,16 +157,22 @@ static int bcma_extpci_write_config(stru
+ if (unlikely(len != 1 && len != 2 && len != 4))
+ goto out;
+ if (dev == 0) {
++ /* we support only two functions on device 0 */
++ if (func > 1)
++ goto out;
++
+ /* accesses to config registers with offsets >= 256
+ * requires indirect access.
+ */
+- if (off < PCI_CONFIG_SPACE_SIZE) {
+- addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
++ if (off >= PCI_CONFIG_SPACE_SIZE) {
++ addr = (func << 12);
++ addr |= (off & 0x0FFC);
++ val = bcma_pcie_read_config(pc, addr);
++ } else {
++ addr = BCMA_CORE_PCI_PCICFG0;
+ addr |= (func << 8);
+- addr |= (off & 0xfc);
+- mmio = ioremap_nocache(addr, sizeof(val));
+- if (!mmio)
+- goto out;
++ addr |= (off & 0xFC);
++ val = pcicore_read32(pc, addr);
+ }
+ } else {
+ addr = bcma_get_cfgspace_addr(pc, dev, func, off);
+@@ -180,19 +184,17 @@ static int bcma_extpci_write_config(stru
+ goto out;
+
+ if (mips_busprobe32(val, mmio)) {
+- val = 0xffffffff;
++ val = 0xFFFFFFFF;
+ goto unmap;
+ }
+ }
+
+ switch (len) {
+ case 1:
+- val = readl(mmio);
+ val &= ~(0xFF << (8 * (off & 3)));
+ val |= *((const u8 *)buf) << (8 * (off & 3));
+ break;
+ case 2:
+- val = readl(mmio);
+ val &= ~(0xFFFF << (8 * (off & 3)));
+ val |= *((const u16 *)buf) << (8 * (off & 3));
+ break;
+@@ -200,13 +202,14 @@ static int bcma_extpci_write_config(stru
+ val = *((const u32 *)buf);
+ break;
+ }
+- if (dev == 0 && !addr) {
++ if (dev == 0) {
+ /* accesses to config registers with offsets >= 256
+ * requires indirect access.
+ */
+- addr = (func << 12);
+- addr |= (off & 0x0FFF);
+- bcma_pcie_write_config(pc, addr, val);
++ if (off >= PCI_CONFIG_SPACE_SIZE)
++ bcma_pcie_write_config(pc, addr, val);
++ else
++ pcicore_write32(pc, addr, val);
+ } else {
+ writel(val, mmio);
+
+@@ -276,7 +279,7 @@ static u8 bcma_find_pci_capability(struc
+ /* check for Header type 0 */
+ bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
+ sizeof(u8));
+- if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
++ if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
+ return cap_ptr;
+
+ /* check if the capability pointer field exists */
+@@ -426,7 +429,7 @@ void bcma_core_pci_hostmode_init(struct
+ /* Reset RC */
+ usleep_range(3000, 5000);
+ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
+- usleep_range(1000, 2000);
++ msleep(50);
+ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
+ BCMA_CORE_PCI_CTL_RST_OE);
+
+@@ -488,6 +491,17 @@ void bcma_core_pci_hostmode_init(struct
+
+ bcma_core_pci_enable_crs(pc);
+
++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
++ bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
++ u16 val16;
++ bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
++ &val16, sizeof(val16));
++ val16 |= (2 << 5); /* Max payload size of 512 */
++ val16 |= (2 << 12); /* MRRS 512 */
++ bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
++ &val16, sizeof(val16));
++ }
++
+ /* Enable PCI bridge BAR0 memory & master access */
+ tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
+@@ -576,7 +590,7 @@ int bcma_core_pci_plat_dev_init(struct p
+ pr_info("PCI: Fixing up device %s\n", pci_name(dev));
+
+ /* Fix up interrupt lines */
+- dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
++ dev->irq = bcma_core_irq(pc_host->pdev->core);
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+
+ return 0;
+@@ -595,6 +609,6 @@ int bcma_core_pci_pcibios_map_irq(const
+
+ pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
+ pci_ops);
+- return bcma_core_mips_irq(pc_host->pdev->core) + 2;
++ return bcma_core_irq(pc_host->pdev->core);
+ }
+ EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
+--- a/drivers/bcma/main.c
++++ b/drivers/bcma/main.c
+@@ -81,8 +81,8 @@ struct bcma_device *bcma_find_core(struc
+ }
+ EXPORT_SYMBOL_GPL(bcma_find_core);
+
+-static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
+- u8 unit)
++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
++ u8 unit)
+ {
+ struct bcma_device *core;
+
+@@ -149,6 +149,14 @@ static int bcma_register_cores(struct bc
+ dev_id++;
+ }
+
++#ifdef CONFIG_BCMA_DRIVER_MIPS
++ if (bus->drv_cc.pflash.present) {
++ err = platform_device_register(&bcma_pflash_dev);
++ if (err)
++ bcma_err(bus, "Error registering parallel flash\n");
++ }
++#endif
++
+ #ifdef CONFIG_BCMA_SFLASH
+ if (bus->drv_cc.sflash.present) {
+ err = platform_device_register(&bcma_sflash_dev);
+--- a/include/linux/bcma/bcma_driver_chipcommon.h
++++ b/include/linux/bcma/bcma_driver_chipcommon.h
+@@ -27,7 +27,7 @@
+ #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
+ #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
+ #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
+-#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
++#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
+ #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
+ #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
+ #define BCMA_PLLTYPE_NONE 0x00000000
+--- a/include/linux/bcma/bcma_driver_mips.h
++++ b/include/linux/bcma/bcma_driver_mips.h
+@@ -28,6 +28,7 @@
+ #define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
+ #define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
+
++#define BCMA_MIPS_OOBSELINA74 0x004
+ #define BCMA_MIPS_OOBSELOUTA30 0x100
+
+ struct bcma_device;
+@@ -36,19 +37,23 @@ struct bcma_drv_mips {
+ struct bcma_device *core;
+ u8 setup_done:1;
+ u8 early_setup_done:1;
+- unsigned int assigned_irqs;
+ };
+
+ #ifdef CONFIG_BCMA_DRIVER_MIPS
+ extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
+ extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
++
++extern unsigned int bcma_core_irq(struct bcma_device *core);
+ #else
+ static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
+ static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
++
++static inline unsigned int bcma_core_irq(struct bcma_device *core)
++{
++ return 0;
++}
+ #endif
+
+ extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
+
+-extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
+-
+ #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
+--- a/include/linux/bcma/bcma_driver_pci.h
++++ b/include/linux/bcma/bcma_driver_pci.h
+@@ -179,6 +179,8 @@ struct pci_dev;
+ #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
+ #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
+
++#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
++
+ /* PCIE Root Capability Register bits (Host mode only) */
+ #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
+
projects / openwrt / staging / wigyori.git / commitdiff