+++ /dev/null
-# CONFIG_AHCI_SUNXI is not set
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ARCH_AXXIA is not set
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=416
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_ERRATA_643719=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_LPAE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-# CONFIG_ATA_SFF is not set
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_AXP20X_POWER=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_BOUNCE=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CAN=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONNECTOR=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BIG_ENDIAN is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_SUN4I_SS=y
-CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_SUN4I=y
-CONFIG_DMA_SUN6I=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_DWMAC_DWC_QOS_ETH is not set
-CONFIG_DWMAC_GENERIC=y
-# CONFIG_DWMAC_SUN8I is not set
-CONFIG_DWMAC_SUNXI=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ELF_CORE=y
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-# CONFIG_F2FS_CHECK_FS is not set
-CONFIG_F2FS_FS=y
-# CONFIG_F2FS_FS_SECURITY is not set
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_STAT_FS=y
-CONFIG_FAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_FOREIGN_ENDIAN=y
-CONFIG_FB_LITTLE_ENDIAN=y
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FREEZER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_AXP209=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_GRO_CELLS is not set
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_HAVE_ARM_SMCCC=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_GUP=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
-CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
-CONFIG_HAVE_KVM_EVENTFD=y
-CONFIG_HAVE_KVM_IRQCHIP=y
-CONFIG_HAVE_KVM_IRQFD=y
-CONFIG_HAVE_KVM_IRQ_ROUTING=y
-CONFIG_HAVE_KVM_MSI=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_RCU_TABLE_FREE=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-# CONFIG_HUGETLBFS is not set
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_I2C_SUN6I_P2WI=y
-CONFIG_IIO=y
-# CONFIG_IIO_BUFFER is not set
-# CONFIG_IIO_TRIGGER is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_AXP20X_PEK=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-# CONFIG_KERNEL_MODE_NEON is not set
-CONFIG_KEYBOARD_SUN4I_LRADC=y
-CONFIG_KSM=y
-CONFIG_KVM=y
-CONFIG_KVM_ARM_HOST=y
-CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
-CONFIG_KVM_MMIO=y
-CONFIG_KVM_VFIO=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_MACH_SUN4I=y
-CONFIG_MACH_SUN5I=y
-CONFIG_MACH_SUN6I=y
-CONFIG_MACH_SUN7I=y
-CONFIG_MACH_SUN8I=y
-CONFIG_MACH_SUN9I=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_SUN4I=y
-CONFIG_MEDIA_SUPPORT=y
-# CONFIG_MFD_AC100 is not set
-CONFIG_MFD_AXP20X=y
-CONFIG_MFD_AXP20X_I2C=y
-CONFIG_MFD_AXP20X_RSB=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SUNXI=y
-CONFIG_MMU_NOTIFIER=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD=y
-CONFIG_MTD_SPLIT_SUPPORT=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_JEDECPROBE=y
-# CONFIG_MTD_IMPA7 is not set
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_VENDOR_ALLWINNER=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=8
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SUNXI_SID=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-# CONFIG_PCI_DOMAINS_GENERIC is not set
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_SUN4I_USB=y
-CONFIG_PHY_SUN9I_USB=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_SUN4I_A10=y
-# CONFIG_PINCTRL_SUN50I_A64 is not set
-# CONFIG_PINCTRL_SUN50I_A64_R is not set
-# CONFIG_PINCTRL_SUN50I_H5 is not set
-CONFIG_PINCTRL_SUN5I=y
-CONFIG_PINCTRL_SUN6I_A31=y
-CONFIG_PINCTRL_SUN6I_A31_R=y
-CONFIG_PINCTRL_SUN8I_A23=y
-CONFIG_PINCTRL_SUN8I_A23_R=y
-CONFIG_PINCTRL_SUN8I_A33=y
-CONFIG_PINCTRL_SUN8I_A83T=y
-CONFIG_PINCTRL_SUN8I_A83T_R=y
-CONFIG_PINCTRL_SUN8I_H3=y
-CONFIG_PINCTRL_SUN8I_H3_R=y
-CONFIG_PINCTRL_SUN8I_V3S=y
-CONFIG_PINCTRL_SUN9I_A80=y
-CONFIG_PINCTRL_SUN9I_A80_R=y
-CONFIG_PINCTRL_SUNXI=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PWM=y
-CONFIG_PWM_SUN4I=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-# CONFIG_RCU_BOOST is not set
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_AXP20X=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_RELAY=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SUNXI=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_SATA_PMP=y
-# CONFIG_SCHED_INFO is not set
-CONFIG_SCSI=y
-CONFIG_SDIO_UART=y
-CONFIG_SECURITYFS=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=8
-CONFIG_SERIAL_8250_RUNTIME_UARTS=8
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SND=y
-CONFIG_SND_COMPRESS_OFFLOAD=y
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_PCM=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SUN4I_I2S is not set
-# CONFIG_SND_SUN4I_SPDIF is not set
-# CONFIG_SND_SUN8I_CODEC is not set
-# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_SUN4I=y
-CONFIG_SPI_SUN6I=y
-CONFIG_SRCU=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_SUN4I_A10_CCU=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN5I_CCU=y
-CONFIG_SUN5I_HSTIMER=y
-CONFIG_SUN6I_A31_CCU=y
-CONFIG_SUN8I_A23_CCU=y
-CONFIG_SUN8I_A33_CCU=y
-CONFIG_SUN8I_A83T_CCU=y
-CONFIG_SUN8I_DE2_CCU=y
-CONFIG_SUN8I_H3_CCU=y
-CONFIG_SUN8I_R40_CCU=y
-CONFIG_SUN8I_R_CCU=y
-CONFIG_SUN8I_V3S_CCU=y
-CONFIG_SUN9I_A80_CCU=y
-CONFIG_SUNXI_CCU=y
-CONFIG_SUNXI_RSB=y
-CONFIG_SUNXI_SRAM=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_B53=y
-# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set
-CONFIG_SWCONFIG_B53_PHY_DRIVER=y
-CONFIG_SWCONFIG_B53_PHY_FIXUP=y
-# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_SYS_SUPPORTS_HUGETLBFS=y
-CONFIG_TASKS_RCU=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TOUCHSCREEN_PROPERTIES=y
-CONFIG_TOUCHSCREEN_SUN4I=y
-CONFIG_TREE_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_DWC2_HOST=y
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USERIO=y
-CONFIG_USE_OF=y
-CONFIG_VDSO=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VHOST=y
-CONFIG_VHOST_NET=y
-CONFIG_VIRTUALIZATION=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
-# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
-CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_FRAME_POINTERS=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_ARM64=y
-# CONFIG_ARM64_16K_PAGES is not set
-CONFIG_ARM64_4K_PAGES=y
-# CONFIG_ARM64_64K_PAGES is not set
-CONFIG_ARM64_CONT_SHIFT=4
-# CONFIG_ARM64_CRYPTO is not set
-# CONFIG_ARM64_HW_AFDBM is not set
-# CONFIG_ARM64_LSE_ATOMICS is not set
-CONFIG_ARM64_PAGE_SHIFT=12
-# CONFIG_ARM64_PAN is not set
-# CONFIG_ARM64_PMEM is not set
-# CONFIG_ARM64_PTDUMP_CORE is not set
-# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
-# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
-CONFIG_ARM64_SSBD=y
-# CONFIG_ARM64_UAO is not set
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-# CONFIG_ARM64_VA_BITS_48 is not set
-# CONFIG_ARM64_VHE is not set
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_GIC_V3=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_DWMAC_SUN8I=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_ARCH_HUGE_VMAP=y
-CONFIG_HAVE_ARCH_KASAN=y
-CONFIG_HAVE_ARCH_VMAP_STACK=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_DEBUG_BUGVERBOSE=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-CONFIG_HAVE_PATA_PLATFORM=y
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_KERNEL_MODE_NEON=y
-CONFIG_KVM_ARM_PMU=y
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NO_IOPORT_MAP=y
-# CONFIG_NUMA is not set
-CONFIG_PARTITION_PERCPU=y
-# CONFIG_PCI_DOMAINS is not set
-# CONFIG_PINCTRL_SUN4I_A10 is not set
-CONFIG_PINCTRL_SUN50I_A64=y
-CONFIG_PINCTRL_SUN50I_A64_R=y
-CONFIG_PINCTRL_SUN50I_H5=y
-# CONFIG_PINCTRL_SUN5I is not set
-# CONFIG_PINCTRL_SUN6I_A31 is not set
-# CONFIG_PINCTRL_SUN6I_A31_R is not set
-# CONFIG_PINCTRL_SUN8I_A23 is not set
-# CONFIG_PINCTRL_SUN8I_A23_R is not set
-# CONFIG_PINCTRL_SUN8I_A33 is not set
-# CONFIG_PINCTRL_SUN8I_A83T is not set
-# CONFIG_PINCTRL_SUN8I_A83T_R is not set
-# CONFIG_PINCTRL_SUN8I_H3 is not set
-# CONFIG_PINCTRL_SUN8I_V3S is not set
-# CONFIG_PINCTRL_SUN9I_A80 is not set
-# CONFIG_PINCTRL_SUN9I_A80_R is not set
-# CONFIG_RANDOMIZE_BASE is not set
-CONFIG_REALTEK_PHY=y
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SUN50I_A64_CCU=y
-CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_VMAP_STACK=y
+++ /dev/null
-CONFIG_DWMAC_SUN8I=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-# CONFIG_MACH_SUN4I is not set
-# CONFIG_MACH_SUN5I is not set
-# CONFIG_PINCTRL_GR8 is not set
-CONFIG_PINCTRL_SUN4I_A10=y
-# CONFIG_PINCTRL_SUN5I_A10S is not set
-# CONFIG_PINCTRL_SUN5I_A13 is not set
-CONFIG_MDIO_BUS_MUX=y
-# CONFIG_PINCTRL_SUN5I is not set
+++ /dev/null
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-# CONFIG_ARM_ERRATA_643719 is not set
-# CONFIG_ARM_LPAE is not set
-# CONFIG_MACH_SUN6I is not set
-# CONFIG_MACH_SUN7I is not set
-# CONFIG_MACH_SUN8I is not set
-# CONFIG_MACH_SUN9I is not set
-CONFIG_PGTABLE_LEVELS=2
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-# CONFIG_PINCTRL_SUN6I_A31 is not set
-# CONFIG_PINCTRL_SUN6I_A31_R is not set
-# CONFIG_PINCTRL_SUN8I_A23 is not set
-# CONFIG_PINCTRL_SUN8I_A23_R is not set
-# CONFIG_PINCTRL_SUN8I_A33 is not set
-# CONFIG_PINCTRL_SUN8I_A83T is not set
-# CONFIG_PINCTRL_SUN8I_A83T_R is not set
-# CONFIG_PINCTRL_SUN8I_H3 is not set
-# CONFIG_PINCTRL_SUN8I_H3_R is not set
-# CONFIG_PINCTRL_SUN8I_V3S is not set
-# CONFIG_PINCTRL_SUN9I_A80 is not set
-# CONFIG_PINCTRL_SUN9I_A80_R is not set
+++ /dev/null
-From b5beecb580376cd8d959eb990abece6a748a3ce3 Mon Sep 17 00:00:00 2001
-From: Corentin Labbe <clabbe.montjoie@gmail.com>
-Date: Tue, 24 Oct 2017 19:57:12 +0200
-Subject: [PATCH] net: stmmac: snps, dwmac-mdio MDIOs are automatically
- registered
-
-stmmac bindings docs said that its mdio node must have
-compatible = "snps,dwmac-mdio";
-Since dwmac-sun8i does not have any good reasons to not doing it, all
-their MDIO node must have it.
-
-Since these compatible is automatically registered, dwmac-sun8i compatible
-does not need to be in need_mdio_ids.
-
-Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ----
- 1 file changed, 4 deletions(-)
-
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -317,10 +317,6 @@ static int stmmac_dt_phy(struct plat_stm
- bool mdio = true;
- static const struct of_device_id need_mdio_ids[] = {
- { .compatible = "snps,dwc-qos-ethernet-4.10" },
-- { .compatible = "allwinner,sun8i-a83t-emac" },
-- { .compatible = "allwinner,sun8i-h3-emac" },
-- { .compatible = "allwinner,sun8i-v3s-emac" },
-- { .compatible = "allwinner,sun50i-a64-emac" },
- {},
- };
-
+++ /dev/null
-From 634db83b82658f4641d8026e340c6027cf74a6bb Mon Sep 17 00:00:00 2001
-From: Corentin Labbe <clabbe.montjoie@gmail.com>
-Date: Tue, 24 Oct 2017 19:57:13 +0200
-Subject: [PATCH] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs
-
-The Allwinner H3 SoC have two distinct MDIO bus, only one could be
-active at the same time.
-The selection of the active MDIO bus are done via some bits in the EMAC
-register of the system controller.
-
-This patch implement this MDIO switch via a custom MDIO-mux.
-
-Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 353 ++++++++++++++--------
- 2 files changed, 224 insertions(+), 130 deletions(-)
-
---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
-+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
-@@ -159,6 +159,7 @@ config DWMAC_SUN8I
- tristate "Allwinner sun8i GMAC support"
- default ARCH_SUNXI
- depends on OF && (ARCH_SUNXI || COMPILE_TEST)
-+ select MDIO_BUS_MUX
- ---help---
- Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
-
---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
-@@ -17,6 +17,7 @@
- #include <linux/clk.h>
- #include <linux/io.h>
- #include <linux/iopoll.h>
-+#include <linux/mdio-mux.h>
- #include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/of_device.h>
-@@ -41,14 +42,14 @@
- * This value is used for disabling properly EMAC
- * and used as a good starting value in case of the
- * boot process(uboot) leave some stuff.
-- * @internal_phy: Does the MAC embed an internal PHY
-+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
- * @support_mii: Does the MAC handle MII
- * @support_rmii: Does the MAC handle RMII
- * @support_rgmii: Does the MAC handle RGMII
- */
- struct emac_variant {
- u32 default_syscon_value;
-- int internal_phy;
-+ bool soc_has_internal_phy;
- bool support_mii;
- bool support_rmii;
- bool support_rgmii;
-@@ -61,7 +62,8 @@ struct emac_variant {
- * @rst_ephy: reference to the optional EPHY reset for the internal PHY
- * @variant: reference to the current board variant
- * @regmap: regmap for using the syscon
-- * @use_internal_phy: Does the current PHY choice imply using the internal PHY
-+ * @internal_phy_powered: Does the internal PHY is enabled
-+ * @mux_handle: Internal pointer used by mdio-mux lib
- */
- struct sunxi_priv_data {
- struct clk *tx_clk;
-@@ -70,12 +72,13 @@ struct sunxi_priv_data {
- struct reset_control *rst_ephy;
- const struct emac_variant *variant;
- struct regmap *regmap;
-- bool use_internal_phy;
-+ bool internal_phy_powered;
-+ void *mux_handle;
- };
-
- static const struct emac_variant emac_variant_h3 = {
- .default_syscon_value = 0x58000,
-- .internal_phy = PHY_INTERFACE_MODE_MII,
-+ .soc_has_internal_phy = true,
- .support_mii = true,
- .support_rmii = true,
- .support_rgmii = true
-@@ -83,20 +86,20 @@ static const struct emac_variant emac_va
-
- static const struct emac_variant emac_variant_v3s = {
- .default_syscon_value = 0x38000,
-- .internal_phy = PHY_INTERFACE_MODE_MII,
-+ .soc_has_internal_phy = true,
- .support_mii = true
- };
-
- static const struct emac_variant emac_variant_a83t = {
- .default_syscon_value = 0,
-- .internal_phy = 0,
-+ .soc_has_internal_phy = false,
- .support_mii = true,
- .support_rgmii = true
- };
-
- static const struct emac_variant emac_variant_a64 = {
- .default_syscon_value = 0,
-- .internal_phy = 0,
-+ .soc_has_internal_phy = false,
- .support_mii = true,
- .support_rmii = true,
- .support_rgmii = true
-@@ -195,6 +198,9 @@ static const struct emac_variant emac_va
- #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
- #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
- #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
-+#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
-+#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1
-+#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2
-
- /* H3/A64 specific bits */
- #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
-@@ -635,6 +641,159 @@ static int sun8i_dwmac_reset(struct stmm
- return 0;
- }
-
-+/* Search in mdio-mux node for internal PHY node and get its clk/reset */
-+static int get_ephy_nodes(struct stmmac_priv *priv)
-+{
-+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
-+ struct device_node *mdio_mux, *iphynode;
-+ struct device_node *mdio_internal;
-+ int ret;
-+
-+ mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
-+ if (!mdio_mux) {
-+ dev_err(priv->device, "Cannot get mdio-mux node\n");
-+ return -ENODEV;
-+ }
-+
-+ mdio_internal = of_find_compatible_node(mdio_mux, NULL,
-+ "allwinner,sun8i-h3-mdio-internal");
-+ if (!mdio_internal) {
-+ dev_err(priv->device, "Cannot get internal_mdio node\n");
-+ return -ENODEV;
-+ }
-+
-+ /* Seek for internal PHY */
-+ for_each_child_of_node(mdio_internal, iphynode) {
-+ gmac->ephy_clk = of_clk_get(iphynode, 0);
-+ if (IS_ERR(gmac->ephy_clk))
-+ continue;
-+ gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
-+ if (IS_ERR(gmac->rst_ephy)) {
-+ ret = PTR_ERR(gmac->rst_ephy);
-+ if (ret == -EPROBE_DEFER)
-+ return ret;
-+ continue;
-+ }
-+ dev_info(priv->device, "Found internal PHY node\n");
-+ return 0;
-+ }
-+ return -ENODEV;
-+}
-+
-+static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
-+{
-+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
-+ int ret;
-+
-+ if (gmac->internal_phy_powered) {
-+ dev_warn(priv->device, "Internal PHY already powered\n");
-+ return 0;
-+ }
-+
-+ dev_info(priv->device, "Powering internal PHY\n");
-+ ret = clk_prepare_enable(gmac->ephy_clk);
-+ if (ret) {
-+ dev_err(priv->device, "Cannot enable internal PHY\n");
-+ return ret;
-+ }
-+
-+ /* Make sure the EPHY is properly reseted, as U-Boot may leave
-+ * it at deasserted state, and thus it may fail to reset EMAC.
-+ */
-+ reset_control_assert(gmac->rst_ephy);
-+
-+ ret = reset_control_deassert(gmac->rst_ephy);
-+ if (ret) {
-+ dev_err(priv->device, "Cannot deassert internal phy\n");
-+ clk_disable_unprepare(gmac->ephy_clk);
-+ return ret;
-+ }
-+
-+ gmac->internal_phy_powered = true;
-+
-+ return 0;
-+}
-+
-+static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
-+{
-+ if (!gmac->internal_phy_powered)
-+ return 0;
-+
-+ clk_disable_unprepare(gmac->ephy_clk);
-+ reset_control_assert(gmac->rst_ephy);
-+ gmac->internal_phy_powered = false;
-+ return 0;
-+}
-+
-+/* MDIO multiplexing switch function
-+ * This function is called by the mdio-mux layer when it thinks the mdio bus
-+ * multiplexer needs to switch.
-+ * 'current_child' is the current value of the mux register
-+ * 'desired_child' is the value of the 'reg' property of the target child MDIO
-+ * node.
-+ * The first time this function is called, current_child == -1.
-+ * If current_child == desired_child, then the mux is already set to the
-+ * correct bus.
-+ */
-+static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
-+ void *data)
-+{
-+ struct stmmac_priv *priv = data;
-+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
-+ u32 reg, val;
-+ int ret = 0;
-+ bool need_power_ephy = false;
-+
-+ if (current_child ^ desired_child) {
-+ regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);
-+ switch (desired_child) {
-+ case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
-+ dev_info(priv->device, "Switch mux to internal PHY");
-+ val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
-+
-+ need_power_ephy = true;
-+ break;
-+ case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
-+ dev_info(priv->device, "Switch mux to external PHY");
-+ val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
-+ need_power_ephy = false;
-+ break;
-+ default:
-+ dev_err(priv->device, "Invalid child ID %x\n",
-+ desired_child);
-+ return -EINVAL;
-+ }
-+ regmap_write(gmac->regmap, SYSCON_EMAC_REG, val);
-+ if (need_power_ephy) {
-+ ret = sun8i_dwmac_power_internal_phy(priv);
-+ if (ret)
-+ return ret;
-+ } else {
-+ sun8i_dwmac_unpower_internal_phy(gmac);
-+ }
-+ /* After changing syscon value, the MAC need reset or it will
-+ * use the last value (and so the last PHY set).
-+ */
-+ ret = sun8i_dwmac_reset(priv);
-+ }
-+ return ret;
-+}
-+
-+static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)
-+{
-+ int ret;
-+ struct device_node *mdio_mux;
-+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
-+
-+ mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
-+ if (!mdio_mux)
-+ return -ENODEV;
-+
-+ ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
-+ &gmac->mux_handle, priv, priv->mii);
-+ return ret;
-+}
-+
- static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
- {
- struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
-@@ -649,35 +808,25 @@ static int sun8i_dwmac_set_syscon(struct
- "Current syscon value is not the default %x (expect %x)\n",
- val, reg);
-
-- if (gmac->variant->internal_phy) {
-- if (!gmac->use_internal_phy) {
-- /* switch to external PHY interface */
-- reg &= ~H3_EPHY_SELECT;
-- } else {
-- reg |= H3_EPHY_SELECT;
-- reg &= ~H3_EPHY_SHUTDOWN;
-- dev_dbg(priv->device, "Select internal_phy %x\n", reg);
--
-- if (of_property_read_bool(priv->plat->phy_node,
-- "allwinner,leds-active-low"))
-- reg |= H3_EPHY_LED_POL;
-- else
-- reg &= ~H3_EPHY_LED_POL;
--
-- /* Force EPHY xtal frequency to 24MHz. */
-- reg |= H3_EPHY_CLK_SEL;
--
-- ret = of_mdio_parse_addr(priv->device,
-- priv->plat->phy_node);
-- if (ret < 0) {
-- dev_err(priv->device, "Could not parse MDIO addr\n");
-- return ret;
-- }
-- /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
-- * address. No need to mask it again.
-- */
-- reg |= ret << H3_EPHY_ADDR_SHIFT;
-+ if (gmac->variant->soc_has_internal_phy) {
-+ if (of_property_read_bool(priv->plat->phy_node,
-+ "allwinner,leds-active-low"))
-+ reg |= H3_EPHY_LED_POL;
-+ else
-+ reg &= ~H3_EPHY_LED_POL;
-+
-+ /* Force EPHY xtal frequency to 24MHz. */
-+ reg |= H3_EPHY_CLK_SEL;
-+
-+ ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node);
-+ if (ret < 0) {
-+ dev_err(priv->device, "Could not parse MDIO addr\n");
-+ return ret;
- }
-+ /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
-+ * address. No need to mask it again.
-+ */
-+ reg |= 1 << H3_EPHY_ADDR_SHIFT;
- }
-
- if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
-@@ -750,81 +899,21 @@ static void sun8i_dwmac_unset_syscon(str
- regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
- }
-
--static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
-+static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
- {
-- struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
-- int ret;
--
-- if (!gmac->use_internal_phy)
-- return 0;
-+ struct sunxi_priv_data *gmac = priv;
-
-- ret = clk_prepare_enable(gmac->ephy_clk);
-- if (ret) {
-- dev_err(priv->device, "Cannot enable ephy\n");
-- return ret;
-+ if (gmac->variant->soc_has_internal_phy) {
-+ /* sun8i_dwmac_exit could be called with mdiomux uninit */
-+ if (gmac->mux_handle)
-+ mdio_mux_uninit(gmac->mux_handle);
-+ if (gmac->internal_phy_powered)
-+ sun8i_dwmac_unpower_internal_phy(gmac);
- }
-
-- /* Make sure the EPHY is properly reseted, as U-Boot may leave
-- * it at deasserted state, and thus it may fail to reset EMAC.
-- */
-- reset_control_assert(gmac->rst_ephy);
--
-- ret = reset_control_deassert(gmac->rst_ephy);
-- if (ret) {
-- dev_err(priv->device, "Cannot deassert ephy\n");
-- clk_disable_unprepare(gmac->ephy_clk);
-- return ret;
-- }
--
-- return 0;
--}
--
--static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
--{
-- if (!gmac->use_internal_phy)
-- return 0;
--
-- clk_disable_unprepare(gmac->ephy_clk);
-- reset_control_assert(gmac->rst_ephy);
-- return 0;
--}
--
--/* sun8i_power_phy() - Activate the PHY:
-- * In case of error, no need to call sun8i_unpower_phy(),
-- * it will be called anyway by sun8i_dwmac_exit()
-- */
--static int sun8i_power_phy(struct stmmac_priv *priv)
--{
-- int ret;
--
-- ret = sun8i_dwmac_power_internal_phy(priv);
-- if (ret)
-- return ret;
--
-- ret = sun8i_dwmac_set_syscon(priv);
-- if (ret)
-- return ret;
--
-- /* After changing syscon value, the MAC need reset or it will use
-- * the last value (and so the last PHY set.
-- */
-- ret = sun8i_dwmac_reset(priv);
-- if (ret)
-- return ret;
-- return 0;
--}
--
--static void sun8i_unpower_phy(struct sunxi_priv_data *gmac)
--{
- sun8i_dwmac_unset_syscon(gmac);
-- sun8i_dwmac_unpower_internal_phy(gmac);
--}
--
--static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
--{
-- struct sunxi_priv_data *gmac = priv;
-
-- sun8i_unpower_phy(gmac);
-+ reset_control_put(gmac->rst_ephy);
-
- clk_disable_unprepare(gmac->tx_clk);
-
-@@ -853,7 +942,7 @@ static struct mac_device_info *sun8i_dwm
- if (!mac)
- return NULL;
-
-- ret = sun8i_power_phy(priv);
-+ ret = sun8i_dwmac_set_syscon(priv);
- if (ret)
- return NULL;
-
-@@ -895,6 +984,8 @@ static int sun8i_dwmac_probe(struct plat
- struct sunxi_priv_data *gmac;
- struct device *dev = &pdev->dev;
- int ret;
-+ struct stmmac_priv *priv;
-+ struct net_device *ndev;
-
- ret = stmmac_get_platform_resources(pdev, &stmmac_res);
- if (ret)
-@@ -938,29 +1029,6 @@ static int sun8i_dwmac_probe(struct plat
- }
-
- plat_dat->interface = of_get_phy_mode(dev->of_node);
-- if (plat_dat->interface == gmac->variant->internal_phy) {
-- dev_info(&pdev->dev, "Will use internal PHY\n");
-- gmac->use_internal_phy = true;
-- gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
-- if (IS_ERR(gmac->ephy_clk)) {
-- ret = PTR_ERR(gmac->ephy_clk);
-- dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret);
-- return -EINVAL;
-- }
--
-- gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
-- if (IS_ERR(gmac->rst_ephy)) {
-- ret = PTR_ERR(gmac->rst_ephy);
-- if (ret == -EPROBE_DEFER)
-- return ret;
-- dev_err(&pdev->dev, "No EPHY reset control found %d\n",
-- ret);
-- return -EINVAL;
-- }
-- } else {
-- dev_info(&pdev->dev, "Will use external PHY\n");
-- gmac->use_internal_phy = false;
-- }
-
- /* platform data specifying hardware features and callbacks.
- * hardware features were copied from Allwinner drivers.
-@@ -979,9 +1047,34 @@ static int sun8i_dwmac_probe(struct plat
-
- ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
- if (ret)
-- sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
-+ goto dwmac_exit;
-+
-+ ndev = dev_get_drvdata(&pdev->dev);
-+ priv = netdev_priv(ndev);
-+ /* The mux must be registered after parent MDIO
-+ * so after stmmac_dvr_probe()
-+ */
-+ if (gmac->variant->soc_has_internal_phy) {
-+ ret = get_ephy_nodes(priv);
-+ if (ret)
-+ goto dwmac_exit;
-+ ret = sun8i_dwmac_register_mdio_mux(priv);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Failed to register mux\n");
-+ goto dwmac_mux;
-+ }
-+ } else {
-+ ret = sun8i_dwmac_reset(priv);
-+ if (ret)
-+ goto dwmac_exit;
-+ }
-
- return ret;
-+dwmac_mux:
-+ sun8i_dwmac_unset_syscon(gmac);
-+dwmac_exit:
-+ sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
-+return ret;
- }
-
- static const struct of_device_id sun8i_dwmac_match[] = {
+++ /dev/null
-From a8ff8ccb45d37efa64476958fc5e9a8d9716b23b Mon Sep 17 00:00:00 2001
-From: Corentin Labbe <clabbe.montjoie@gmail.com>
-Date: Tue, 24 Oct 2017 19:57:14 +0200
-Subject: [PATCH] net: stmmac: sun8i: Restore the compatibles
-
-The original dwmac-sun8i DT bindings have some issue on how to handle
-integrated PHY and was reverted in last RC of 4.13.
-But now we have a solution so we need to get back that was reverted.
-
-This patch restore compatibles about dwmac-sun8i
-This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles")
-
-Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
-@@ -1078,6 +1078,14 @@ return ret;
- }
-
- static const struct of_device_id sun8i_dwmac_match[] = {
-+ { .compatible = "allwinner,sun8i-h3-emac",
-+ .data = &emac_variant_h3 },
-+ { .compatible = "allwinner,sun8i-v3s-emac",
-+ .data = &emac_variant_v3s },
-+ { .compatible = "allwinner,sun8i-a83t-emac",
-+ .data = &emac_variant_a83t },
-+ { .compatible = "allwinner,sun50i-a64-emac",
-+ .data = &emac_variant_a64 },
- { }
- };
- MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
+++ /dev/null
-From 1c08ac0c4bd8e9d66c4dde29bc496c3b430dd028 Mon Sep 17 00:00:00 2001
-From: Corentin Labbe <clabbe.montjoie@gmail.com>
-Date: Tue, 28 Nov 2017 17:48:22 +0100
-Subject: net: stmmac: dwmac-sun8i: fix allwinner,leds-active-low handling
-
-The driver expect "allwinner,leds-active-low" to be in PHY node, but
-the binding doc expect it to be in MAC node.
-
-Since all board DT use it also in MAC node, the driver need to search
-allwinner,leds-active-low in MAC node.
-
-Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
-@@ -809,8 +809,7 @@ static int sun8i_dwmac_set_syscon(struct
- val, reg);
-
- if (gmac->variant->soc_has_internal_phy) {
-- if (of_property_read_bool(priv->plat->phy_node,
-- "allwinner,leds-active-low"))
-+ if (of_property_read_bool(node, "allwinner,leds-active-low"))
- reg |= H3_EPHY_LED_POL;
- else
- reg &= ~H3_EPHY_LED_POL;
+++ /dev/null
-From 4904337fe34fa7fc529d6f4d9ee8b96fe7db310a Mon Sep 17 00:00:00 2001
-From: Corentin Labbe <clabbe.montjoie@gmail.com>
-Date: Tue, 31 Oct 2017 09:19:12 +0100
-Subject: [PATCH] ARM: dts: sunxi: Restore EMAC changes (boards)
-
-The original dwmac-sun8i DT bindings have some issue on how to handle
-integrated PHY and was reverted in last RC of 4.13.
-But now we have a solution so we need to get back that was reverted.
-
-This patch restore all boards DT about dwmac-sun8i
-This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
-
-Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 +++++++
- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++
- arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 29 +++++++++++++++++++++++
- arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++++++
- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++++++
- arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++++++
- arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 ++++
- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 +++++++
- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++++++++++++++++
- arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 +++++++++++++
- 10 files changed, 131 insertions(+)
-
---- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
-+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
-@@ -56,6 +56,8 @@
-
- aliases {
- serial0 = &uart0;
-+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
-+ ethernet0 = &emac;
- ethernet1 = &xr819;
- };
-
-@@ -102,6 +104,13 @@
- status = "okay";
- };
-
-+&emac {
-+ phy-handle = <&int_mii_phy>;
-+ phy-mode = "mii";
-+ allwinner,leds-active-low;
-+ status = "okay";
-+};
-+
- &mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
---- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
-@@ -52,6 +52,7 @@
- compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
-
- aliases {
-+ ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- };
-@@ -114,6 +115,24 @@
- status = "okay";
- };
-
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+
-+ allwinner,leds-active-low;
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <0>;
-+ };
-+};
-+
- &ir {
- pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
---- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
-@@ -45,6 +45,16 @@
- / {
- model = "FriendlyArm NanoPi M1 Plus";
- compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3";
-+
-+ reg_gmac_3v3: gmac-3v3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "gmac-3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <100000>;
-+ enable-active-high;
-+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
-+ };
- };
-
- &ehci1 {
-@@ -55,6 +65,25 @@
- status = "okay";
- };
-
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+
-+ allwinner,leds-active-low;
-+
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <7>;
-+ };
-+};
-+
- &ohci1 {
- status = "okay";
- };
---- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
-@@ -46,3 +46,10 @@
- model = "FriendlyARM NanoPi NEO";
- compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
- };
-+
-+&emac {
-+ phy-handle = <&int_mii_phy>;
-+ phy-mode = "mii";
-+ allwinner,leds-active-low;
-+ status = "okay";
-+};
---- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
-@@ -54,6 +54,7 @@
- aliases {
- serial0 = &uart0;
- /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
-+ ethernet0 = &emac;
- ethernet1 = &rtl8189;
- };
-
-@@ -117,6 +118,13 @@
- status = "okay";
- };
-
-+&emac {
-+ phy-handle = <&int_mii_phy>;
-+ phy-mode = "mii";
-+ allwinner,leds-active-low;
-+ status = "okay";
-+};
-+
- &ir {
- pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
---- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
-@@ -52,6 +52,7 @@
- compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
-
- aliases {
-+ ethernet0 = &emac;
- serial0 = &uart0;
- };
-
-@@ -97,6 +98,13 @@
- status = "okay";
- };
-
-+&emac {
-+ phy-handle = <&int_mii_phy>;
-+ phy-mode = "mii";
-+ allwinner,leds-active-low;
-+ status = "okay";
-+};
-+
- &mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
---- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
-@@ -53,6 +53,11 @@
- };
- };
-
-+&emac {
-+ /* LEDs changed to active high on the plus */
-+ /delete-property/ allwinner,leds-active-low;
-+};
-+
- &mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
---- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
-@@ -52,6 +52,7 @@
- compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
-
- aliases {
-+ ethernet0 = &emac;
- serial0 = &uart0;
- };
-
-@@ -113,6 +114,13 @@
- status = "okay";
- };
-
-+&emac {
-+ phy-handle = <&int_mii_phy>;
-+ phy-mode = "mii";
-+ allwinner,leds-active-low;
-+ status = "okay";
-+};
-+
- &ir {
- pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
---- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
-@@ -47,6 +47,10 @@
- model = "Xunlong Orange Pi Plus / Plus 2";
- compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
-
-+ aliases {
-+ ethernet0 = &emac;
-+ };
-+
- reg_gmac_3v3: gmac-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "gmac-3v3";
-@@ -74,6 +78,24 @@
- status = "okay";
- };
-
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+
-+ allwinner,leds-active-low;
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <0>;
-+ };
-+};
-+
- &mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
---- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
-@@ -61,3 +61,19 @@
- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
- };
- };
-+
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
+++ /dev/null
-From 4b236a0fe51259ccde06aed046fe20bfe6e25dce Mon Sep 17 00:00:00 2001
-From: Corentin Labbe <clabbe.montjoie@gmail.com>
-Date: Tue, 31 Oct 2017 09:19:10 +0100
-Subject: [PATCH] arm: dts: sunxi: h3/h5: Restore EMAC changes
-
-The original dwmac-sun8i DT bindings have some issue on how to handle
-integrated PHY and was reverted in last RC of 4.13.
-But now we have a solution so we need to get back that was reverted.
-
-This patch restore sunxi-h3-h5.dtsi
-This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
-
-Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
-+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
-@@ -391,6 +391,32 @@
- clocks = <&osc24M>;
- };
-
-+ emac: ethernet@1c30000 {
-+ compatible = "allwinner,sun8i-h3-emac";
-+ syscon = <&syscon>;
-+ reg = <0x01c30000 0x10000>;
-+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "macirq";
-+ resets = <&ccu RST_BUS_EMAC>;
-+ reset-names = "stmmaceth";
-+ clocks = <&ccu CLK_BUS_EMAC>;
-+ clock-names = "stmmaceth";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ mdio: mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ int_mii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ clocks = <&ccu CLK_BUS_EPHY>;
-+ resets = <&ccu RST_BUS_EPHY>;
-+ };
-+ };
-+ };
-+
- spi0: spi@01c68000 {
- compatible = "allwinner,sun8i-h3-spi";
- reg = <0x01c68000 0x1000>;
+++ /dev/null
-From 776245ae02f63ba2b94596b892c597676e190e78 Mon Sep 17 00:00:00 2001
-From: Corentin Labbe <clabbe.montjoie@gmail.com>
-Date: Tue, 31 Oct 2017 09:19:11 +0100
-Subject: [PATCH] ARM: dts: sunxi: h3/h5: represent the mdio switch used by
- sun8i-h3-emac
-
-Since dwmac-sun8i could use either an integrated PHY or an external PHY
-(which could be at same MDIO address), we need to represent this selection
-by a MDIO switch.
-
-Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +++++++++++++++++++++++++++----
- 1 file changed, 27 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
-+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
-@@ -408,11 +408,34 @@
- mdio: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-- int_mii_phy: ethernet-phy@1 {
-- compatible = "ethernet-phy-ieee802.3-c22";
-+ compatible = "snps,dwmac-mdio";
-+ };
-+
-+ mdio-mux {
-+ compatible = "allwinner,sun8i-h3-mdio-mux";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ mdio-parent-bus = <&mdio>;
-+ /* Only one MDIO is usable at the time */
-+ internal_mdio: mdio@1 {
-+ compatible = "allwinner,sun8i-h3-mdio-internal";
- reg = <1>;
-- clocks = <&ccu CLK_BUS_EPHY>;
-- resets = <&ccu RST_BUS_EPHY>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ int_mii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ clocks = <&ccu CLK_BUS_EPHY>;
-+ resets = <&ccu RST_BUS_EPHY>;
-+ };
-+ };
-+
-+ external_mdio: mdio@2 {
-+ reg = <2>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
- };
- };
- };
+++ /dev/null
-From 94f442886711c6c4f4383a1c5a6994a788ba05d8 Mon Sep 17 00:00:00 2001
-From: Corentin Labbe <clabbe.montjoie@gmail.com>
-Date: Tue, 31 Oct 2017 09:19:13 +0100
-Subject: [PATCH] arm64: dts: allwinner: A64: Restore EMAC changes
-
-The original dwmac-sun8i DT bindings have some issue on how to handle
-integrated PHY and was reverted in last RC of 4.13.
-But now we have a solution so we need to get back that was reverted.
-
-This patch restore arm64 DT about dwmac-sun8i for A64
-This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
-
-Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++++++++++++++++
- .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 +++++++++++++++
- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +++++++++++++++++
- .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++++++++++++++++
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 ++++++++++++++++++++
- 5 files changed, 84 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
-@@ -51,6 +51,7 @@
- compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
-
- aliases {
-+ ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- };
-@@ -69,6 +70,14 @@
- status = "okay";
- };
-
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&rgmii_pins>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&ext_rgmii_phy>;
-+ status = "okay";
-+};
-+
- &i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
-@@ -79,6 +88,13 @@
- bias-pull-up;
- };
-
-+&mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
-+
- &mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>;
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
-@@ -48,3 +48,18 @@
-
- /* TODO: Camera, touchscreen, etc. */
- };
-+
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&rgmii_pins>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&ext_rgmii_phy>;
-+ status = "okay";
-+};
-+
-+&mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
-@@ -51,6 +51,7 @@
- compatible = "pine64,pine64", "allwinner,sun50i-a64";
-
- aliases {
-+ ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
-@@ -71,6 +72,15 @@
- status = "okay";
- };
-
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&rmii_pins>;
-+ phy-mode = "rmii";
-+ phy-handle = <&ext_rmii_phy1>;
-+ status = "okay";
-+
-+};
-+
- &i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
-@@ -81,6 +91,13 @@
- bias-pull-up;
- };
-
-+&mdio {
-+ ext_rmii_phy1: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
-+
- &mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>;
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
-@@ -53,6 +53,7 @@
- "allwinner,sun50i-a64";
-
- aliases {
-+ ethernet0 = &emac;
- serial0 = &uart0;
- };
-
-@@ -76,6 +77,21 @@
- status = "okay";
- };
-
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&rgmii_pins>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&ext_rgmii_phy>;
-+ status = "okay";
-+};
-+
-+&mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
-+
- &mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins>;
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -450,6 +450,26 @@
- #size-cells = <0>;
- };
-
-+ emac: ethernet@1c30000 {
-+ compatible = "allwinner,sun50i-a64-emac";
-+ syscon = <&syscon>;
-+ reg = <0x01c30000 0x10000>;
-+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "macirq";
-+ resets = <&ccu RST_BUS_EMAC>;
-+ reset-names = "stmmaceth";
-+ clocks = <&ccu CLK_BUS_EMAC>;
-+ clock-names = "stmmaceth";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ mdio: mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+ };
-+
- gic: interrupt-controller@1c81000 {
- compatible = "arm,gic-400";
- reg = <0x01c81000 0x1000>,
+++ /dev/null
-From 16416084e06e1ebff51a9e7721a8cc4ccc186f28 Mon Sep 17 00:00:00 2001
-From: Corentin Labbe <clabbe.montjoie@gmail.com>
-Date: Tue, 31 Oct 2017 09:19:15 +0100
-Subject: [PATCH] arm64: dts: allwinner: add snps,dwmac-mdio compatible to
- emac/mdio
-
-stmmac bindings docs said that its mdio node must have
-compatible = "snps,dwmac-mdio";
-Since dwmac-sun8i does not have any good reasons to not doing it, all
-their MDIO node must have it.
-
-Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -465,6 +465,7 @@
- #size-cells = <0>;
-
- mdio: mdio {
-+ compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- };
+++ /dev/null
-From 44a94c7ef989317de81e3e7f84385be2bf1b5fe2 Mon Sep 17 00:00:00 2001
-From: Corentin Labbe <clabbe.montjoie@gmail.com>
-Date: Tue, 31 Oct 2017 09:19:14 +0100
-Subject: [PATCH] arm64: dts: allwinner: H5: Restore EMAC changes
-
-The original dwmac-sun8i DT bindings have some issue on how to handle
-integrated PHY and was reverted in last RC of 4.13.
-But now we have a solution so we need to get back that was reverted.
-
-This patch restore arm64 DT about dwmac-sun8i for H5
-This reverts a part of commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
-
-Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +++++++++++++++++
- .../arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 +++++++++++++++++
- .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +++++++++++++++++
- 3 files changed, 51 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
-@@ -50,6 +50,7 @@
- compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
-
- aliases {
-+ ethernet0 = &emac;
- serial0 = &uart0;
- };
-
-@@ -108,6 +109,22 @@
- status = "okay";
- };
-
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@7 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <7>;
-+ };
-+};
-+
- &mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
-@@ -59,6 +59,7 @@
- };
-
- aliases {
-+ ethernet0 = &emac;
- serial0 = &uart0;
- };
-
-@@ -136,6 +137,22 @@
- status = "okay";
- };
-
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
-+
- &ir {
- pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
-@@ -54,6 +54,7 @@
- compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
-
- aliases {
-+ ethernet0 = &emac;
- serial0 = &uart0;
- };
-
-@@ -143,6 +144,22 @@
- status = "okay";
- };
-
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
-+
- &ir {
- pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
+++ /dev/null
-From bdfe4cebea11476d278b1b98dd0f7cdac8269d62 Mon Sep 17 00:00:00 2001
-From: Icenowy Zheng <icenowy@aosc.io>
-Date: Fri, 10 Nov 2017 17:26:54 +0800
-Subject: [PATCH] arm64: allwinner: a64: add Ethernet PHY regulator for several
- boards
-
-On several A64 boards the Ethernet PHY is powered by the DC1SW regulator
-on the AXP803 PMIC.
-
-Add phy-handle property to these boards' emac node.
-
-Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
-Acked-by: Corentin LABBE <clabbe.montjoie@gmail.com>
-Tested-by: Corentin LABBE <clabbe.montjoie@gmail.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 1 +
- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 1 +
- arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 1 +
- 3 files changed, 3 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
-@@ -75,6 +75,7 @@
- pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
- phy-handle = <&ext_rgmii_phy>;
-+ phy-supply = <®_dc1sw>;
- status = "okay";
- };
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
-@@ -77,6 +77,7 @@
- pinctrl-0 = <&rmii_pins>;
- phy-mode = "rmii";
- phy-handle = <&ext_rmii_phy1>;
-+ phy-supply = <®_dc1sw>;
- status = "okay";
-
- };
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
-@@ -82,6 +82,7 @@
- pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
- phy-handle = <&ext_rgmii_phy>;
-+ phy-supply = <®_dc1sw>;
- status = "okay";
- };
-
+++ /dev/null
-From f2e600c149fda3453344f89c7e9353fe278ebd32 Mon Sep 17 00:00:00 2001
-From: Christoffer Dall <christoffer.dall@linaro.org>
-Date: Wed, 18 Oct 2017 13:06:25 +0200
-Subject: [PATCH] arm64: Implement arch_counter_get_cntpct to read the physical
- counter
-
-As we are about to use the physical counter on arm64 systems that have
-KVM support, implement arch_counter_get_cntpct() and the associated
-errata workaround functionality for stable timer reads.
-
-Cc: Will Deacon <will.deacon@arm.com>
-Cc: Mark Rutland <mark.rutland@arm.com>
-Acked-by: Catalin Marinas <catalin.marinas@arm.com>
-Acked-by: Marc Zyngier <marc.zyngier@arm.com>
-Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
----
- arch/arm64/include/asm/arch_timer.h | 8 +++-----
- drivers/clocksource/arm_arch_timer.c | 23 +++++++++++++++++++++++
- 2 files changed, 26 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/include/asm/arch_timer.h
-+++ b/arch/arm64/include/asm/arch_timer.h
-@@ -52,6 +52,7 @@ struct arch_timer_erratum_workaround {
- const char *desc;
- u32 (*read_cntp_tval_el0)(void);
- u32 (*read_cntv_tval_el0)(void);
-+ u64 (*read_cntpct_el0)(void);
- u64 (*read_cntvct_el0)(void);
- int (*set_next_event_phys)(unsigned long, struct clock_event_device *);
- int (*set_next_event_virt)(unsigned long, struct clock_event_device *);
-@@ -148,11 +149,8 @@ static inline void arch_timer_set_cntkct
-
- static inline u64 arch_counter_get_cntpct(void)
- {
-- /*
-- * AArch64 kernel and user space mandate the use of CNTVCT.
-- */
-- BUG();
-- return 0;
-+ isb();
-+ return arch_timer_reg_read_stable(cntpct_el0);
- }
-
- static inline u64 arch_counter_get_cntvct(void)
---- a/drivers/clocksource/arm_arch_timer.c
-+++ b/drivers/clocksource/arm_arch_timer.c
-@@ -217,6 +217,11 @@ static u32 notrace fsl_a008585_read_cntv
- return __fsl_a008585_read_reg(cntv_tval_el0);
- }
-
-+static u64 notrace fsl_a008585_read_cntpct_el0(void)
-+{
-+ return __fsl_a008585_read_reg(cntpct_el0);
-+}
-+
- static u64 notrace fsl_a008585_read_cntvct_el0(void)
- {
- return __fsl_a008585_read_reg(cntvct_el0);
-@@ -258,6 +263,11 @@ static u32 notrace hisi_161010101_read_c
- return __hisi_161010101_read_reg(cntv_tval_el0);
- }
-
-+static u64 notrace hisi_161010101_read_cntpct_el0(void)
-+{
-+ return __hisi_161010101_read_reg(cntpct_el0);
-+}
-+
- static u64 notrace hisi_161010101_read_cntvct_el0(void)
- {
- return __hisi_161010101_read_reg(cntvct_el0);
-@@ -288,6 +298,15 @@ static struct ate_acpi_oem_info hisi_161
- #endif
-
- #ifdef CONFIG_ARM64_ERRATUM_858921
-+static u64 notrace arm64_858921_read_cntpct_el0(void)
-+{
-+ u64 old, new;
-+
-+ old = read_sysreg(cntpct_el0);
-+ new = read_sysreg(cntpct_el0);
-+ return (((old ^ new) >> 32) & 1) ? old : new;
-+}
-+
- static u64 notrace arm64_858921_read_cntvct_el0(void)
- {
- u64 old, new;
-@@ -346,6 +365,7 @@ static const struct arch_timer_erratum_w
- .desc = "Freescale erratum a005858",
- .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
- .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
-+ .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
- .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
- .set_next_event_phys = erratum_set_next_event_tval_phys,
- .set_next_event_virt = erratum_set_next_event_tval_virt,
-@@ -358,6 +378,7 @@ static const struct arch_timer_erratum_w
- .desc = "HiSilicon erratum 161010101",
- .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
- .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
-+ .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
- .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
- .set_next_event_phys = erratum_set_next_event_tval_phys,
- .set_next_event_virt = erratum_set_next_event_tval_virt,
-@@ -368,6 +389,7 @@ static const struct arch_timer_erratum_w
- .desc = "HiSilicon erratum 161010101",
- .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
- .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
-+ .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
- .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
- .set_next_event_phys = erratum_set_next_event_tval_phys,
- .set_next_event_virt = erratum_set_next_event_tval_virt,
-@@ -378,6 +400,7 @@ static const struct arch_timer_erratum_w
- .match_type = ate_match_local_cap_id,
- .id = (void *)ARM64_WORKAROUND_858921,
- .desc = "ARM erratum 858921",
-+ .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
- .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
- },
- #endif
+++ /dev/null
-From d41850437c364ef7aba9bc25c1c701699d0240e0 Mon Sep 17 00:00:00 2001
-From: Harald Geyer <harald@ccbib.org>
-Date: Thu, 15 Mar 2018 16:25:07 +0000
-Subject: [PATCH] arm64: dts: allwinner: a64: Add watchdog
-
-Add a watchdog node for the A64, automatically enabled on all boards.
-Since the device is compatible with an existing driver, we only reserve
-a new compatible string to be used together with the fall back.
-Tested on Olimex Teres-I.
-
-Signed-off-by: Harald Geyer <harald@ccbib.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
----
- Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 6 ++++--
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 7 +++++++
- 2 files changed, 11 insertions(+), 2 deletions(-)
-
---- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
-+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
-@@ -2,8 +2,10 @@ Allwinner SoCs Watchdog timer
-
- Required properties:
-
--- compatible : should be either "allwinner,sun4i-a10-wdt" or
-- "allwinner,sun6i-a31-wdt"
-+- compatible : should be one of
-+ "allwinner,sun4i-a10-wdt"
-+ "allwinner,sun6i-a31-wdt"
-+ "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt"
- - reg : Specifies base physical address and size of the registers.
-
- Example:
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -538,5 +538,12 @@
- #address-cells = <1>;
- #size-cells = <0>;
- };
-+
-+ wdt0: watchdog@1c20ca0 {
-+ compatible = "allwinner,sun50i-a64-wdt",
-+ "allwinner,sun6i-a31-wdt";
-+ reg = <0x01c20ca0 0x20>;
-+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-+ };
- };
- };
+++ /dev/null
-From 74942cd5dfe4ac4fd982fe58118bc69346a2bd18 Mon Sep 17 00:00:00 2001
-From: Icenowy Zheng <icenowy@aosc.io>
-Date: Sun, 12 Nov 2017 20:41:29 +0800
-Subject: [PATCH] ARM: dts: sun8i: add support for Orange Pi R1
-
-Orange Pi R1 is a board design based on Orange Pi Zero, with XR819 Wi-Fi
-chip replaced by RTL8189ETV Wi-Fi module and the USB Type-A jack
-replaced by an onboard USB RTL8152B USB-Ethernet adapter.
-
-Add support for it.
-
-Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts | 73 +++++++++++++++++++++++++
- 2 files changed, 74 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -916,6 +916,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
- sun8i-a83t-allwinner-h8homlet-v2.dtb \
- sun8i-a83t-bananapi-m3.dtb \
- sun8i-a83t-cubietruck-plus.dtb \
-+ sun8i-h2-plus-orangepi-r1.dtb \
- sun8i-h2-plus-orangepi-zero.dtb \
- sun8i-h3-bananapi-m2-plus.dtb \
- sun8i-h3-beelink-x2.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
-@@ -0,0 +1,73 @@
-+/*
-+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ * a) This file is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This file is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ * b) Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation
-+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use,
-+ * copy, modify, merge, publish, distribute, sublicense, and/or
-+ * sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following
-+ * conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+/* Orange Pi R1 is based on Orange Pi Zero design */
-+#include "sun8i-h2-plus-orangepi-zero.dts"
-+
-+/ {
-+ model = "Xunlong Orange Pi R1";
-+ compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus";
-+
-+ /delete-node/ reg_vcc_wifi;
-+
-+ aliases {
-+ ethernet1 = &rtl8189etv;
-+ };
-+};
-+
-+&ohci1 {
-+ /*
-+ * RTL8152B USB-Ethernet adapter is connected to USB1,
-+ * and it's a USB 2.0 device. So the OHCI1 controller
-+ * can be left disabled.
-+ */
-+ status = "disabled";
-+};
-+
-+&mmc1 {
-+ vmmc-supply = <®_vcc3v3>;
-+ vqmmc-supply = <®_vcc3v3>;
-+
-+ rtl8189etv: sdio_wifi@1 {
-+ reg = <1>;
-+ };
-+};
+++ /dev/null
-From 54cc3330c2334a0cea8cafc105a29c5d67f9fd32 Mon Sep 17 00:00:00 2001
-From: Antony Antony <antony@phenome.org>
-Date: Fri, 2 Mar 2018 10:50:48 +0100
-Subject: [PATCH] arm64: allwinner: h5: add NanoPi NEO Plus2 DT support
-
-Add initial DT for NanoPi NEO Plus2 by FriendlyARM
-- Allwinner quad core H5 Cortex A53 with an ARM Mali-450MP GPU
-- 1 GB DDR3 RAM
-- 8GB eMMC flash (Samsung KLM8G1WEPD-B031)
-- micro SD card slot
-- Gigabit Ethernet (external RTL8211E-VB-CG chip)
-- 802.11 b/g/n WiFi, Bluetooth 4.0 (Ampak AP6212A module)
-- 2x USB 2.0 host ports & 2x USB via headers
-
-Kernel 4.15 commit d7341305863b
-Kernel 4.16 commit 27d7f9297027
-
-Signed-off-by: Antony Antony <antony@phenome.org>
-
---- a/arch/arm64/boot/dts/allwinner/Makefile
-+++ b/arch/arm64/boot/dts/allwinner/Makefile
-@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-or
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
-
- always := $(dtb-y)
- subdir-y := $(dts-dirs)
---- /dev/null
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
-@@ -0,0 +1,210 @@
-+/*
-+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
-+ * Copyright (C) 2016 ARM Ltd.
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ * a) This file is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This file is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ * b) Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation
-+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use,
-+ * copy, modify, merge, publish, distribute, sublicense, and/or
-+ * sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following
-+ * conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+/dts-v1/;
-+#include "sun50i-h5.dtsi"
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/pinctrl/sun4i-a10.h>
-+
-+/ {
-+ model = "FriendlyARM NanoPi NEO Plus2";
-+ compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
-+
-+ aliases {
-+ ethernet0 = &emac;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ pwr {
-+ label = "nanopi:green:pwr";
-+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ };
-+
-+ status {
-+ label = "nanopi:red:status";
-+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+
-+ reg_gmac_3v3: gmac-3v3 {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ regulator-name = "gmac-3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <100000>;
-+ enable-active-high;
-+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ reg_vcc3v3: vcc3v3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ vdd_cpux: gpio-regulator {
-+ compatible = "regulator-gpio";
-+ pinctrl-names = "default";
-+ regulator-name = "vdd-cpux";
-+ regulator-type = "voltage";
-+ regulator-boot-on;
-+ regulator-always-on;
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1300000>;
-+ regulator-ramp-delay = <50>; /* 4ms */
-+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
-+ gpios-states = <0x1>;
-+ states = <1100000 0x0
-+ 1300000 0x1>;
-+ };
-+
-+ wifi_pwrseq: wifi_pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ pinctrl-names = "default";
-+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
-+ post-power-on-delay-ms = <200>;
-+ };
-+};
-+
-+&codec {
-+ allwinner,audio-routing =
-+ "Line Out", "LINEOUT",
-+ "MIC1", "Mic",
-+ "Mic", "MBIAS";
-+ status = "okay";
-+};
-+
-+&ehci0 {
-+ status = "okay";
-+};
-+
-+&ehci3 {
-+ status = "okay";
-+};
-+
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@7 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <7>;
-+ };
-+};
-+
-+&mmc0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
-+ vmmc-supply = <®_vcc3v3>;
-+ bus-width = <4>;
-+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-+ status = "okay";
-+};
-+
-+&mmc1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mmc1_pins_a>;
-+ vmmc-supply = <®_vcc3v3>;
-+ vqmmc-supply = <®_vcc3v3>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ bus-width = <4>;
-+ non-removable;
-+ status = "okay";
-+
-+ brcmf: wifi@1 {
-+ reg = <1>;
-+ compatible = "brcm,bcm4329-fmac";
-+ };
-+};
-+
-+&mmc2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mmc2_8bit_pins>;
-+ vmmc-supply = <®_vcc3v3>;
-+ bus-width = <8>;
-+ non-removable;
-+ cap-mmc-hw-reset;
-+ status = "okay";
-+};
-+
-+&ohci0 {
-+ status = "okay";
-+};
-+
-+&ohci3 {
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_pins_a>;
-+ status = "okay";
-+};
-+
-+&usb_otg {
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ /* USB Type-A ports' VBUS is always on */
-+ status = "okay";
-+};
+++ /dev/null
-From b518bb159032aac33503fd4cf98706dc84cc1266 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Stefan=20Br=C3=BCns?= <stefan.bruens@rwth-aachen.de>
-Date: Thu, 31 Aug 2017 01:06:37 +0200
-Subject: [PATCH] arm64: allwinner: a64: add SPI nodes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The A64 SPI controllers are register compatible to the h3/h5 SPI
-controllers.
-
-The A64 has two SPI controllers, each with a single chip select.
-The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted,
-as the A64 DMA support is currently missing.
-
-Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 41 +++++++++++++++++++
- 1 file changed, 41 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -326,6 +326,16 @@
- drive-strength = <40>;
- };
-
-+ spi0_pins: spi0 {
-+ pins = "PC0", "PC1", "PC2", "PC3";
-+ function = "spi0";
-+ };
-+
-+ spi1_pins: spi1 {
-+ pins = "PD0", "PD1", "PD2", "PD3";
-+ function = "spi1";
-+ };
-+
- uart0_pins_a: uart0@0 {
- pins = "PB8", "PB9";
- function = "uart0";
-@@ -471,6 +481,37 @@
- };
- };
-
-+
-+ spi0: spi@01c68000 {
-+ compatible = "allwinner,sun8i-h3-spi";
-+ reg = <0x01c68000 0x1000>;
-+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
-+ clock-names = "ahb", "mod";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi0_pins>;
-+ resets = <&ccu RST_BUS_SPI0>;
-+ status = "disabled";
-+ num-cs = <1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ spi1: spi@01c69000 {
-+ compatible = "allwinner,sun8i-h3-spi";
-+ reg = <0x01c69000 0x1000>;
-+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
-+ clock-names = "ahb", "mod";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi1_pins>;
-+ resets = <&ccu RST_BUS_SPI1>;
-+ status = "disabled";
-+ num-cs = <1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- gic: interrupt-controller@1c81000 {
- compatible = "arm,gic-400";
- reg = <0x01c81000 0x1000>,
+++ /dev/null
-From 4661c3afefe900ff7b5004aca0a2c927cfa37f3b Mon Sep 17 00:00:00 2001
-From: Emmanuel Vadot <manu@freebsd.org>
-Date: Mon, 21 May 2018 13:54:13 +0200
-Subject: [PATCH] arm64: dts: allwinner: sun50i: a64: Add spi flash node for
- sopine
-
-The Sopine and Pine64-LTS have a winbond w25q128 spi flash on spi0.
-Add a node for it.
-
-Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
----
- arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
-@@ -75,6 +75,18 @@
- };
- };
-
-+&spi0 {
-+ status = "okay";
-+
-+ flash@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <40000000>;
-+ };
-+};
-+
- #include "axp803.dtsi"
-
- ®_aldo2 {
+++ /dev/null
-From 7cd6dca3600d8d71328950216688ecd00015d1ce Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 12 Jan 2019 20:17:18 -0600
-Subject: [PATCH] clocksource/drivers/arch_timer: Workaround for Allwinner A64
- timer instability
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Allwinner A64 SoC is known[1] to have an unstable architectural
-timer, which manifests itself most obviously in the time jumping forward
-a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a
-timer frequency of 24 MHz, implying that the time went slightly backward
-(and this was interpreted by the kernel as it jumping forward and
-wrapping around past the epoch).
-
-Investigation revealed instability in the low bits of CNTVCT at the
-point a high bit rolls over. This leads to power-of-two cycle forward
-and backward jumps. (Testing shows that forward jumps are about twice as
-likely as backward jumps.) Since the counter value returns to normal
-after an indeterminate read, each "jump" really consists of both a
-forward and backward jump from the software perspective.
-
-Unless the kernel is trapping CNTVCT reads, a userspace program is able
-to read the register in a loop faster than it changes. A test program
-running on all 4 CPU cores that reported jumps larger than 100 ms was
-run for 13.6 hours and reported the following:
-
- Count | Event
--------+---------------------------
- 9940 | jumped backward 699ms
- 268 | jumped backward 1398ms
- 1 | jumped backward 2097ms
- 16020 | jumped forward 175ms
- 6443 | jumped forward 699ms
- 2976 | jumped forward 1398ms
- 9 | jumped forward 356516ms
- 9 | jumped forward 357215ms
- 4 | jumped forward 714430ms
- 1 | jumped forward 3578440ms
-
-This works out to a jump larger than 100 ms about every 5.5 seconds on
-each CPU core.
-
-The largest jump (almost an hour!) was the following sequence of reads:
- 0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000
-
-Note that the middle bits don't necessarily all read as all zeroes or
-all ones during the anomalous behavior; however the low 10 bits checked
-by the function in this patch have never been observed with any other
-value.
-
-Also note that smaller jumps are much more common, with backward jumps
-of 2048 (2^11) cycles observed over 400 times per second on each core.
-(Of course, this is partially explained by lower bits rolling over more
-frequently.) Any one of these could have caused the 95 year time skip.
-
-Similar anomalies were observed while reading CNTPCT (after patching the
-kernel to allow reads from userspace). However, the CNTPCT jumps are
-much less frequent, and only small jumps were observed. The same program
-as before (except now reading CNTPCT) observed after 72 hours:
-
- Count | Event
--------+---------------------------
- 17 | jumped backward 699ms
- 52 | jumped forward 175ms
- 2831 | jumped forward 699ms
- 5 | jumped forward 1398ms
-
-Further investigation showed that the instability in CNTPCT/CNTVCT also
-affected the respective timer's TVAL register. The following values were
-observed immediately after writing CNVT_TVAL to 0x10000000:
-
- CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error
---------------------+------------+--------------------+-----------------
- 0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000
- 0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000
- 0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000
- 0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000
-
-The pattern of errors in CNTV_TVAL seemed to depend on exactly which
-value was written to it. For example, after writing 0x10101010:
-
- CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error
---------------------+------------+--------------------+-----------------
- 0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000
- 0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000
- 0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000
- 0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000
- 0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000
- 0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000
-
-I was also twice able to reproduce the issue covered by Allwinner's
-workaround[4], that writing to TVAL sometimes fails, and both CVAL and
-TVAL are left with entirely bogus values. One was the following values:
-
- CNTVCT | CNTV_TVAL | CNTV_CVAL
---------------------+------------+--------------------------------------
- 0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past)
-Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
-
-========================================================================
-
-Because the CPU can read the CNTPCT/CNTVCT registers faster than they
-change, performing two reads of the register and comparing the high bits
-(like other workarounds) is not a workable solution. And because the
-timer can jump both forward and backward, no pair of reads can
-distinguish a good value from a bad one. The only way to guarantee a
-good value from consecutive reads would be to read _three_ times, and
-take the middle value only if the three values are 1) each unique and
-2) increasing. This takes at minimum 3 counter cycles (125 ns), or more
-if an anomaly is detected.
-
-However, since there is a distinct pattern to the bad values, we can
-optimize the common case (1022/1024 of the time) to a single read by
-simply ignoring values that match the error pattern. This still takes no
-more than 3 cycles in the worst case, and requires much less code. As an
-additional safety check, we still limit the loop iteration to the number
-of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods.
-
-For the TVAL registers, the simple solution is to not use them. Instead,
-read or write the CVAL and calculate the TVAL value in software.
-
-Although the manufacturer is aware of at least part of the erratum[4],
-there is no official name for it. For now, use the kernel-internal name
-"UNKNOWN1".
-
-[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
-[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
-[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
-[4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272
-
-Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
-Tested-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
-Cc: stable@vger.kernel.org
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- Documentation/arm64/silicon-errata.txt | 2 +
- drivers/clocksource/Kconfig | 10 +++++
- drivers/clocksource/arm_arch_timer.c | 55 ++++++++++++++++++++++++++
- 3 files changed, 67 insertions(+)
-
---- a/Documentation/arm64/silicon-errata.txt
-+++ b/Documentation/arm64/silicon-errata.txt
-@@ -44,6 +44,8 @@ stable kernels.
-
- | Implementor | Component | Erratum ID | Kconfig |
- +----------------+-----------------+-----------------+-----------------------------+
-+| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
-+| | | | |
- | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
- | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
- | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
---- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -374,6 +374,16 @@ config ARM64_ERRATUM_858921
- The workaround will be dynamically enabled when an affected
- core is detected.
-
-+config SUN50I_ERRATUM_UNKNOWN1
-+ bool "Workaround for Allwinner A64 erratum UNKNOWN1"
-+ default y
-+ depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI
-+ select ARM_ARCH_TIMER_OOL_WORKAROUND
-+ help
-+ This option enables a workaround for instability in the timer on
-+ the Allwinner A64 SoC. The workaround will only be active if the
-+ allwinner,erratum-unknown1 property is found in the timer node.
-+
- config ARM_GLOBAL_TIMER
- bool "Support for the ARM global timer" if COMPILE_TEST
- select TIMER_OF if OF
---- a/drivers/clocksource/arm_arch_timer.c
-+++ b/drivers/clocksource/arm_arch_timer.c
-@@ -317,6 +317,48 @@ static u64 notrace arm64_858921_read_cnt
- }
- #endif
-
-+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
-+/*
-+ * The low bits of the counter registers are indeterminate while bit 10 or
-+ * greater is rolling over. Since the counter value can jump both backward
-+ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
-+ * with all ones or all zeros in the low bits. Bound the loop by the maximum
-+ * number of CPU cycles in 3 consecutive 24 MHz counter periods.
-+ */
-+#define __sun50i_a64_read_reg(reg) ({ \
-+ u64 _val; \
-+ int _retries = 150; \
-+ \
-+ do { \
-+ _val = read_sysreg(reg); \
-+ _retries--; \
-+ } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
-+ \
-+ WARN_ON_ONCE(!_retries); \
-+ _val; \
-+})
-+
-+static u64 notrace sun50i_a64_read_cntpct_el0(void)
-+{
-+ return __sun50i_a64_read_reg(cntpct_el0);
-+}
-+
-+static u64 notrace sun50i_a64_read_cntvct_el0(void)
-+{
-+ return __sun50i_a64_read_reg(cntvct_el0);
-+}
-+
-+static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
-+{
-+ return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
-+}
-+
-+static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
-+{
-+ return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
-+}
-+#endif
-+
- #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
- DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *,
- timer_unstable_counter_workaround);
-@@ -404,6 +446,19 @@ static const struct arch_timer_erratum_w
- .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
- },
- #endif
-+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
-+ {
-+ .match_type = ate_match_dt,
-+ .id = "allwinner,erratum-unknown1",
-+ .desc = "Allwinner erratum UNKNOWN1",
-+ .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
-+ .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
-+ .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
-+ .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
-+ .set_next_event_phys = erratum_set_next_event_tval_phys,
-+ .set_next_event_virt = erratum_set_next_event_tval_virt,
-+ },
-+#endif
- };
-
- typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
+++ /dev/null
-From 55ec26d6a4241363fa94f15377ebd8f1116fbfd7 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 12 Jan 2019 20:17:19 -0600
-Subject: [PATCH] arm64: dts: allwinner: a64: Enable A64 timer workaround
-
-As instability in the architectural timer has been observed on multiple
-devices using this SoC, inluding the Pine64 and the Orange Pi Win,
-enable the workaround in the SoC's device tree.
-
-Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -114,6 +114,7 @@
-
- timer {
- compatible = "arm,armv8-timer";
-+ allwinner,erratum-unknown1;
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14
+++ /dev/null
-From b76dc5927f6442df913f03ed261c5bff18a98df6 Mon Sep 17 00:00:00 2001
-From: Icenowy Zheng <icenowy@aosc.io>
-Date: Thu, 28 Dec 2017 21:01:56 +0800
-Subject: [PATCH] ARM: dts: sun8i: fix USB Ethernet of Orange Pi R1
-
-Orange Pi R1 uses a Realtek RTL8152B USB Ethernet chip, which is easily
-seen on the board but not show in the schematics. A regulator for the
-power of the RTL8152B chip is hidden, which uses the same pin with the
-Wi-Fi regulator on the original Orange Pi Zero.
-
-Add this regulator back to the device tree, and bind it to USB1.
-
-Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
----
- arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
---- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
-+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
-@@ -49,6 +49,20 @@
-
- /delete-node/ reg_vcc_wifi;
-
-+ /*
-+ * Ths pin of this regulator is the same with the Wi-Fi extra
-+ * regulator on the original Zero. However it's used for USB
-+ * Ethernet rather than the Wi-Fi now.
-+ */
-+ reg_vcc_usb_eth: reg-vcc-usb-ethernet {
-+ compatible = "regulator-fixed";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-name = "vcc-usb-ethernet";
-+ enable-active-high;
-+ gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
-+ };
-+
- aliases {
- ethernet1 = &rtl8189etv;
- };
-@@ -71,3 +85,7 @@
- reg = <1>;
- };
- };
-+
-+&usbphy {
-+ usb1_vbus-supply = <®_vcc_usb_eth>;
-+};
+++ /dev/null
-From 4a36ec1f82db3fa34d766dec5062b4de06b50f7f Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Thu, 28 Dec 2017 14:11:36 +0100
-Subject: [PATCH] ARM: dts: sun8i: activate SPI on Orange Pi R1
-
-This board has a SPI flash, activate it also in device tree by default.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
-+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
-@@ -68,6 +68,14 @@
- };
- };
-
-+&spi0 {
-+ status = "okay";
-+
-+ flash@0 {
-+ compatible = "mxicy,mx25l12805d", "jedec,spi-nor";
-+ };
-+};
-+
- &ohci1 {
- /*
- * RTL8152B USB-Ethernet adapter is connected to USB1,
+++ /dev/null
-From 0e2da1a792a21e3933e17727920ed3c35a3ba57a Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sun, 11 Mar 2018 15:13:30 +0100
-Subject: [PATCH] arm64: allwinner: H5: Add Xunlong Orange Pi Zero Plus
-
-The Xunlong Orange Pi Zero Plus is single board computer.
-- H5 Quad-core 64-bit Cortex-A53
-- 512MB DDR3
-- microSD slot
-- Debug TTL UART
-- 1000M/100M/10M Ethernet RJ45
-- Realtek RTL8189FTV
-- Spi flash (2MB)
-- One USB 2.0 HOST, One USB 2.0 OTG
-
-This is based on a patch from armbian:
-https://github.com/armbian/build/blob/master/patch/kernel/sunxi-next/sunxi-add-orangepi-zero-plus.patch
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- arch/arm64/boot/dts/allwinner/Makefile | 1 +
- .../dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 147 +++++++++++++++++++++
- 2 files changed, 148 insertions(+)
- create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
-
---- a/arch/arm64/boot/dts/allwinner/Makefile
-+++ b/arch/arm64/boot/dts/allwinner/Makefile
-@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-p
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
-@@ -0,0 +1,147 @@
-+/*
-+ * Copyright (C) 2016 ARM Ltd.
-+ * Copyright (C) 2018 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * SPDX-License-Identifier: (GPL-2.0+ OR X11)
-+ */
-+
-+/dts-v1/;
-+#include "sun50i-h5.dtsi"
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/pinctrl/sun4i-a10.h>
-+
-+/ {
-+ model = "Xunlong Orange Pi Zero Plus";
-+ compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5";
-+
-+ reg_vcc3v3: vcc3v3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ aliases {
-+ ethernet0 = &emac;
-+ ethernet1 = &rtl8189ftv;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ pwr {
-+ label = "orangepi:green:pwr";
-+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
-+ default-state = "on";
-+ };
-+
-+ status {
-+ label = "orangepi:red:status";
-+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
-+ };
-+ };
-+
-+ reg_gmac_3v3: gmac-3v3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "gmac-3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <100000>;
-+ enable-active-high;
-+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
-+ };
-+};
-+
-+&ehci0 {
-+ status = "okay";
-+};
-+
-+&ehci1 {
-+ status = "okay";
-+};
-+
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
-+
-+&mmc0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ vmmc-supply = <®_vcc3v3>;
-+ bus-width = <4>;
-+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-+ status = "okay";
-+};
-+
-+&mmc1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mmc1_pins_a>;
-+ vmmc-supply = <®_vcc3v3>;
-+ bus-width = <4>;
-+ non-removable;
-+ status = "okay";
-+
-+ /*
-+ * Explicitly define the sdio device, so that we can add an ethernet
-+ * alias for it (which e.g. makes u-boot set a mac-address).
-+ */
-+ rtl8189ftv: sdio_wifi@1 {
-+ reg = <1>;
-+ };
-+};
-+
-+&spi0 {
-+ status = "okay";
-+
-+ flash@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "mxicy,mx25l1606e", "winbond,w25q128";
-+ reg = <0>;
-+ spi-max-frequency = <40000000>;
-+ };
-+};
-+
-+&ohci0 {
-+ status = "okay";
-+};
-+
-+&ohci1 {
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_pins_a>;
-+ status = "okay";
-+};
-+
-+&usb_otg {
-+ dr_mode = "peripheral";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ /* USB Type-A ports' VBUS is always on */
-+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
-+ status = "okay";
-+};
+++ /dev/null
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
-@@ -87,7 +87,7 @@
-
- sw4 {
- label = "sw4";
-- linux,code = <BTN_0>;
-+ linux,code = <KEY_POWER>;
- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
- };
- };
-@@ -203,7 +203,7 @@
- };
-
- &usb_otg {
-- dr_mode = "otg";
-+ dr_mode = "host";
- status = "okay";
- };
-
+++ /dev/null
-From 49cd9ea6dc8d68eb519ccd9f31c9730dec8a181a Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Thu, 8 Mar 2018 22:14:50 +0100
-Subject: [PATCH] Revert "ARM: dts: sun7i: Add BCM53125 switch nodes to the
- lamobo-r1 board"
-
-This reverts the changes needed for the upstream b53 DSA switch driver
-to use the OpenWrt b43 swconfig switch driver.
-
-This reverts commit 0cdefd5b5485ee6eb3512a75739d09a4090176ed.
-This reverts commit d7b9eaff5f0ca00726336b4c0c3c29decf30412a.
----
- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 60 ++-----------------------------
- 1 file changed, 3 insertions(+), 57 deletions(-)
-
---- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
-@@ -109,67 +109,13 @@
- &gmac {
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
-+ phy = <&phy1>;
- phy-mode = "rgmii";
- phy-supply = <®_gmac_3v3>;
- status = "okay";
-
-- fixed-link {
-- speed = <1000>;
-- full-duplex;
-- };
--
-- mdio {
-- compatible = "snps,dwmac-mdio";
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- switch: ethernet-switch@1e {
-- compatible = "brcm,bcm53125";
-- reg = <30>;
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- ports {
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- port0: port@0 {
-- reg = <0>;
-- label = "lan2";
-- };
--
-- port1: port@1 {
-- reg = <1>;
-- label = "lan3";
-- };
--
-- port2: port@2 {
-- reg = <2>;
-- label = "lan4";
-- };
--
-- port3: port@3 {
-- reg = <3>;
-- label = "wan";
-- };
--
-- port4: port@4 {
-- reg = <4>;
-- label = "lan1";
-- };
--
-- port8: port@8 {
-- reg = <8>;
-- label = "cpu";
-- ethernet = <&gmac>;
-- phy-mode = "rgmii-txid";
-- fixed-link {
-- speed = <1000>;
-- full-duplex;
-- };
-- };
-- };
-- };
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
- };
- };
-
+++ /dev/null
-From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001
-From: Oskari Lemmela <oskari@lemmela.net>
-Date: Mon, 31 Dec 2018 07:44:49 +0200
-Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions.
-
-First 896kB to u-boot. Enough space for SPL, u-boot and ATF.
-Next 128kB to u-boot environment and rest to firmware.
-
-Firmware partition is compatible FIT image dynamic splitting.
-
-Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
----
- .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
-@@ -84,6 +84,28 @@
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
-+
-+ partitions {
-+ compatible = "fixed-partitions";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "u-boot";
-+ reg = <0x000000 0x0E0000>;
-+ };
-+
-+ partition@e0000 {
-+ label = "u-boot-env";
-+ reg = <0x0E0000 0x020000>;
-+ };
-+
-+ partition@100000 {
-+ compatible = "denx,fit";
-+ label = "firmware";
-+ reg = <0x100000 0xF00000>;
-+ };
-+ };
- };
- };
-
projects / openwrt / openwrt.git / commitdiff