drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.

These tables are used on voltage vswing sequence initialization on
Icelake.

The swing_sel on the spec's table is defined in a 4 bits binary like
1010.  However the register bits are split in upper 1 bit swing_sel
and lower 3 bits swing sel.

In this table here we store this value as a single value in hex like
it is mentioned in the Bspec and split it to the upper and lower bit
values only while programming the registers.

For instance: b1010 is written as 0xA and then while writing to the
register, the upper 1 bit is obtained by (0xA & 0x8) and shifting by
appropriate bits while lower 3 bits are obtained by (0xA & 0x7) and
shifting by appropriate bits.

Some of the columns need to be updated after the spec is updated.

v5 (from Paulo):
* Checkpatch fixes.
v4 (from Paulo):
* Fix minor typo
* Coding style conformance
v3:
* Get rid of HDMI/DVI tables, same as DP (Paulo)
* Use combo_phy in ddi buf trans table defs (Paulo)
v2:
* Added DW4_scaling_hex column to the translation tables (Rodrigo)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180323172419.24911-3-paulo.r.zanoni@intel.com

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c449619427da0725b4b005c686101007c870e5db..229b9d5250c4682b053bebb74d8fc8eeed1b7481 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -493,6 +493,105 @@ static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
        { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 };
 
+struct icl_combo_phy_ddi_buf_trans {
+       u32 dw2_swing_select;
+       u32 dw2_swing_scalar;
+       u32 dw4_scaling;
+};
+
+/* Voltage Swing Programming for VccIO 0.85V for DP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
+                               /* Voltage mV  db    */
+       { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
+       { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
+       { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
+       { 0x2, 0x98, 0x900F },  /* 400         9.5   */
+       { 0xB, 0x70, 0x0018 },  /* 600         0.0   */
+       { 0xB, 0x70, 0x3015 },  /* 600         3.5   */
+       { 0xB, 0x70, 0x6012 },  /* 600         6.0   */
+       { 0x5, 0x00, 0x0018 },  /* 800         0.0   */
+       { 0x5, 0x00, 0x3015 },  /* 800         3.5   */
+       { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
+};
+
+/* FIXME - After table is updated in Bspec */
+/* Voltage Swing Programming for VccIO 0.85V for eDP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
+                               /* Voltage mV  db    */
+       { 0x0, 0x00, 0x00 },    /* 200         0.0   */
+       { 0x0, 0x00, 0x00 },    /* 200         1.5   */
+       { 0x0, 0x00, 0x00 },    /* 200         4.0   */
+       { 0x0, 0x00, 0x00 },    /* 200         6.0   */
+       { 0x0, 0x00, 0x00 },    /* 250         0.0   */
+       { 0x0, 0x00, 0x00 },    /* 250         1.5   */
+       { 0x0, 0x00, 0x00 },    /* 250         4.0   */
+       { 0x0, 0x00, 0x00 },    /* 300         0.0   */
+       { 0x0, 0x00, 0x00 },    /* 300         1.5   */
+       { 0x0, 0x00, 0x00 },    /* 350         0.0   */
+};
+
+/* Voltage Swing Programming for VccIO 0.95V for DP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
+                               /* Voltage mV  db    */
+       { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
+       { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
+       { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
+       { 0x2, 0x98, 0x900F },  /* 400         9.5   */
+       { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
+       { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
+       { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
+       { 0x5, 0x76, 0x0018 },  /* 800         0.0   */
+       { 0x5, 0x76, 0x3015 },  /* 800         3.5   */
+       { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
+};
+
+/* FIXME - After table is updated in Bspec */
+/* Voltage Swing Programming for VccIO 0.95V for eDP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
+                               /* Voltage mV  db    */
+       { 0x0, 0x00, 0x00 },    /* 200         0.0   */
+       { 0x0, 0x00, 0x00 },    /* 200         1.5   */
+       { 0x0, 0x00, 0x00 },    /* 200         4.0   */
+       { 0x0, 0x00, 0x00 },    /* 200         6.0   */
+       { 0x0, 0x00, 0x00 },    /* 250         0.0   */
+       { 0x0, 0x00, 0x00 },    /* 250         1.5   */
+       { 0x0, 0x00, 0x00 },    /* 250         4.0   */
+       { 0x0, 0x00, 0x00 },    /* 300         0.0   */
+       { 0x0, 0x00, 0x00 },    /* 300         1.5   */
+       { 0x0, 0x00, 0x00 },    /* 350         0.0   */
+};
+
+/* Voltage Swing Programming for VccIO 1.05V for DP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
+                               /* Voltage mV  db    */
+       { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
+       { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
+       { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
+       { 0x2, 0x98, 0x900F },  /* 400         9.5   */
+       { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
+       { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
+       { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
+       { 0x5, 0x71, 0x0018 },  /* 800         0.0   */
+       { 0x5, 0x71, 0x3015 },  /* 800         3.5   */
+       { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
+};
+
+/* FIXME - After table is updated in Bspec */
+/* Voltage Swing Programming for VccIO 1.05V for eDP */
+static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
+                               /* Voltage mV  db    */
+       { 0x0, 0x00, 0x00 },    /* 200         0.0   */
+       { 0x0, 0x00, 0x00 },    /* 200         1.5   */
+       { 0x0, 0x00, 0x00 },    /* 200         4.0   */
+       { 0x0, 0x00, 0x00 },    /* 200         6.0   */
+       { 0x0, 0x00, 0x00 },    /* 250         0.0   */
+       { 0x0, 0x00, 0x00 },    /* 250         1.5   */
+       { 0x0, 0x00, 0x00 },    /* 250         4.0   */
+       { 0x0, 0x00, 0x00 },    /* 300         0.0   */
+       { 0x0, 0x00, 0x00 },    /* 300         1.5   */
+       { 0x0, 0x00, 0x00 },    /* 350         0.0   */
+};
+
 static const struct ddi_buf_trans *
 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 {