drm/amd/display: guard DPPHY_Internal_ctrl
authorCharlene Liu <Charlene.Liu@amd.com>
Tue, 21 Jan 2020 02:32:03 +0000 (21:32 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 19 Mar 2020 04:03:04 +0000 (00:03 -0400)
[why]
this register not exist in some asic, based on request remove this from
dc.

[how]
add guard for sanization.

Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

index eb13589b9a81b6579e164c781310ec169ab780f8..762109174fb879650a32df771596410d43d2f564 100644 (file)
        SRI(DP_DPHY_FAST_TRAINING, DP, id), \
        SRI(DP_SEC_CNTL1, DP, id), \
        SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
-       SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
        SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
 
 
 #define LE_DCN10_REG_LIST(id)\
+       SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
        LE_DCN_COMMON_REG_LIST(id)
 
 struct dcn10_link_enc_aux_registers {