drm/amdgpu/gfx9: allow updating gfx mgpg state

Wire up the functions to control medium grained
powergating.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index bba13c796cd9bb1513dc315c0d6f06826c991a6e..a1e1b7aa54043a6b040e8a9d122207df6bf7e147 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1992,6 +1992,34 @@ static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
                data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
 }
 
+void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
+                                               bool enable)
+{
+       uint32_t data, default_data;
+
+       default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+       if (enable == true)
+               data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
+       else
+               data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
+       if(default_data != data)
+               WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+}
+
+void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
+                                               bool enable)
+{
+       uint32_t data, default_data;
+
+       default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+       if (enable == true)
+               data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
+       else
+               data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
+       if(default_data != data)
+               WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+}
+
 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
 {
        if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
@@ -3259,6 +3287,25 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
        /* gfx_v9_0_exit_rlc_safe_mode(adev); */
 }
 
+static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
+                                               bool enable)
+{
+       /* TODO: double check if we need to perform under safe mode */
+       /* gfx_v9_0_enter_rlc_safe_mode(adev); */
+
+       if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
+               gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
+       else
+               gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
+
+       if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
+               gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
+       else
+               gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
+
+       /* gfx_v9_0_exit_rlc_safe_mode(adev); */
+}
+
 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
                                                      bool enable)
 {
@@ -3469,6 +3516,9 @@ static int gfx_v9_0_set_powergating_state(void *handle,
 
                /* update gfx cgpg state */
                gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
+
+               /* update mgcg state */
+               gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
                break;
        default:
                break;