case AMDGPU_FAMILY_RV:
switch (hwmgr->chip_id) {
case CHIP_RAVEN:
+ case CHIP_PICASSO:
hwmgr->od_enabled = false;
hwmgr->smumgr_funcs = &smu10_smu_funcs;
smu10_init_function_pointers(hwmgr);
uint16_t size;
if (!table_addr) {
- if (hwmgr->chip_id == CHIP_RAVEN) {
+ if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) {
table_addr = &soft_dummy_pp_table[0];
hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
hwmgr->platform_descriptor.overdriveVDDCStep = 0;
- if (hwmgr->chip_id == CHIP_RAVEN)
+ if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO)
return 0;
/* We assume here that fw_info is unchanged if this call fails.*/
int result;
const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table;
- if (hwmgr->chip_id == CHIP_RAVEN)
+ if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO)
return 0;
hwmgr->need_pp_table_upload = true;
static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
{
- if (hwmgr->chip_id == CHIP_RAVEN)
+ if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO)
return 0;
kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);