Rename 'atheros' target to more precise 'ath25'.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 44736
define KernelPackage/ath
$(call KernelPackage/mac80211/Default)
TITLE:=Atheros common driver part
- DEPENDS+= @PCI_SUPPORT||USB_SUPPORT||TARGET_ar71xx||TARGET_atheros +kmod-mac80211
+ DEPENDS+= @PCI_SUPPORT||USB_SUPPORT||TARGET_ar71xx||TARGET_ath25 +kmod-mac80211
FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath.ko
MENU:=1
endef
$(call KernelPackage/mac80211/Default)
TITLE:=Atheros 5xxx wireless cards support
URL:=http://linuxwireless.org/en/users/Drivers/ath5k
- DEPENDS+= @PCI_SUPPORT||@TARGET_atheros +kmod-ath
+ DEPENDS+= @PCI_SUPPORT||@TARGET_ath25 +kmod-ath
FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath5k/ath5k.ko
AUTOLOAD:=$(call AutoProbe,ath5k)
endef
config-$(call config_package,ath10k) += ATH10K ATH10K_PCI
config-$(call config_package,ath5k) += ATH5K
-ifdef CONFIG_TARGET_atheros
+ifdef CONFIG_TARGET_ath25
config-y += ATH5K_AHB
else
config-y += ATH5K_PCI
define KernelPackage/wrt55agv2-spidevs
SUBMENU:=Other modules
TITLE:=WRT55AG v2 SPI devices support
- DEPENDS:=@TARGET_atheros +kmod-spi-gpio-old +kmod-spi-ks8995
+ DEPENDS:=@TARGET_ath25 +kmod-spi-gpio-old +kmod-spi-ks8995
FILES:=$(PKG_BUILD_DIR)/wrt55agv2_spidevs.ko
endef
--- /dev/null
+#
+# Copyright (C) 2006-2013 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+
+ARCH:=mips
+BOARD:=ath25
+BOARDNAME:=Atheros AR231x/AR5312
+FEATURES:=squashfs low_mem
+
+KERNEL_PATCHVER:=3.18
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += wpad-mini kmod-ath5k swconfig kmod-gpio-button-hotplug
+
+define Target/Description
+ Build firmware images for Atheros SoC boards
+endef
+
+$(eval $(call BuildTarget))
--- /dev/null
+config system
+ option hostname OpenWrt
+ option timezone UTC
+
+config timeserver ntp
+ list server 0.openwrt.pool.ntp.org
+ list server 1.openwrt.pool.ntp.org
+ list server 2.openwrt.pool.ntp.org
+ list server 3.openwrt.pool.ntp.org
+
+config button
+ option button reset
+ option action released
+ option handler "logger reboot"
+ option min 0
+ option max 4
+
+config button
+ option button reset
+ option action released
+ option handler "logger factory default"
+ option min 5
+ option max 30
--- /dev/null
+. /lib/functions.sh
+do_button () {
+ local button
+ local action
+ local handler
+ local min
+ local max
+
+ config_get button $1 button
+ config_get action $1 action
+ config_get handler $1 handler
+ config_get min $1 min
+ config_get max $1 max
+
+ [ "$ACTION" = "$action" -a "$BUTTON" = "$button" -a -n "$handler" ] && {
+ [ -z "$min" -o -z "$max" ] && eval $handler
+ [ -n "$min" -a -n "$max" ] && {
+ [ $min -le $SEEN -a $max -ge $SEEN ] && eval $handler
+ }
+ }
+}
+
+config_load system
+config_foreach do_button button
--- /dev/null
+#!/bin/sh
+# Copyright 2012 OpenWrt.org
+#
+
+. /lib/functions/uci-defaults.sh
+
+ucidef_set_led_netdev "wlan" "wlan" "wlan" "wlan0"
+
+ucidef_commit_leds
+
+exit 0
--- /dev/null
+#!/bin/sh
+if [ -e "/sys/bus/mdio_bus/drivers/IC+ IP175C/0:00" -o \
+ -e "/sys/bus/mdio_bus/drivers/IC+ IP17xx/0:00" ] && \
+ [ -x /sbin/swconfig ];
+then
+ uci batch <<EOF
+set network.eth0=switch
+set network.eth0.name=eth0
+set network.eth0.reset=1
+set network.eth0.enable_vlan=1
+set network.eth0_1=switch_vlan
+set network.eth0_1.device=eth0
+set network.eth0_1.vlan=1
+set network.eth0_1.ports="0 1 2 3 5t"
+set network.eth0_2=switch_vlan
+set network.eth0_2.device=eth0
+set network.eth0_2.vlan=2
+set network.eth0_2.ports="4 5t"
+EOF
+ HAS_SWITCH=1
+fi
+
+if [ -n "$HAS_SWITCH" -o \
+ -e "/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00" -o \
+ -e "/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10" ]; then
+ uci batch <<EOF
+set network.lan.ifname=eth0.1
+set network.wan=interface
+set network.wan.ifname=eth0.2
+set network.wan.proto=dhcp
+commit network
+EOF
+ HAS_SWITCH=1
+fi
+
+[ -z "$HAS_SWITCH" -a -d /sys/class/net/eth1 ] && {
+ uci batch <<EOF
+set network.wan=interface
+set network.wan.ifname=eth1
+set network.wan.proto=dhcp
+commit network
+EOF
+}
+
+uci commit network
--- /dev/null
+#!/bin/sh
+
+# reset button only supported on ar5315+ at the moment
+preinit_ip() {
+ if [ -z "$pi_ifname" ]; then
+ grep -q 'Atheros AR231[567]' /proc/cpuinfo && {
+ if [ -e "/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00" -o \
+ -e "/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10" ]; then
+ vconfig set_name_type DEV_PLUS_VID_NO_PAD
+ ifconfig eth0 up
+ vconfig add eth0 1
+ ifname=eth0.1
+ else
+ ifname=eth0
+ fi
+ pi_ifname=$ifname
+ }
+ fi
+ [ -n "$pi_ifname" ] && grep -q "$pi_ifname" /proc/net/dev && {
+ ifconfig $pi_ifname $pi_ip netmask $pi_netmask broadcast $pi_broadcast up
+ }
+}
+
+
+# reset button only supported on ar5315+ at the moment
+
+preinit_ip_deconfig() {
+ if [ -e "/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00" -o \
+ -e "/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10" ]; then
+ vconfig rem eth0.1 2>/dev/null
+ ifconfig $pi_ifname down
+ elif [ -n "$pi_ifname" ]; then
+ ifconfig $pi_ifname 0.0.0.0
+ fi
+}
--- /dev/null
+CI_BLKSZ=65536
+CI_LDADR=0x80041000
+
+platform_find_partitions() {
+ local first dev size erasesize name
+ while read dev size erasesize name; do
+ name=${name#'"'}; name=${name%'"'}
+ case "$name" in
+ vmlinux.bin.l7|kernel|linux|rootfs)
+ if [ -z "$first" ]; then
+ first="$name"
+ else
+ echo "$erasesize:$first:$name"
+ break
+ fi
+ ;;
+ esac
+ done < /proc/mtd
+}
+
+platform_find_kernelpart() {
+ local part
+ for part in "${1%:*}" "${1#*:}"; do
+ case "$part" in
+ vmlinux.bin.l7|kernel|linux)
+ echo "$part"
+ break
+ ;;
+ esac
+ done
+}
+
+platform_check_image() {
+ [ "$#" -gt 1 ] && return 1
+
+ case "$(get_magic_word "$1")" in
+ # Combined Image
+ 4349)
+ local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null)
+ local md5_chk=$(dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}"
+
+ if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then
+ return 0
+ else
+ echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)"
+ return 1
+ fi
+ ;;
+ *)
+ echo "Invalid image. Use combined .img files on this platform"
+ return 1
+ ;;
+ esac
+}
+
+platform_do_upgrade() {
+ local partitions=$(platform_find_partitions)
+ local kernelpart=$(platform_find_kernelpart "${partitions#*:}")
+ local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}"
+ local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null)
+ local kern_blocks=$(($kern_length / $CI_BLKSZ))
+ local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ))
+
+ if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \
+ [ ${kern_blocks:-0} -gt 0 ] && \
+ [ ${root_blocks:-0} -gt ${kern_blocks:-0} ] && \
+ [ ${erase_size:-0} -gt 0 ];
+ then
+ local append=""
+ [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR"
+
+ ( dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null; \
+ dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null ) | \
+ mtd -r $append -F$kernelpart:$kern_length:$CI_LDADR,rootfs write - $partitions
+ fi
+}
--- /dev/null
+CONFIG_ADM6996_PHY=y
+CONFIG_AR2315_WDT=y
+CONFIG_AR8216_PHY=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ATH25=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_AR2315=y
+CONFIG_GPIO_AR5312=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IP17XX_PHY=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_GPIO=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_AR2315=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_MYLOADER_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MVSWITCH_PHY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_AR231X=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_AR2315=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_STALL_COMMON is not set
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SOC_AR2315=y
+CONFIG_SOC_AR5312=y
+# CONFIG_SWAP is not set
+CONFIG_SWCONFIG=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_SUPPORT=y
+CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+#
+# Copyright (C) 2006-2010 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+define Image/BuildKernel
+ cp $(KDIR)/vmlinux.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.elf
+ gzip -9 -c $(KDIR)/vmlinux > $(KDIR)/vmlinux.bin.gz
+ $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.bin.l7
+ dd if=$(KDIR)/vmlinux.bin.l7 of=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma bs=65536 conv=sync
+ dd if=$(KDIR)/vmlinux.bin.gz of=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.gz bs=65536 conv=sync
+endef
+
+define Image/Build/squashfs
+ $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
+endef
+
+define Image/Build
+ $(call Image/Build/$(1))
+ dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync
+
+ -$(STAGING_DIR_HOST)/bin/mkfwimage \
+ -B XS2 -v XS2.ar2316.OpenWrt.$(REVISION) \
+ -k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \
+ -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
+ -o $(BIN_DIR)/$(IMG_PREFIX)-ubnt2-$(1).bin
+
+ -$(STAGING_DIR_HOST)/bin/mkfwimage \
+ -B XS5 -v XS5.ar2313.OpenWrt.$(REVISION) \
+ -k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \
+ -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
+ -o $(BIN_DIR)/$(IMG_PREFIX)-ubnt5-$(1).bin
+
+ -$(STAGING_DIR_HOST)/bin/mkfwimage \
+ -B XS2-8 -v XS2.ar2316.OpenWrt.$(REVISION) \
+ -k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \
+ -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
+ -o $(BIN_DIR)/$(IMG_PREFIX)-ubnt2-pico2-$(1).bin
+
+ -$(STAGING_DIR_HOST)/bin/mkmylofw -B np25g \
+ -p0x020000:0x130000:ah:0x80041000:linux:$(KDIR)/vmlinux.bin.gz \
+ -p0x150000:0x2a0000:::rootfs:$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
+ $(BIN_DIR)/$(IMG_PREFIX)-np25g-$(1).bin
+
+ -$(STAGING_DIR_HOST)/bin/mkmylofw -B wpe53g \
+ -p0x020000:0x130000:ah:0x80041000:linux:$(KDIR)/vmlinux.bin.gz \
+ -p0x150000:0x2a0000:::rootfs:$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
+ $(BIN_DIR)/$(IMG_PREFIX)-wpe53g-$(1).bin
+
+ -sh $(TOPDIR)/scripts/combined-image.sh \
+ "$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma" \
+ "$(BIN_DIR)/$(IMG_PREFIX)-root.$(1)" \
+ "$(BIN_DIR)/$(IMG_PREFIX)-combined.$(1).img"
+endef
+
+$(eval $(call BuildImage))
--- /dev/null
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -96,6 +96,19 @@ config AR7
+ Support for the Texas Instruments AR7 System-on-a-Chip
+ family: TNETD7100, 7200 and 7300.
+
++config ATH25
++ bool "Atheros AR231x/AR531x SoC support"
++ select CEVT_R4K
++ select CSRC_R4K
++ select DMA_NONCOHERENT
++ select IRQ_CPU
++ select IRQ_DOMAIN
++ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_SUPPORTS_BIG_ENDIAN
++ select SYS_SUPPORTS_32BIT_KERNEL
++ help
++ Support for Atheros AR231x and Atheros AR531x based boards
++
+ config ATH79
+ bool "Atheros AR71XX/AR724X/AR913X based boards"
+ select ARCH_REQUIRE_GPIOLIB
+@@ -835,6 +848,7 @@ config MIPS_PARAVIRT
+ endchoice
+
+ source "arch/mips/alchemy/Kconfig"
++source "arch/mips/ath25/Kconfig"
+ source "arch/mips/ath79/Kconfig"
+ source "arch/mips/bcm47xx/Kconfig"
+ source "arch/mips/bcm63xx/Kconfig"
+--- a/arch/mips/Kbuild.platforms
++++ b/arch/mips/Kbuild.platforms
+@@ -2,6 +2,7 @@
+
+ platforms += alchemy
+ platforms += ar7
++platforms += ath25
+ platforms += ath79
+ platforms += bcm47xx
+ platforms += bcm63xx
+--- /dev/null
++++ b/arch/mips/ath25/Platform
+@@ -0,0 +1,6 @@
++#
++# Atheros AR531X/AR231X WiSoC
++#
++platform-$(CONFIG_ATH25) += ath25/
++cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
++load-$(CONFIG_ATH25) += 0xffffffff80041000
+--- /dev/null
++++ b/arch/mips/ath25/Kconfig
+@@ -0,0 +1,9 @@
++config SOC_AR5312
++ bool "Atheros AR5312/AR2312+ SoC support"
++ depends on ATH25
++ default y
++
++config SOC_AR2315
++ bool "Atheros AR2315+ SoC support"
++ depends on ATH25
++ default y
+--- /dev/null
++++ b/arch/mips/ath25/Makefile
+@@ -0,0 +1,13 @@
++#
++# This file is subject to the terms and conditions of the GNU General Public
++# License. See the file "COPYING" in the main directory of this archive
++# for more details.
++#
++# Copyright (C) 2006 FON Technology, SL.
++# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++#
++
++obj-y += board.o prom.o devices.o
++obj-$(CONFIG_SOC_AR5312) += ar5312.o
++obj-$(CONFIG_SOC_AR2315) += ar2315.o
+--- /dev/null
++++ b/arch/mips/ath25/board.c
+@@ -0,0 +1,234 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++ */
++
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <asm/irq_cpu.h>
++#include <asm/reboot.h>
++#include <asm/bootinfo.h>
++#include <asm/time.h>
++
++#include <ath25_platform.h>
++#include "devices.h"
++#include "ar5312.h"
++#include "ar2315.h"
++
++void (*ath25_irq_dispatch)(void);
++
++static inline bool check_radio_magic(const void __iomem *addr)
++{
++ addr += 0x7a; /* offset for flash magic */
++ return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
++}
++
++static inline bool check_notempty(const void __iomem *addr)
++{
++ return __raw_readl(addr) != 0xffffffff;
++}
++
++static inline bool check_board_data(const void __iomem *addr, bool broken)
++{
++ /* config magic found */
++ if (__raw_readl(addr) == ATH25_BD_MAGIC)
++ return true;
++
++ if (!broken)
++ return false;
++
++ /* broken board data detected, use radio data to find the
++ * offset, user will fix this */
++
++ if (check_radio_magic(addr + 0x1000))
++ return true;
++ if (check_radio_magic(addr + 0xf8))
++ return true;
++
++ return false;
++}
++
++static const void __iomem * __init find_board_config(const void __iomem *limit,
++ const bool broken)
++{
++ const void __iomem *addr;
++ const void __iomem *begin = limit - 0x1000;
++ const void __iomem *end = limit - 0x30000;
++
++ for (addr = begin; addr >= end; addr -= 0x1000)
++ if (check_board_data(addr, broken))
++ return addr;
++
++ return NULL;
++}
++
++static const void __iomem * __init find_radio_config(const void __iomem *limit,
++ const void __iomem *bcfg)
++{
++ const void __iomem *rcfg, *begin, *end;
++
++ /*
++ * Now find the start of Radio Configuration data, using heuristics:
++ * Search forward from Board Configuration data by 0x1000 bytes
++ * at a time until we find non-0xffffffff.
++ */
++ begin = bcfg + 0x1000;
++ end = limit;
++ for (rcfg = begin; rcfg < end; rcfg += 0x1000)
++ if (check_notempty(rcfg) && check_radio_magic(rcfg))
++ return rcfg;
++
++ /* AR2316 relocates radio config to new location */
++ begin = bcfg + 0xf8;
++ end = limit - 0x1000 + 0xf8;
++ for (rcfg = begin; rcfg < end; rcfg += 0x1000)
++ if (check_notempty(rcfg) && check_radio_magic(rcfg))
++ return rcfg;
++
++ return NULL;
++}
++
++/*
++ * NB: Search region size could be larger than the actual flash size,
++ * but this shouldn't be a problem here, because the flash
++ * will simply be mapped multiple times.
++ */
++int __init ath25_find_config(phys_addr_t base, unsigned long size)
++{
++ const void __iomem *flash_base, *flash_limit;
++ struct ath25_boarddata *config;
++ unsigned int rcfg_size;
++ int broken_boarddata = 0;
++ const void __iomem *bcfg, *rcfg;
++ u8 *board_data;
++ u8 *radio_data;
++ u8 *mac_addr;
++ u32 offset;
++
++ flash_base = ioremap_nocache(base, size);
++ flash_limit = flash_base + size;
++
++ ath25_board.config = NULL;
++ ath25_board.radio = NULL;
++
++ /* Copy the board and radio data to RAM, because accessing the mapped
++ * memory of the flash directly after booting is not safe */
++
++ /* Try to find valid board and radio data */
++ bcfg = find_board_config(flash_limit, false);
++
++ /* If that fails, try to at least find valid radio data */
++ if (!bcfg) {
++ bcfg = find_board_config(flash_limit, true);
++ broken_boarddata = 1;
++ }
++
++ if (!bcfg) {
++ pr_warn("WARNING: No board configuration data found!\n");
++ goto error;
++ }
++
++ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
++ ath25_board.config = (struct ath25_boarddata *)board_data;
++ memcpy_fromio(board_data, bcfg, 0x100);
++ if (broken_boarddata) {
++ pr_warn("WARNING: broken board data detected\n");
++ config = ath25_board.config;
++ if (is_zero_ether_addr(config->enet0_mac)) {
++ pr_info("Fixing up empty mac addresses\n");
++ config->reset_config_gpio = 0xffff;
++ config->sys_led_gpio = 0xffff;
++ random_ether_addr(config->wlan0_mac);
++ config->wlan0_mac[0] &= ~0x06;
++ random_ether_addr(config->enet0_mac);
++ random_ether_addr(config->enet1_mac);
++ }
++ }
++
++ /* Radio config starts 0x100 bytes after board config, regardless
++ * of what the physical layout on the flash chip looks like */
++
++ rcfg = find_radio_config(flash_limit, bcfg);
++ if (!rcfg) {
++ pr_warn("WARNING: Could not find Radio Configuration data\n");
++ goto error;
++ }
++
++ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
++ ath25_board.radio = radio_data;
++ offset = radio_data - board_data;
++ pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
++ offset);
++ rcfg_size = BOARD_CONFIG_BUFSZ - offset;
++ memcpy_fromio(radio_data, rcfg, rcfg_size);
++
++ mac_addr = &radio_data[0x1d * 2];
++ if (is_broadcast_ether_addr(mac_addr)) {
++ pr_info("Radio MAC is blank; using board-data\n");
++ ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
++ }
++
++ iounmap(flash_base);
++
++ return 0;
++
++error:
++ iounmap(flash_base);
++ return -ENODEV;
++}
++
++static void ath25_halt(void)
++{
++ local_irq_disable();
++ unreachable();
++}
++
++void __init plat_mem_setup(void)
++{
++ _machine_halt = ath25_halt;
++ pm_power_off = ath25_halt;
++
++ if (is_ar5312())
++ ar5312_plat_mem_setup();
++ else
++ ar2315_plat_mem_setup();
++
++ /* Disable data watchpoints */
++ write_c0_watchlo0(0);
++}
++
++asmlinkage void plat_irq_dispatch(void)
++{
++ ath25_irq_dispatch();
++}
++
++void __init plat_time_init(void)
++{
++ if (is_ar5312())
++ ar5312_plat_time_init();
++ else
++ ar2315_plat_time_init();
++}
++
++unsigned int __cpuinit get_c0_compare_int(void)
++{
++ return CP0_LEGACY_COMPARE_IRQ;
++}
++
++void __init arch_init_irq(void)
++{
++ clear_c0_status(ST0_IM);
++ mips_cpu_irq_init();
++
++ /* Initialize interrupt controllers */
++ if (is_ar5312())
++ ar5312_arch_init_irq();
++ else
++ ar2315_arch_init_irq();
++}
+--- /dev/null
++++ b/arch/mips/ath25/prom.c
+@@ -0,0 +1,26 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright MontaVista Software Inc
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
++ */
++
++/*
++ * Prom setup file for AR5312/AR231x SoCs
++ */
++
++#include <linux/init.h>
++#include <asm/bootinfo.h>
++
++void __init prom_init(void)
++{
++}
++
++void __init prom_free_prom_memory(void)
++{
++}
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
+@@ -0,0 +1,73 @@
++#ifndef __ASM_MACH_ATH25_PLATFORM_H
++#define __ASM_MACH_ATH25_PLATFORM_H
++
++#include <linux/etherdevice.h>
++
++/*
++ * This is board-specific data that is stored in a "fixed" location in flash.
++ * It is shared across operating systems, so it should not be changed lightly.
++ * The main reason we need it is in order to extract the ethernet MAC
++ * address(es).
++ */
++struct ath25_boarddata {
++ u32 magic; /* board data is valid */
++#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
++ u16 cksum; /* checksum (starting with BD_REV 2) */
++ u16 rev; /* revision of this struct */
++#define BD_REV 4
++ char board_name[64]; /* Name of board */
++ u16 major; /* Board major number */
++ u16 minor; /* Board minor number */
++ u32 flags; /* Board configuration */
++#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
++#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
++#define BD_UART1 0x00000004 /* UART1 is stuffed */
++#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
++#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
++#define BD_SYSLED 0x00000020 /* System LED stuffed */
++#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
++#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
++#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
++#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
++#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
++#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
++#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
++#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
++#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
++#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
++#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
++#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
++ u16 reset_config_gpio; /* Reset factory GPIO pin */
++ u16 sys_led_gpio; /* System LED GPIO pin */
++
++ u32 cpu_freq; /* CPU core frequency in Hz */
++ u32 sys_freq; /* System frequency in Hz */
++ u32 cnt_freq; /* Calculated C0_COUNT frequency */
++
++ u8 wlan0_mac[ETH_ALEN];
++ u8 enet0_mac[ETH_ALEN];
++ u8 enet1_mac[ETH_ALEN];
++
++ u16 pci_id; /* Pseudo PCIID for common code */
++ u16 mem_cap; /* cap bank1 in MB */
++
++ /* version 3 */
++ u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
++};
++
++#define BOARD_CONFIG_BUFSZ 0x1000
++
++/*
++ * Platform device information for the Wireless MAC
++ */
++struct ar231x_board_config {
++ u16 devid;
++
++ /* board config data */
++ struct ath25_boarddata *config;
++
++ /* radio calibration data */
++ const char *radio;
++};
++
++#endif /* __ASM_MACH_ATH25_PLATFORM_H */
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
+@@ -0,0 +1,64 @@
++/*
++ * Atheros AR231x/AR531x SoC specific CPU feature overrides
++ *
++ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This file was derived from: include/asm-mips/cpu-features.h
++ * Copyright (C) 2003, 2004 Ralf Baechle
++ * Copyright (C) 2004 Maciej W. Rozycki
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
++#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
++
++/*
++ * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
++ */
++#define cpu_has_tlb 1
++#define cpu_has_4kex 1
++#define cpu_has_3k_cache 0
++#define cpu_has_4k_cache 1
++#define cpu_has_tx39_cache 0
++#define cpu_has_sb1_cache 0
++#define cpu_has_fpu 0
++#define cpu_has_32fpr 0
++#define cpu_has_counter 1
++#define cpu_has_ejtag 1
++
++#if !defined(CONFIG_SOC_AR5312)
++# define cpu_has_llsc 1
++#else
++/*
++ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
++ * ll/sc instructions.
++ */
++# define cpu_has_llsc 0
++#endif
++
++#define cpu_has_mips16 0
++#define cpu_has_mdmx 0
++#define cpu_has_mips3d 0
++#define cpu_has_smartmips 0
++
++#define cpu_has_mips32r1 1
++
++#if !defined(CONFIG_SOC_AR5312)
++# define cpu_has_mips32r2 1
++#endif
++
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
++
++#define cpu_has_dsp 0
++#define cpu_has_mipsmt 0
++
++#define cpu_has_64bits 0
++#define cpu_has_64bit_zero_reg 0
++#define cpu_has_64bit_gp_regs 0
++#define cpu_has_64bit_addresses 0
++
++#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
+@@ -0,0 +1,82 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
++ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
++ *
++ */
++#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
++#define __ASM_MACH_ATH25_DMA_COHERENCE_H
++
++#include <linux/device.h>
++
++/*
++ * We need some arbitrary non-zero value to be programmed to the BAR1 register
++ * of PCI host controller to enable DMA. The same value should be used as the
++ * offset to calculate the physical address of DMA buffer for PCI devices.
++ */
++#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
++
++static inline dma_addr_t ath25_dev_offset(struct device *dev)
++{
++#ifdef CONFIG_PCI
++ extern struct bus_type pci_bus_type;
++
++ if (dev && dev->bus == &pci_bus_type)
++ return AR2315_PCI_HOST_SDRAM_BASEADDR;
++#endif
++ return 0;
++}
++
++static inline dma_addr_t
++plat_map_dma_mem(struct device *dev, void *addr, size_t size)
++{
++ return virt_to_phys(addr) + ath25_dev_offset(dev);
++}
++
++static inline dma_addr_t
++plat_map_dma_mem_page(struct device *dev, struct page *page)
++{
++ return page_to_phys(page) + ath25_dev_offset(dev);
++}
++
++static inline unsigned long
++plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
++{
++ return dma_addr - ath25_dev_offset(dev);
++}
++
++static inline void
++plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
++ enum dma_data_direction direction)
++{
++}
++
++static inline int plat_dma_supported(struct device *dev, u64 mask)
++{
++ return 1;
++}
++
++static inline void plat_extra_sync_for_device(struct device *dev)
++{
++}
++
++static inline int plat_dma_mapping_error(struct device *dev,
++ dma_addr_t dma_addr)
++{
++ return 0;
++}
++
++static inline int plat_device_is_coherent(struct device *dev)
++{
++#ifdef CONFIG_DMA_COHERENT
++ return 1;
++#endif
++#ifdef CONFIG_DMA_NONCOHERENT
++ return 0;
++#endif
++}
++
++#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath25/gpio.h
+@@ -0,0 +1,16 @@
++#ifndef __ASM_MACH_ATH25_GPIO_H
++#define __ASM_MACH_ATH25_GPIO_H
++
++#include <asm-generic/gpio.h>
++
++#define gpio_get_value __gpio_get_value
++#define gpio_set_value __gpio_set_value
++#define gpio_cansleep __gpio_cansleep
++#define gpio_to_irq __gpio_to_irq
++
++static inline int irq_to_gpio(unsigned irq)
++{
++ return -EINVAL;
++}
++
++#endif /* __ASM_MACH_ATH25_GPIO_H */
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath25/war.h
+@@ -0,0 +1,25 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
++ */
++#ifndef __ASM_MACH_ATH25_WAR_H
++#define __ASM_MACH_ATH25_WAR_H
++
++#define R4600_V1_INDEX_ICACHEOP_WAR 0
++#define R4600_V1_HIT_CACHEOP_WAR 0
++#define R4600_V2_HIT_CACHEOP_WAR 0
++#define R5432_CP0_INTERRUPT_WAR 0
++#define BCM1250_M3_WAR 0
++#define SIBYTE_1956_WAR 0
++#define MIPS4K_ICACHE_REFILL_WAR 0
++#define MIPS_CACHE_SYNC_WAR 0
++#define TX49XX_ICACHE_INDEX_INV_WAR 0
++#define RM9000_CDEX_SMP_WAR 0
++#define ICACHE_REFILLS_WORKAROUND_WAR 0
++#define R10000_LLSC_WAR 0
++#define MIPS34K_MISSED_ITLB_WAR 0
++
++#endif /* __ASM_MACH_ATH25_WAR_H */
+--- /dev/null
++++ b/arch/mips/ath25/ar2315_regs.h
+@@ -0,0 +1,410 @@
++/*
++ * Register definitions for AR2315+
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
++ */
++
++#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
++#define __ASM_MACH_ATH25_AR2315_REGS_H
++
++/*
++ * IRQs
++ */
++#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
++#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
++#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
++#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
++#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
++
++/*
++ * Miscellaneous interrupts, which share IP2.
++ */
++#define AR2315_MISC_IRQ_UART0 0
++#define AR2315_MISC_IRQ_I2C_RSVD 1
++#define AR2315_MISC_IRQ_SPI 2
++#define AR2315_MISC_IRQ_AHB 3
++#define AR2315_MISC_IRQ_APB 4
++#define AR2315_MISC_IRQ_TIMER 5
++#define AR2315_MISC_IRQ_GPIO 6
++#define AR2315_MISC_IRQ_WATCHDOG 7
++#define AR2315_MISC_IRQ_IR_RSVD 8
++#define AR2315_MISC_IRQ_COUNT 9
++
++/*
++ * Address map
++ */
++#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
++#define AR2315_SPI_READ_SIZE 0x01000000
++#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
++#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
++#define AR2315_PCI_SIZE 0x00001000
++#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
++#define AR2315_SDRAMCTL_SIZE 0x00000020
++#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
++#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
++#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
++#define AR2315_RST_SIZE 0x00000100
++#define AR2315_UART0_BASE 0x11100000 /* UART MMR */
++#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
++#define AR2315_SPI_MMR_SIZE 0x00000010
++#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
++#define AR2315_PCI_EXT_SIZE 0x40000000
++
++/*
++ * Configuration registers
++ */
++
++/* Cold reset register */
++#define AR2315_COLD_RESET 0x0000
++
++#define AR2315_RESET_COLD_AHB 0x00000001
++#define AR2315_RESET_COLD_APB 0x00000002
++#define AR2315_RESET_COLD_CPU 0x00000004
++#define AR2315_RESET_COLD_CPUWARM 0x00000008
++#define AR2315_RESET_SYSTEM (RESET_COLD_CPU |\
++ RESET_COLD_APB |\
++ RESET_COLD_AHB) /* full system */
++#define AR2317_RESET_SYSTEM 0x00000010
++
++/* Reset register */
++#define AR2315_RESET 0x0004
++
++#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
++#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BB */
++#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
++#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
++#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset mem control */
++#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
++#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
++#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI iface */
++#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
++#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR iface */
++#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
++#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 MAC */
++
++/* AHB master arbitration control */
++#define AR2315_AHB_ARB_CTL 0x0008
++
++#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
++#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
++#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
++#define AR2315_ARB_LOCAL 0x00000008 /* Local bus */
++#define AR2315_ARB_PCI 0x00000010 /* PCI bus */
++#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
++#define AR2315_ARB_RETRY 0x00000100 /* Retry policy (debug) */
++
++/* Config Register */
++#define AR2315_ENDIAN_CTL 0x000c
++
++#define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
++#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
++#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
++#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
++#define AR2315_CONFIG_MEMCTL 0x00000010 /* Mem controller endian */
++#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
++#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
++#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
++#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
++#define AR2315_CONFIG_BIG 0x00000400
++#define AR2315_CONFIG_PCIAHB 0x00000800
++#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
++#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
++#define AR2315_CONFIG_CPU_DRAM 0x00010000
++#define AR2315_CONFIG_CPU_PCI 0x00020000
++#define AR2315_CONFIG_CPU_MMR 0x00040000
++
++/* NMI control */
++#define AR2315_NMI_CTL 0x0010
++
++#define AR2315_NMI_EN 1
++
++/* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
++#define AR2315_SREV 0x0014
++
++#define AR2315_REV_MAJ 0x000000f0
++#define AR2315_REV_MAJ_S 4
++#define AR2315_REV_MIN 0x0000000f
++#define AR2315_REV_MIN_S 0
++#define AR2315_REV_CHIP (AR2315_REV_MAJ | AR2315_REV_MIN)
++
++/* Interface Enable */
++#define AR2315_IF_CTL 0x0018
++
++#define AR2315_IF_MASK 0x00000007
++#define AR2315_IF_DISABLED 0 /* Disable all */
++#define AR2315_IF_PCI 1 /* PCI */
++#define AR2315_IF_TS_LOCAL 2 /* Local bus */
++#define AR2315_IF_ALL 3 /* Emulation only */
++#define AR2315_IF_LOCAL_HOST 0x00000008
++#define AR2315_IF_PCI_HOST 0x00000010
++#define AR2315_IF_PCI_INTR 0x00000020
++#define AR2315_IF_PCI_CLK_MASK 0x00030000
++#define AR2315_IF_PCI_CLK_INPUT 0
++#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
++#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
++#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
++#define AR2315_IF_PCI_CLK_SHIFT 16
++
++/* APB Interrupt control */
++#define AR2315_ISR 0x0020
++#define AR2315_IMR 0x0024
++#define AR2315_GISR 0x0028
++
++#define AR2315_ISR_UART0 0x00000001 /* high speed UART */
++#define AR2315_ISR_I2C_RSVD 0x00000002 /* I2C bus */
++#define AR2315_ISR_SPI 0x00000004 /* SPI bus */
++#define AR2315_ISR_AHB 0x00000008 /* AHB error */
++#define AR2315_ISR_APB 0x00000010 /* APB error */
++#define AR2315_ISR_TIMER 0x00000020 /* Timer */
++#define AR2315_ISR_GPIO 0x00000040 /* GPIO */
++#define AR2315_ISR_WD 0x00000080 /* Watchdog */
++#define AR2315_ISR_IR_RSVD 0x00000100 /* IR */
++
++#define AR2315_GISR_MISC 0x00000001 /* Misc */
++#define AR2315_GISR_WLAN0 0x00000002 /* WLAN0 */
++#define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
++#define AR2315_GISR_LOCALPCI 0x00000008 /* Local/PCI bus */
++#define AR2315_GISR_WMACPOLL 0x00000010
++#define AR2315_GISR_TIMER 0x00000020
++#define AR2315_GISR_ETHERNET 0x00000040 /* Ethernet */
++
++/* Generic timer */
++#define AR2315_TIMER 0x0030
++#define AR2315_RELOAD 0x0034
++
++/* Watchdog timer */
++#define AR2315_WDT_TIMER 0x0038
++#define AR2315_WDT_CTRL 0x003c
++
++#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
++#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
++#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
++
++/* CPU Performance Counters */
++#define AR2315_PERFCNT0 0x0048
++#define AR2315_PERFCNT1 0x004c
++
++#define AR2315_PERF0_DATAHIT 0x00000001 /* Count Data Cache Hits */
++#define AR2315_PERF0_DATAMISS 0x00000002 /* Count Data Cache Misses */
++#define AR2315_PERF0_INSTHIT 0x00000004 /* Count Instruction Cache Hits */
++#define AR2315_PERF0_INSTMISS 0x00000008 /* Count Instruction Cache Misses */
++#define AR2315_PERF0_ACTIVE 0x00000010 /* Count Active Processor Cycles */
++#define AR2315_PERF0_WBHIT 0x00000020 /* Count CPU Write Buffer Hits */
++#define AR2315_PERF0_WBMISS 0x00000040 /* Count CPU Write Buffer Misses */
++
++#define AR2315_PERF1_EB_ARDY 0x00000001 /* Count EB_ARdy signal */
++#define AR2315_PERF1_EB_AVALID 0x00000002 /* Count EB_AValid signal */
++#define AR2315_PERF1_EB_WDRDY 0x00000004 /* Count EB_WDRdy signal */
++#define AR2315_PERF1_EB_RDVAL 0x00000008 /* Count EB_RdVal signal */
++#define AR2315_PERF1_VRADDR 0x00000010 /* Count valid read address cycles*/
++#define AR2315_PERF1_VWADDR 0x00000020 /* Count valid write address cycl.*/
++#define AR2315_PERF1_VWDATA 0x00000040 /* Count valid write data cycles */
++
++/* AHB Error Reporting */
++#define AR2315_AHB_ERR0 0x0050 /* error */
++#define AR2315_AHB_ERR1 0x0054 /* haddr */
++#define AR2315_AHB_ERR2 0x0058 /* hwdata */
++#define AR2315_AHB_ERR3 0x005c /* hrdata */
++#define AR2315_AHB_ERR4 0x0060 /* status */
++
++#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */
++ /* write 1 to clear all bits in ERR0 */
++#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
++#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
++
++#define AR2315_PROCERR_HMAST 0x0000000f
++#define AR2315_PROCERR_HMAST_DFLT 0
++#define AR2315_PROCERR_HMAST_WMAC 1
++#define AR2315_PROCERR_HMAST_ENET 2
++#define AR2315_PROCERR_HMAST_PCIENDPT 3
++#define AR2315_PROCERR_HMAST_LOCAL 4
++#define AR2315_PROCERR_HMAST_CPU 5
++#define AR2315_PROCERR_HMAST_PCITGT 6
++#define AR2315_PROCERR_HMAST_S 0
++#define AR2315_PROCERR_HWRITE 0x00000010
++#define AR2315_PROCERR_HSIZE 0x00000060
++#define AR2315_PROCERR_HSIZE_S 5
++#define AR2315_PROCERR_HTRANS 0x00000180
++#define AR2315_PROCERR_HTRANS_S 7
++#define AR2315_PROCERR_HBURST 0x00000e00
++#define AR2315_PROCERR_HBURST_S 9
++
++/* Clock Control */
++#define AR2315_PLLC_CTL 0x0064
++#define AR2315_PLLV_CTL 0x0068
++#define AR2315_CPUCLK 0x006c
++#define AR2315_AMBACLK 0x0070
++#define AR2315_SYNCCLK 0x0074
++#define AR2315_DSL_SLEEP_CTL 0x0080
++#define AR2315_DSL_SLEEP_DUR 0x0084
++
++/* PLLc Control fields */
++#define AR2315_PLLC_REF_DIV_M 0x00000003
++#define AR2315_PLLC_REF_DIV_S 0
++#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c
++#define AR2315_PLLC_FDBACK_DIV_S 2
++#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080
++#define AR2315_PLLC_ADD_FDBACK_DIV_S 7
++#define AR2315_PLLC_CLKC_DIV_M 0x0001c000
++#define AR2315_PLLC_CLKC_DIV_S 14
++#define AR2315_PLLC_CLKM_DIV_M 0x00700000
++#define AR2315_PLLC_CLKM_DIV_S 20
++
++/* CPU CLK Control fields */
++#define AR2315_CPUCLK_CLK_SEL_M 0x00000003
++#define AR2315_CPUCLK_CLK_SEL_S 0
++#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c
++#define AR2315_CPUCLK_CLK_DIV_S 2
++
++/* AMBA CLK Control fields */
++#define AR2315_AMBACLK_CLK_SEL_M 0x00000003
++#define AR2315_AMBACLK_CLK_SEL_S 0
++#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
++#define AR2315_AMBACLK_CLK_DIV_S 2
++
++/* PCI Clock Control */
++#define AR2315_PCICLK 0x00a4
++
++#define AR2315_PCICLK_INPUT_M 0x00000003
++#define AR2315_PCICLK_INPUT_S 0
++#define AR2315_PCICLK_PLLC_CLKM 0
++#define AR2315_PCICLK_PLLC_CLKM1 1
++#define AR2315_PCICLK_PLLC_CLKC 2
++#define AR2315_PCICLK_REF_CLK 3
++#define AR2315_PCICLK_DIV_M 0x0000000c
++#define AR2315_PCICLK_DIV_S 2
++#define AR2315_PCICLK_IN_FREQ 0
++#define AR2315_PCICLK_IN_FREQ_DIV_6 1
++#define AR2315_PCICLK_IN_FREQ_DIV_8 2
++#define AR2315_PCICLK_IN_FREQ_DIV_10 3
++
++/* Observation Control Register */
++#define AR2315_OCR 0x00b0
++
++#define AR2315_OCR_GPIO0_IRIN 0x00000040
++#define AR2315_OCR_GPIO1_IROUT 0x00000080
++#define AR2315_OCR_GPIO3_RXCLR 0x00000200
++
++/* General Clock Control */
++#define AR2315_MISCCLK 0x00b4
++
++#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
++#define AR2315_MISCCLK_PROCREFCLK 0x00000002
++
++/*
++ * SDRAM Controller
++ * - No read or write buffers are included.
++ */
++#define AR2315_MEM_CFG 0x0000
++#define AR2315_MEM_CTRL 0x000c
++#define AR2315_MEM_REF 0x0010
++
++#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000
++#define AR2315_MEM_CFG_DATA_WIDTH_S 13
++#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00
++#define AR2315_MEM_CFG_COL_WIDTH_S 9
++#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0
++#define AR2315_MEM_CFG_ROW_WIDTH_S 5
++#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
++#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
++
++/*
++ * Local Bus Interface Registers
++ */
++#define AR2315_LB_CONFIG 0x0000
++
++#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
++#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
++#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
++#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
++#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
++#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
++#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
++#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
++#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
++#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
++#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
++#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
++#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
++#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
++#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
++#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
++#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
++#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
++#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
++#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
++#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
++#define AR2315_LBCONF_INT_CTR3 0x000c0000 /* GND drive, Vdd drive */
++#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
++#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
++#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
++
++#define AR2315_LB_CLKSEL 0x0004
++
++#define AR2315_LBCLK_EXT 0x00000001 /* use external clk for lb */
++
++#define AR2315_LB_1MS 0x0008
++
++#define AR2315_LB1MS_MASK 0x0003ffff /* # of AHB clk cycles in 1ms */
++
++#define AR2315_LB_MISCCFG 0x000c
++
++#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
++#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
++#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
++#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
++#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
++#define AR2315_LBM_TIMEOUT_M 0x00ffff80
++#define AR2315_LBM_TIMEOUT_S 7
++#define AR2315_LBM_PORTMUX 0x07000000
++
++#define AR2315_LB_RXTSOFF 0x0010
++
++#define AR2315_LB_TX_CHAIN_EN 0x0100
++
++#define AR2315_LB_TXEN_0 0x00000001
++#define AR2315_LB_TXEN_1 0x00000002
++#define AR2315_LB_TXEN_2 0x00000004
++#define AR2315_LB_TXEN_3 0x00000008
++
++#define AR2315_LB_TX_CHAIN_DIS 0x0104
++#define AR2315_LB_TX_DESC_PTR 0x0200
++
++#define AR2315_LB_RX_CHAIN_EN 0x0400
++
++#define AR2315_LB_RXEN 0x00000001
++
++#define AR2315_LB_RX_CHAIN_DIS 0x0404
++#define AR2315_LB_RX_DESC_PTR 0x0408
++
++#define AR2315_LB_INT_STATUS 0x0500
++
++#define AR2315_LB_INT_TX_DESC 0x00000001
++#define AR2315_LB_INT_TX_OK 0x00000002
++#define AR2315_LB_INT_TX_ERR 0x00000004
++#define AR2315_LB_INT_TX_EOF 0x00000008
++#define AR2315_LB_INT_RX_DESC 0x00000010
++#define AR2315_LB_INT_RX_OK 0x00000020
++#define AR2315_LB_INT_RX_ERR 0x00000040
++#define AR2315_LB_INT_RX_EOF 0x00000080
++#define AR2315_LB_INT_TX_TRUNC 0x00000100
++#define AR2315_LB_INT_TX_STARVE 0x00000200
++#define AR2315_LB_INT_LB_TIMEOUT 0x00000400
++#define AR2315_LB_INT_LB_ERR 0x00000800
++#define AR2315_LB_INT_MBOX_WR 0x00001000
++#define AR2315_LB_INT_MBOX_RD 0x00002000
++
++/* Bit definitions for INT MASK are the same as INT_STATUS */
++#define AR2315_LB_INT_MASK 0x0504
++
++#define AR2315_LB_INT_EN 0x0508
++#define AR2315_LB_MBOX 0x0600
++
++#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
+--- /dev/null
++++ b/arch/mips/ath25/ar5312_regs.h
+@@ -0,0 +1,224 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
++ */
++
++#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
++#define __ASM_MACH_ATH25_AR5312_REGS_H
++
++/*
++ * IRQs
++ */
++#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
++#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
++#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
++#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
++#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
++
++/*
++ * Miscellaneous interrupts, which share IP6.
++ */
++#define AR5312_MISC_IRQ_TIMER 0
++#define AR5312_MISC_IRQ_AHB_PROC 1
++#define AR5312_MISC_IRQ_AHB_DMA 2
++#define AR5312_MISC_IRQ_GPIO 3
++#define AR5312_MISC_IRQ_UART0 4
++#define AR5312_MISC_IRQ_UART0_DMA 5
++#define AR5312_MISC_IRQ_WATCHDOG 6
++#define AR5312_MISC_IRQ_LOCAL 7
++#define AR5312_MISC_IRQ_SPI 8
++#define AR5312_MISC_IRQ_COUNT 9
++
++/*
++ * Address Map
++ *
++ * The AR5312 supports 2 enet MACS, even though many reference boards only
++ * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
++ * PHY or PHY switch. The AR2312 supports 1 enet MAC.
++ */
++#define AR5312_WLAN0_BASE 0x18000000
++#define AR5312_ENET0_BASE 0x18100000
++#define AR5312_ENET1_BASE 0x18200000
++#define AR5312_SDRAMCTL_BASE 0x18300000
++#define AR5312_SDRAMCTL_SIZE 0x00000010
++#define AR5312_FLASHCTL_BASE 0x18400000
++#define AR5312_FLASHCTL_SIZE 0x00000010
++#define AR5312_WLAN1_BASE 0x18500000
++#define AR5312_UART0_BASE 0x1c000000 /* UART MMR */
++#define AR5312_GPIO_BASE 0x1c002000
++#define AR5312_GPIO_SIZE 0x00000010
++#define AR5312_RST_BASE 0x1c003000
++#define AR5312_RST_SIZE 0x00000100
++#define AR5312_FLASH_BASE 0x1e000000
++#define AR5312_FLASH_SIZE 0x00800000
++
++/*
++ * Need these defines to determine true number of ethernet MACs
++ */
++#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
++#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
++#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
++
++/* Reset/Timer Block Address Map */
++#define AR5312_TIMER 0x0000 /* countdown timer */
++#define AR5312_RELOAD 0x0004 /* timer reload value */
++#define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */
++#define AR5312_WDT_TIMER 0x000c /* watchdog timer */
++#define AR5312_ISR 0x0010 /* Intr Status Reg */
++#define AR5312_IMR 0x0014 /* Intr Mask Reg */
++#define AR5312_RESET 0x0020
++#define AR5312_CLOCKCTL1 0x0064
++#define AR5312_SCRATCH 0x006c
++#define AR5312_PROCADDR 0x0070
++#define AR5312_PROC1 0x0074
++#define AR5312_DMAADDR 0x0078
++#define AR5312_DMA1 0x007c
++#define AR5312_ENABLE 0x0080 /* interface enb */
++#define AR5312_REV 0x0090 /* revision */
++
++/* AR5312_WDT_CTRL register bit field definitions */
++#define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
++#define AR5312_WDT_CTRL_NMI 0x00000001
++#define AR5312_WDT_CTRL_RESET 0x00000002
++
++/* AR5312_ISR register bit field definitions */
++#define AR5312_ISR_TIMER 0x00000001
++#define AR5312_ISR_AHBPROC 0x00000002
++#define AR5312_ISR_AHBDMA 0x00000004
++#define AR5312_ISR_GPIO 0x00000008
++#define AR5312_ISR_UART0 0x00000010
++#define AR5312_ISR_UART0DMA 0x00000020
++#define AR5312_ISR_WD 0x00000040
++#define AR5312_ISR_LOCAL 0x00000080
++
++/* AR5312_RESET register bit field definitions */
++#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
++#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
++#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC/BB */
++#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
++#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
++#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 MAC */
++#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 MAC */
++#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 */
++#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
++#define AR5312_RESET_APB 0x00000400 /* cold reset APB ar5312 */
++#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
++#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
++#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BB */
++#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the CPU */
++#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 MAC */
++#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 BB */
++#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
++#define AR5312_RESET_WDOG 0x00100000 /* last reset was a wdt */
++
++#define AR5312_RESET_WMAC0_BITS (AR5312_RESET_WLAN0 |\
++ AR5312_RESET_WARM_WLAN0_MAC |\
++ AR5312_RESET_WARM_WLAN0_BB)
++
++#define AR5312_RESET_WMAC1_BITS (AR5312_RESET_WLAN1 |\
++ AR5312_RESET_WARM_WLAN1_MAC |\
++ AR5312_RESET_WARM_WLAN1_BB)
++
++/* AR5312_CLOCKCTL1 register bit field definitions */
++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
++
++/* Valid for AR5312 and AR2312 */
++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
++
++/* Valid for AR2313 */
++#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
++#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
++#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
++#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
++#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
++
++/* AR5312_ENABLE register bit field definitions */
++#define AR5312_ENABLE_WLAN0 0x00000001
++#define AR5312_ENABLE_ENET0 0x00000002
++#define AR5312_ENABLE_ENET1 0x00000004
++#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x00000008/* UART & WLAN1 PIO */
++#define AR5312_ENABLE_WLAN1_DMA 0x00000010/* WLAN1 DMAs */
++#define AR5312_ENABLE_WLAN1 (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
++ AR5312_ENABLE_WLAN1_DMA)
++
++/* AR5312_REV register bit field definitions */
++#define AR5312_REV_WMAC_MAJ 0x0000f000
++#define AR5312_REV_WMAC_MAJ_S 12
++#define AR5312_REV_WMAC_MIN 0x00000f00
++#define AR5312_REV_WMAC_MIN_S 8
++#define AR5312_REV_MAJ 0x000000f0
++#define AR5312_REV_MAJ_S 4
++#define AR5312_REV_MIN 0x0000000f
++#define AR5312_REV_MIN_S 0
++#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
++
++/* Major revision numbers, bits 7..4 of Revision ID register */
++#define AR5312_REV_MAJ_AR5312 0x4
++#define AR5312_REV_MAJ_AR2313 0x5
++
++/* Minor revision numbers, bits 3..0 of Revision ID register */
++#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
++#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
++
++/*
++ * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
++ */
++#define AR5312_FLASHCTL0 0x0000
++#define AR5312_FLASHCTL1 0x0004
++#define AR5312_FLASHCTL2 0x0008
++
++/* AR5312_FLASHCTL register bit field definitions */
++#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */
++#define AR5312_FLASHCTL_IDCY_S 0
++#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
++#define AR5312_FLASHCTL_WST1_S 5
++#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
++#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
++#define AR5312_FLASHCTL_WST2_S 11
++#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */
++#define AR5312_FLASHCTL_AC_S 16
++#define AR5312_FLASHCTL_AC_128K 0x00000000
++#define AR5312_FLASHCTL_AC_256K 0x00010000
++#define AR5312_FLASHCTL_AC_512K 0x00020000
++#define AR5312_FLASHCTL_AC_1M 0x00030000
++#define AR5312_FLASHCTL_AC_2M 0x00040000
++#define AR5312_FLASHCTL_AC_4M 0x00050000
++#define AR5312_FLASHCTL_AC_8M 0x00060000
++#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
++#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
++#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */
++#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */
++#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */
++#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */
++#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
++#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
++#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
++#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */
++#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */
++#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
++#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */
++
++/*
++ * ARM SDRAM Controller -- just enough to determine memory size
++ */
++#define AR5312_MEM_CFG1 0x0004
++
++#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */
++#define AR5312_MEM_CFG1_AC0_S 8
++#define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */
++#define AR5312_MEM_CFG1_AC1_S 12
++
++#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
+--- /dev/null
++++ b/arch/mips/ath25/ar5312.c
+@@ -0,0 +1,393 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
++ */
++
++/*
++ * Platform devices for Atheros AR5312 SoCs
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/physmap.h>
++#include <linux/reboot.h>
++#include <asm/bootinfo.h>
++#include <asm/reboot.h>
++#include <asm/time.h>
++
++#include <ath25_platform.h>
++
++#include "devices.h"
++#include "ar5312.h"
++#include "ar5312_regs.h"
++
++static void __iomem *ar5312_rst_base;
++static struct irq_domain *ar5312_misc_irq_domain;
++
++static inline u32 ar5312_rst_reg_read(u32 reg)
++{
++ return __raw_readl(ar5312_rst_base + reg);
++}
++
++static inline void ar5312_rst_reg_write(u32 reg, u32 val)
++{
++ __raw_writel(val, ar5312_rst_base + reg);
++}
++
++static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
++{
++ u32 ret = ar5312_rst_reg_read(reg);
++
++ ret &= ~mask;
++ ret |= val;
++ ar5312_rst_reg_write(reg, ret);
++}
++
++static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
++{
++ u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
++ u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
++ u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
++ u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
++
++ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
++ proc_addr, proc1, dma_addr, dma1);
++
++ machine_restart("AHB error"); /* Catastrophic failure */
++ return IRQ_HANDLED;
++}
++
++static struct irqaction ar5312_ahb_err_interrupt = {
++ .handler = ar5312_ahb_err_handler,
++ .name = "ar5312-ahb-error",
++};
++
++static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
++{
++ u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
++ ar5312_rst_reg_read(AR5312_IMR);
++ unsigned nr, misc_irq = 0;
++
++ if (pending) {
++ struct irq_domain *domain = irq_get_handler_data(irq);
++
++ nr = __ffs(pending);
++ misc_irq = irq_find_mapping(domain, nr);
++ }
++
++ if (misc_irq) {
++ generic_handle_irq(misc_irq);
++ if (nr == AR5312_MISC_IRQ_TIMER)
++ ar5312_rst_reg_read(AR5312_TIMER);
++ } else {
++ spurious_interrupt();
++ }
++}
++
++/* Enable the specified AR5312_MISC_IRQ interrupt */
++static void ar5312_misc_irq_unmask(struct irq_data *d)
++{
++ ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
++}
++
++/* Disable the specified AR5312_MISC_IRQ interrupt */
++static void ar5312_misc_irq_mask(struct irq_data *d)
++{
++ ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
++ ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
++}
++
++static struct irq_chip ar5312_misc_irq_chip = {
++ .name = "ar5312-misc",
++ .irq_unmask = ar5312_misc_irq_unmask,
++ .irq_mask = ar5312_misc_irq_mask,
++};
++
++static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
++ irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
++ return 0;
++}
++
++static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
++ .map = ar5312_misc_irq_map,
++};
++
++static void ar5312_irq_dispatch(void)
++{
++ u32 pending = read_c0_status() & read_c0_cause();
++
++ if (pending & CAUSEF_IP2)
++ do_IRQ(AR5312_IRQ_WLAN0);
++ else if (pending & CAUSEF_IP5)
++ do_IRQ(AR5312_IRQ_WLAN1);
++ else if (pending & CAUSEF_IP6)
++ do_IRQ(AR5312_IRQ_MISC);
++ else if (pending & CAUSEF_IP7)
++ do_IRQ(ATH25_IRQ_CPU_CLOCK);
++ else
++ spurious_interrupt();
++}
++
++void __init ar5312_arch_init_irq(void)
++{
++ struct irq_domain *domain;
++ unsigned irq;
++
++ ath25_irq_dispatch = ar5312_irq_dispatch;
++
++ domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
++ &ar5312_misc_irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add IRQ domain");
++
++ irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
++ setup_irq(irq, &ar5312_ahb_err_interrupt);
++
++ irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
++ irq_set_handler_data(AR5312_IRQ_MISC, domain);
++
++ ar5312_misc_irq_domain = domain;
++}
++
++static struct physmap_flash_data ar5312_flash_data = {
++ .width = 2,
++};
++
++static struct resource ar5312_flash_resource = {
++ .start = AR5312_FLASH_BASE,
++ .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device ar5312_physmap_flash = {
++ .name = "physmap-flash",
++ .id = 0,
++ .dev.platform_data = &ar5312_flash_data,
++ .resource = &ar5312_flash_resource,
++ .num_resources = 1,
++};
++
++static void __init ar5312_flash_init(void)
++{
++ void __iomem *flashctl_base;
++ u32 ctl;
++
++ flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
++ AR5312_FLASHCTL_SIZE);
++
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
++ ctl &= AR5312_FLASHCTL_MW;
++
++ /* fixup flash width */
++ switch (ctl) {
++ case AR5312_FLASHCTL_MW16:
++ ar5312_flash_data.width = 2;
++ break;
++ case AR5312_FLASHCTL_MW8:
++ default:
++ ar5312_flash_data.width = 1;
++ break;
++ }
++
++ /*
++ * Configure flash bank 0.
++ * Assume 8M window size. Flash will be aliased if it's smaller
++ */
++ ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
++ ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
++ ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
++ ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
++
++ /* Disable other flash banks */
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
++ ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
++ ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
++
++ iounmap(flashctl_base);
++}
++
++void __init ar5312_init_devices(void)
++{
++ struct ath25_boarddata *config;
++
++ ar5312_flash_init();
++
++ /* Locate board/radio config data */
++ ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
++ config = ath25_board.config;
++
++ /* AR2313 has CPU minor rev. 10 */
++ if ((current_cpu_data.processor_id & 0xff) == 0x0a)
++ ath25_soc = ATH25_SOC_AR2313;
++
++ /* AR2312 shares the same Silicon ID as AR5312 */
++ else if (config->flags & BD_ISCASPER)
++ ath25_soc = ATH25_SOC_AR2312;
++
++ /* Everything else is probably AR5312 or compatible */
++ else
++ ath25_soc = ATH25_SOC_AR5312;
++
++ platform_device_register(&ar5312_physmap_flash);
++
++ switch (ath25_soc) {
++ case ATH25_SOC_AR5312:
++ if (!ath25_board.radio)
++ return;
++
++ if (!(config->flags & BD_WLAN0))
++ break;
++
++ ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
++ break;
++ case ATH25_SOC_AR2312:
++ case ATH25_SOC_AR2313:
++ if (!ath25_board.radio)
++ return;
++ break;
++ default:
++ break;
++ }
++
++ if (config->flags & BD_WLAN1)
++ ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
++}
++
++static void ar5312_restart(char *command)
++{
++ /* reset the system */
++ local_irq_disable();
++ while (1)
++ ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
++}
++
++/*
++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
++ * to determine the predevisor value.
++ */
++static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
++
++static unsigned __init ar5312_cpu_frequency(void)
++{
++ u32 scratch, devid, clock_ctl1;
++ u32 predivide_mask, multiplier_mask, doubler_mask;
++ unsigned predivide_shift, multiplier_shift;
++ unsigned predivide_select, predivisor, multiplier;
++
++ /* Trust the bootrom's idea of cpu frequency. */
++ scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
++ if (scratch)
++ return scratch;
++
++ devid = ar5312_rst_reg_read(AR5312_REV);
++ devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
++ if (devid == AR5312_REV_MAJ_AR2313) {
++ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
++ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
++ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
++ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
++ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
++ } else { /* AR5312 and AR2312 */
++ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
++ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
++ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
++ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
++ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
++ }
++
++ /*
++ * Clocking is derived from a fixed 40MHz input clock.
++ *
++ * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
++ * sys_freq = cpu_freq / 4 (used for APB clock, serial,
++ * flash, Timer, Watchdog Timer)
++ *
++ * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
++ *
++ * So, for example, with a PLL multiplier of 5, we have
++ *
++ * cpu_freq = 200MHz
++ * sys_freq = 50MHz
++ * cnt_freq = 100MHz
++ *
++ * We compute the CPU frequency, based on PLL settings.
++ */
++
++ clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
++ predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
++ predivisor = clockctl1_predivide_table[predivide_select];
++ multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
++
++ if (clock_ctl1 & doubler_mask)
++ multiplier <<= 1;
++
++ return (40000000 / predivisor) * multiplier;
++}
++
++static inline unsigned ar5312_sys_frequency(void)
++{
++ return ar5312_cpu_frequency() / 4;
++}
++
++void __init ar5312_plat_time_init(void)
++{
++ mips_hpt_frequency = ar5312_cpu_frequency() / 2;
++}
++
++void __init ar5312_plat_mem_setup(void)
++{
++ void __iomem *sdram_base;
++ u32 memsize, memcfg, bank0_ac, bank1_ac;
++ u32 devid;
++
++ /* Detect memory size */
++ sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
++ AR5312_SDRAMCTL_SIZE);
++ memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
++ bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
++ bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
++ memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
++ (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
++ memsize <<= 20;
++ add_memory_region(0, memsize, BOOT_MEM_RAM);
++ iounmap(sdram_base);
++
++ ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
++
++ devid = ar5312_rst_reg_read(AR5312_REV);
++ devid >>= AR5312_REV_WMAC_MIN_S;
++ devid &= AR5312_REV_CHIP;
++ ath25_board.devid = (u16)devid;
++
++ /* Clear any lingering AHB errors */
++ ar5312_rst_reg_read(AR5312_PROCADDR);
++ ar5312_rst_reg_read(AR5312_DMAADDR);
++ ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
++
++ _machine_restart = ar5312_restart;
++}
++
++void __init ar5312_arch_init(void)
++{
++ unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
++ AR5312_MISC_IRQ_UART0);
++
++ ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
++}
+--- /dev/null
++++ b/arch/mips/ath25/ar2315.c
+@@ -0,0 +1,308 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
++ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
++ */
++
++/*
++ * Platform devices for Atheros AR2315 SoCs
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/reboot.h>
++#include <asm/bootinfo.h>
++#include <asm/reboot.h>
++#include <asm/time.h>
++
++#include <ath25_platform.h>
++
++#include "devices.h"
++#include "ar2315.h"
++#include "ar2315_regs.h"
++
++static void __iomem *ar2315_rst_base;
++static struct irq_domain *ar2315_misc_irq_domain;
++
++static inline u32 ar2315_rst_reg_read(u32 reg)
++{
++ return __raw_readl(ar2315_rst_base + reg);
++}
++
++static inline void ar2315_rst_reg_write(u32 reg, u32 val)
++{
++ __raw_writel(val, ar2315_rst_base + reg);
++}
++
++static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
++{
++ u32 ret = ar2315_rst_reg_read(reg);
++
++ ret &= ~mask;
++ ret |= val;
++ ar2315_rst_reg_write(reg, ret);
++}
++
++static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
++{
++ ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
++ ar2315_rst_reg_read(AR2315_AHB_ERR1);
++
++ pr_emerg("AHB fatal error\n");
++ machine_restart("AHB error"); /* Catastrophic failure */
++
++ return IRQ_HANDLED;
++}
++
++static struct irqaction ar2315_ahb_err_interrupt = {
++ .handler = ar2315_ahb_err_handler,
++ .name = "ar2315-ahb-error",
++};
++
++static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
++{
++ u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
++ ar2315_rst_reg_read(AR2315_IMR);
++ unsigned nr, misc_irq = 0;
++
++ if (pending) {
++ struct irq_domain *domain = irq_get_handler_data(irq);
++
++ nr = __ffs(pending);
++ misc_irq = irq_find_mapping(domain, nr);
++ }
++
++ if (misc_irq) {
++ if (nr == AR2315_MISC_IRQ_GPIO)
++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
++ else if (nr == AR2315_MISC_IRQ_WATCHDOG)
++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
++ generic_handle_irq(misc_irq);
++ } else {
++ spurious_interrupt();
++ }
++}
++
++static void ar2315_misc_irq_unmask(struct irq_data *d)
++{
++ ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
++}
++
++static void ar2315_misc_irq_mask(struct irq_data *d)
++{
++ ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
++}
++
++static struct irq_chip ar2315_misc_irq_chip = {
++ .name = "ar2315-misc",
++ .irq_unmask = ar2315_misc_irq_unmask,
++ .irq_mask = ar2315_misc_irq_mask,
++};
++
++static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
++ irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
++ return 0;
++}
++
++static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
++ .map = ar2315_misc_irq_map,
++};
++
++/*
++ * Called when an interrupt is received, this function
++ * determines exactly which interrupt it was, and it
++ * invokes the appropriate handler.
++ *
++ * Implicitly, we also define interrupt priority by
++ * choosing which to dispatch first.
++ */
++static void ar2315_irq_dispatch(void)
++{
++ u32 pending = read_c0_status() & read_c0_cause();
++
++ if (pending & CAUSEF_IP3)
++ do_IRQ(AR2315_IRQ_WLAN0);
++ else if (pending & CAUSEF_IP2)
++ do_IRQ(AR2315_IRQ_MISC);
++ else if (pending & CAUSEF_IP7)
++ do_IRQ(ATH25_IRQ_CPU_CLOCK);
++ else
++ spurious_interrupt();
++}
++
++void __init ar2315_arch_init_irq(void)
++{
++ struct irq_domain *domain;
++ unsigned irq;
++
++ ath25_irq_dispatch = ar2315_irq_dispatch;
++
++ domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
++ &ar2315_misc_irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add IRQ domain");
++
++ irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
++ setup_irq(irq, &ar2315_ahb_err_interrupt);
++
++ irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
++ irq_set_handler_data(AR2315_IRQ_MISC, domain);
++
++ ar2315_misc_irq_domain = domain;
++}
++
++void __init ar2315_init_devices(void)
++{
++ /* Find board configuration */
++ ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
++
++ ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
++}
++
++static void ar2315_restart(char *command)
++{
++ void (*mips_reset_vec)(void) = (void *)0xbfc00000;
++
++ local_irq_disable();
++
++ /* try reset the system via reset control */
++ ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
++
++ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
++ * a workaround. Give it some time to attempt a gpio based hardware
++ * reset (atheros reference design workaround) */
++
++ /* TODO: implement the GPIO reset workaround */
++
++ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
++ * workaround. Attempt to jump to the mips reset location -
++ * the boot loader itself might be able to recover the system */
++ mips_reset_vec();
++}
++
++/*
++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
++ * to determine the predevisor value.
++ */
++static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
++static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
++
++static unsigned __init ar2315_sys_clk(u32 clock_ctl)
++{
++ unsigned int pllc_ctrl, cpu_div;
++ unsigned int pllc_out, refdiv, fdiv, divby2;
++ unsigned int clk_div;
++
++ pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
++ refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
++ refdiv = clockctl1_predivide_table[refdiv];
++ fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
++ divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
++ pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
++
++ /* clkm input selected */
++ switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
++ case 0:
++ case 1:
++ clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
++ clk_div = pllc_divide_table[clk_div];
++ break;
++ case 2:
++ clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
++ clk_div = pllc_divide_table[clk_div];
++ break;
++ default:
++ pllc_out = 40000000;
++ clk_div = 1;
++ break;
++ }
++
++ cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
++ cpu_div = cpu_div * 2 ?: 1;
++
++ return pllc_out / (clk_div * cpu_div);
++}
++
++static inline unsigned ar2315_cpu_frequency(void)
++{
++ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
++}
++
++static inline unsigned ar2315_apb_frequency(void)
++{
++ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
++}
++
++void __init ar2315_plat_time_init(void)
++{
++ mips_hpt_frequency = ar2315_cpu_frequency() / 2;
++}
++
++void __init ar2315_plat_mem_setup(void)
++{
++ void __iomem *sdram_base;
++ u32 memsize, memcfg;
++ u32 devid;
++ u32 config;
++
++ /* Detect memory size */
++ sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
++ AR2315_SDRAMCTL_SIZE);
++ memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
++ memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
++ memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
++ memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
++ memsize <<= 3;
++ add_memory_region(0, memsize, BOOT_MEM_RAM);
++ iounmap(sdram_base);
++
++ ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
++
++ /* Detect the hardware based on the device ID */
++ devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
++ switch (devid) {
++ case 0x91: /* Need to check */
++ ath25_soc = ATH25_SOC_AR2318;
++ break;
++ case 0x90:
++ ath25_soc = ATH25_SOC_AR2317;
++ break;
++ case 0x87:
++ ath25_soc = ATH25_SOC_AR2316;
++ break;
++ case 0x86:
++ default:
++ ath25_soc = ATH25_SOC_AR2315;
++ break;
++ }
++ ath25_board.devid = devid;
++
++ /* Clear any lingering AHB errors */
++ config = read_c0_config();
++ write_c0_config(config & ~0x3);
++ ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
++ ar2315_rst_reg_read(AR2315_AHB_ERR1);
++ ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
++
++ _machine_restart = ar2315_restart;
++}
++
++void __init ar2315_arch_init(void)
++{
++ unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
++ AR2315_MISC_IRQ_UART0);
++
++ ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
++}
+--- /dev/null
++++ b/arch/mips/ath25/ar2315.h
+@@ -0,0 +1,22 @@
++#ifndef __AR2315_H
++#define __AR2315_H
++
++#ifdef CONFIG_SOC_AR2315
++
++void ar2315_arch_init_irq(void);
++void ar2315_init_devices(void);
++void ar2315_plat_time_init(void);
++void ar2315_plat_mem_setup(void);
++void ar2315_arch_init(void);
++
++#else
++
++static inline void ar2315_arch_init_irq(void) {}
++static inline void ar2315_init_devices(void) {}
++static inline void ar2315_plat_time_init(void) {}
++static inline void ar2315_plat_mem_setup(void) {}
++static inline void ar2315_arch_init(void) {}
++
++#endif
++
++#endif /* __AR2315_H */
+--- /dev/null
++++ b/arch/mips/ath25/ar5312.h
+@@ -0,0 +1,22 @@
++#ifndef __AR5312_H
++#define __AR5312_H
++
++#ifdef CONFIG_SOC_AR5312
++
++void ar5312_arch_init_irq(void);
++void ar5312_init_devices(void);
++void ar5312_plat_time_init(void);
++void ar5312_plat_mem_setup(void);
++void ar5312_arch_init(void);
++
++#else
++
++static inline void ar5312_arch_init_irq(void) {}
++static inline void ar5312_init_devices(void) {}
++static inline void ar5312_plat_time_init(void) {}
++static inline void ar5312_plat_mem_setup(void) {}
++static inline void ar5312_arch_init(void) {}
++
++#endif
++
++#endif /* __AR5312_H */
+--- /dev/null
++++ b/arch/mips/ath25/devices.h
+@@ -0,0 +1,43 @@
++#ifndef __ATH25_DEVICES_H
++#define __ATH25_DEVICES_H
++
++#include <linux/cpu.h>
++
++#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
++
++#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
++
++enum ath25_soc_type {
++ /* handled by ar5312.c */
++ ATH25_SOC_AR2312,
++ ATH25_SOC_AR2313,
++ ATH25_SOC_AR5312,
++
++ /* handled by ar2315.c */
++ ATH25_SOC_AR2315,
++ ATH25_SOC_AR2316,
++ ATH25_SOC_AR2317,
++ ATH25_SOC_AR2318,
++
++ ATH25_SOC_UNKNOWN
++};
++
++extern enum ath25_soc_type ath25_soc;
++extern struct ar231x_board_config ath25_board;
++extern void (*ath25_irq_dispatch)(void);
++
++int ath25_find_config(phys_addr_t offset, unsigned long size);
++void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
++int ath25_add_wmac(int nr, u32 base, int irq);
++
++static inline bool is_ar2315(void)
++{
++ return (current_cpu_data.cputype == CPU_4KEC);
++}
++
++static inline bool is_ar5312(void)
++{
++ return !is_ar2315();
++}
++
++#endif
+--- /dev/null
++++ b/arch/mips/ath25/devices.c
+@@ -0,0 +1,125 @@
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/serial_8250.h>
++#include <linux/platform_device.h>
++#include <asm/bootinfo.h>
++
++#include <ath25_platform.h>
++#include "devices.h"
++#include "ar5312.h"
++#include "ar2315.h"
++
++struct ar231x_board_config ath25_board;
++enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
++
++static struct resource ath25_wmac0_res[] = {
++ {
++ .name = "wmac0_membase",
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "wmac0_irq",
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct resource ath25_wmac1_res[] = {
++ {
++ .name = "wmac1_membase",
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "wmac1_irq",
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device ath25_wmac[] = {
++ {
++ .id = 0,
++ .name = "ar231x-wmac",
++ .resource = ath25_wmac0_res,
++ .num_resources = ARRAY_SIZE(ath25_wmac0_res),
++ .dev.platform_data = &ath25_board,
++ },
++ {
++ .id = 1,
++ .name = "ar231x-wmac",
++ .resource = ath25_wmac1_res,
++ .num_resources = ARRAY_SIZE(ath25_wmac1_res),
++ .dev.platform_data = &ath25_board,
++ },
++};
++
++static const char * const soc_type_strings[] = {
++ [ATH25_SOC_AR5312] = "Atheros AR5312",
++ [ATH25_SOC_AR2312] = "Atheros AR2312",
++ [ATH25_SOC_AR2313] = "Atheros AR2313",
++ [ATH25_SOC_AR2315] = "Atheros AR2315",
++ [ATH25_SOC_AR2316] = "Atheros AR2316",
++ [ATH25_SOC_AR2317] = "Atheros AR2317",
++ [ATH25_SOC_AR2318] = "Atheros AR2318",
++ [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
++};
++
++const char *get_system_type(void)
++{
++ if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
++ !soc_type_strings[ath25_soc])
++ return soc_type_strings[ATH25_SOC_UNKNOWN];
++ return soc_type_strings[ath25_soc];
++}
++
++void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
++{
++ struct uart_port s;
++
++ memset(&s, 0, sizeof(s));
++
++ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
++ s.iotype = UPIO_MEM32;
++ s.irq = irq;
++ s.regshift = 2;
++ s.mapbase = mapbase;
++ s.uartclk = uartclk;
++
++ early_serial_setup(&s);
++}
++
++int __init ath25_add_wmac(int nr, u32 base, int irq)
++{
++ struct resource *res;
++
++ ath25_wmac[nr].dev.platform_data = &ath25_board;
++ res = &ath25_wmac[nr].resource[0];
++ res->start = base;
++ res->end = base + 0x10000 - 1;
++ res++;
++ res->start = irq;
++ res->end = irq;
++ return platform_device_register(&ath25_wmac[nr]);
++}
++
++static int __init ath25_register_devices(void)
++{
++ if (is_ar5312())
++ ar5312_init_devices();
++ else
++ ar2315_init_devices();
++
++ return 0;
++}
++
++device_initcall(ath25_register_devices);
++
++static int __init ath25_arch_init(void)
++{
++ if (is_ar5312())
++ ar5312_arch_init();
++ else
++ ar2315_arch_init();
++
++ return 0;
++}
++
++arch_initcall(ath25_arch_init);
--- /dev/null
+--- /dev/null
++++ b/arch/mips/ath25/early_printk.c
+@@ -0,0 +1,44 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
++ */
++
++#include <linux/mm.h>
++#include <linux/io.h>
++#include <linux/serial_reg.h>
++
++#include "devices.h"
++#include "ar2315_regs.h"
++#include "ar5312_regs.h"
++
++static inline void prom_uart_wr(void __iomem *base, unsigned reg,
++ unsigned char ch)
++{
++ __raw_writel(ch, base + 4 * reg);
++}
++
++static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg)
++{
++ return __raw_readl(base + 4 * reg);
++}
++
++void prom_putchar(unsigned char ch)
++{
++ static void __iomem *base;
++
++ if (unlikely(base == NULL)) {
++ if (is_ar2315())
++ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE));
++ else
++ base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE));
++ }
++
++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
++ ;
++ prom_uart_wr(base, UART_TX, ch);
++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
++ ;
++}
+--- a/arch/mips/ath25/Makefile
++++ b/arch/mips/ath25/Makefile
+@@ -9,5 +9,8 @@
+ #
+
+ obj-y += board.o prom.o devices.o
++
++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
++
+ obj-$(CONFIG_SOC_AR5312) += ar5312.o
+ obj-$(CONFIG_SOC_AR2315) += ar2315.o
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -106,6 +106,7 @@ config ATH25
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_HAS_EARLY_PRINTK
+ help
+ Support for Atheros AR231x and Atheros AR531x based boards
+
--- /dev/null
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
+ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
+ ops-bcm63xx.o
+ obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
++obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
+ obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
+ obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
+ obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
+--- /dev/null
++++ b/arch/mips/pci/pci-ar2315.c
+@@ -0,0 +1,511 @@
++/*
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++/**
++ * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
++ * and interrupt. PCI interface supports MMIO access method, but does not
++ * seem to support I/O ports.
++ *
++ * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
++ * a memory read/write command on the PCI bus. 30 LSBs of address on
++ * the bus are taken from memory read/write request and 2 MSBs are
++ * determined by PCI unit configuration.
++ *
++ * To work with the configuration space instead of memory is necessary set
++ * the CFG_SEL bit in the PCI_MISC_CONFIG register.
++ *
++ * Devices on the bus can perform DMA requests via chip BAR1. PCI host
++ * controller BARs are programmend as if an external device is programmed.
++ * Which means that during configuration, IDSEL pin of the chip should be
++ * asserted.
++ *
++ * We know (and support) only one board that uses the PCI interface -
++ * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
++ * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
++ * and IDSEL pin of AR2315 is connected to AD[16] line.
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/platform_device.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/delay.h>
++#include <linux/bitops.h>
++#include <linux/irq.h>
++#include <linux/irqdomain.h>
++#include <linux/io.h>
++#include <asm/paccess.h>
++
++/*
++ * PCI Bus Interface Registers
++ */
++#define AR2315_PCI_1MS_REG 0x0008
++
++#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
++
++#define AR2315_PCI_MISC_CONFIG 0x000c
++
++#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
++#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
++#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
++#define AR2315_PCIMISC_RST_MODE 0x00000030
++#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
++#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
++#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
++#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
++#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
++#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
++#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
++#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
++ * disable */
++
++#define AR2315_PCI_OUT_TSTAMP 0x0010
++
++#define AR2315_PCI_UNCACHE_CFG 0x0014
++
++#define AR2315_PCI_IN_EN 0x0100
++
++#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
++#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
++#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
++#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
++
++#define AR2315_PCI_IN_DIS 0x0104
++
++#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
++#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
++#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
++#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
++
++#define AR2315_PCI_IN_PTR 0x0200
++
++#define AR2315_PCI_OUT_EN 0x0400
++
++#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
++
++#define AR2315_PCI_OUT_DIS 0x0404
++
++#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
++
++#define AR2315_PCI_OUT_PTR 0x0408
++
++/* PCI interrupt status (write one to clear) */
++#define AR2315_PCI_ISR 0x0500
++
++#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
++#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
++#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
++#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
++#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
++#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
++#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
++#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
++#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
++#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
++#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
++#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
++
++/* PCI interrupt mask */
++#define AR2315_PCI_IMR 0x0504
++
++/* Global PCI interrupt enable */
++#define AR2315_PCI_IER 0x0508
++
++#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
++#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
++
++#define AR2315_PCI_HOST_IN_EN 0x0800
++#define AR2315_PCI_HOST_IN_DIS 0x0804
++#define AR2315_PCI_HOST_IN_PTR 0x0810
++#define AR2315_PCI_HOST_OUT_EN 0x0900
++#define AR2315_PCI_HOST_OUT_DIS 0x0904
++#define AR2315_PCI_HOST_OUT_PTR 0x0908
++
++/*
++ * PCI interrupts, which share IP5
++ * Keep ordered according to AR2315_PCI_INT_XXX bits
++ */
++#define AR2315_PCI_IRQ_EXT 25
++#define AR2315_PCI_IRQ_ABORT 26
++#define AR2315_PCI_IRQ_COUNT 27
++
++/* Arbitrary size of memory region to access the configuration space */
++#define AR2315_PCI_CFG_SIZE 0x00100000
++
++#define AR2315_PCI_HOST_SLOT 3
++#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
++
++/* ??? access BAR */
++#define AR2315_PCI_HOST_MBAR0 0x10000000
++/* RAM access BAR */
++#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
++/* ??? access BAR */
++#define AR2315_PCI_HOST_MBAR2 0x30000000
++
++struct ar2315_pci_ctrl {
++ void __iomem *cfg_mem;
++ void __iomem *mmr_mem;
++ unsigned irq;
++ unsigned irq_ext;
++ struct irq_domain *domain;
++ struct pci_controller pci_ctrl;
++ struct resource mem_res;
++ struct resource io_res;
++};
++
++static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
++{
++ struct pci_controller *hose = bus->sysdata;
++
++ return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
++}
++
++static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
++{
++ return __raw_readl(apc->mmr_mem + reg);
++}
++
++static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
++ u32 val)
++{
++ __raw_writel(val, apc->mmr_mem + reg);
++}
++
++static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
++ u32 mask, u32 val)
++{
++ u32 ret = ar2315_pci_reg_read(apc, reg);
++
++ ret &= ~mask;
++ ret |= val;
++ ar2315_pci_reg_write(apc, reg, ret);
++}
++
++static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
++ int where, int size, u32 *ptr, bool write)
++{
++ int func = PCI_FUNC(devfn);
++ int dev = PCI_SLOT(devfn);
++ u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
++ u32 mask = 0xffffffff >> 8 * (4 - size);
++ u32 sh = (where & 3) * 8;
++ u32 value, isr;
++
++ /* Prevent access past the remapped area */
++ if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ /* Clear pending errors */
++ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
++ /* Select Configuration access */
++ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
++ AR2315_PCIMISC_CFG_SEL);
++
++ mb(); /* PCI must see space change before we begin */
++
++ value = __raw_readl(apc->cfg_mem + addr);
++
++ isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
++
++ if (isr & AR2315_PCI_INT_ABORT)
++ goto exit_err;
++
++ if (write) {
++ value = (value & ~(mask << sh)) | *ptr << sh;
++ __raw_writel(value, apc->cfg_mem + addr);
++ isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
++ if (isr & AR2315_PCI_INT_ABORT)
++ goto exit_err;
++ } else {
++ *ptr = (value >> sh) & mask;
++ }
++
++ goto exit;
++
++exit_err:
++ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
++ if (!write)
++ *ptr = 0xffffffff;
++
++exit:
++ /* Select Memory access */
++ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
++ 0);
++
++ return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
++ PCIBIOS_SUCCESSFUL;
++}
++
++static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
++ unsigned devfn, int where, u32 *val)
++{
++ return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
++ false);
++}
++
++static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
++ unsigned devfn, int where, u32 val)
++{
++ return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
++ true);
++}
++
++static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
++ int size, u32 *value)
++{
++ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
++
++ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
++}
++
++static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
++ int size, u32 value)
++{
++ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
++
++ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
++}
++
++static struct pci_ops ar2315_pci_ops = {
++ .read = ar2315_pci_cfg_read,
++ .write = ar2315_pci_cfg_write,
++};
++
++static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
++{
++ unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
++ int res;
++ u32 id;
++
++ res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
++ if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
++ return -ENODEV;
++
++ /* Program MBARs */
++ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
++ AR2315_PCI_HOST_MBAR0);
++ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
++ AR2315_PCI_HOST_MBAR1);
++ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
++ AR2315_PCI_HOST_MBAR2);
++
++ /* Run */
++ ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
++ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
++ PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
++
++ return 0;
++}
++
++static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
++{
++ struct ar2315_pci_ctrl *apc = irq_get_handler_data(irq);
++ u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
++ ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
++ unsigned pci_irq = 0;
++
++ if (pending)
++ pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
++
++ if (pci_irq)
++ generic_handle_irq(pci_irq);
++ else
++ spurious_interrupt();
++}
++
++static void ar2315_pci_irq_mask(struct irq_data *d)
++{
++ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
++
++ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
++}
++
++static void ar2315_pci_irq_mask_ack(struct irq_data *d)
++{
++ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
++ u32 m = BIT(d->hwirq);
++
++ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
++ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
++}
++
++static void ar2315_pci_irq_unmask(struct irq_data *d)
++{
++ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
++
++ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
++}
++
++static struct irq_chip ar2315_pci_irq_chip = {
++ .name = "AR2315-PCI",
++ .irq_mask = ar2315_pci_irq_mask,
++ .irq_mask_ack = ar2315_pci_irq_mask_ack,
++ .irq_unmask = ar2315_pci_irq_unmask,
++};
++
++static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
++ irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
++ irq_set_chip_data(irq, d->host_data);
++ return 0;
++}
++
++static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
++ .map = ar2315_pci_irq_map,
++};
++
++static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
++{
++ ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
++ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
++ AR2315_PCI_INT_EXT), 0);
++
++ apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
++
++ irq_set_chained_handler(apc->irq, ar2315_pci_irq_handler);
++ irq_set_handler_data(apc->irq, apc);
++
++ /* Clear any pending Abort or external Interrupts
++ * and enable interrupt processing */
++ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
++ AR2315_PCI_INT_EXT);
++ ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
++}
++
++static int ar2315_pci_probe(struct platform_device *pdev)
++{
++ struct ar2315_pci_ctrl *apc;
++ struct device *dev = &pdev->dev;
++ struct resource *res;
++ int irq, err;
++
++ apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
++ if (!apc)
++ return -ENOMEM;
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return -EINVAL;
++ apc->irq = irq;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
++ "ar2315-pci-ctrl");
++ apc->mmr_mem = devm_ioremap_resource(dev, res);
++ if (IS_ERR(apc->mmr_mem))
++ return PTR_ERR(apc->mmr_mem);
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
++ "ar2315-pci-ext");
++ if (!res)
++ return -EINVAL;
++
++ apc->mem_res.name = "AR2315 PCI mem space";
++ apc->mem_res.parent = res;
++ apc->mem_res.start = res->start;
++ apc->mem_res.end = res->end;
++ apc->mem_res.flags = IORESOURCE_MEM;
++
++ /* Remap PCI config space */
++ apc->cfg_mem = devm_ioremap_nocache(dev, res->start,
++ AR2315_PCI_CFG_SIZE);
++ if (!apc->cfg_mem) {
++ dev_err(dev, "failed to remap PCI config space\n");
++ return -ENOMEM;
++ }
++
++ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
++ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
++ AR2315_PCIMISC_RST_MODE,
++ AR2315_PCIRST_LOW);
++ msleep(100);
++
++ /* Bring the PCI out of reset */
++ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
++ AR2315_PCIMISC_RST_MODE,
++ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
++
++ ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
++ 0x1E | /* 1GB uncached */
++ (1 << 5) | /* Enable uncached */
++ (0x2 << 30) /* Base: 0x80000000 */);
++ ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
++
++ msleep(500);
++
++ err = ar2315_pci_host_setup(apc);
++ if (err)
++ return err;
++
++ apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
++ &ar2315_pci_irq_domain_ops, apc);
++ if (!apc->domain) {
++ dev_err(dev, "failed to add IRQ domain\n");
++ return -ENOMEM;
++ }
++
++ ar2315_pci_irq_init(apc);
++
++ /* PCI controller does not support I/O ports */
++ apc->io_res.name = "AR2315 IO space";
++ apc->io_res.start = 0;
++ apc->io_res.end = 0;
++ apc->io_res.flags = IORESOURCE_IO,
++
++ apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
++ apc->pci_ctrl.mem_resource = &apc->mem_res,
++ apc->pci_ctrl.io_resource = &apc->io_res,
++
++ register_pci_controller(&apc->pci_ctrl);
++
++ dev_info(dev, "register PCI controller\n");
++
++ return 0;
++}
++
++static struct platform_driver ar2315_pci_driver = {
++ .probe = ar2315_pci_probe,
++ .driver = {
++ .name = "ar2315-pci",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init ar2315_pci_init(void)
++{
++ return platform_driver_register(&ar2315_pci_driver);
++}
++arch_initcall(ar2315_pci_init);
++
++int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
++
++ return slot ? 0 : apc->irq_ext;
++}
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++ return 0;
++}
+--- a/arch/mips/ath25/Kconfig
++++ b/arch/mips/ath25/Kconfig
+@@ -7,3 +7,10 @@ config SOC_AR2315
+ bool "Atheros AR2315+ SoC support"
+ depends on ATH25
+ default y
++
++config PCI_AR2315
++ bool "Atheros AR2315 PCI controller support"
++ depends on SOC_AR2315
++ select HW_HAS_PCI
++ select PCI
++ default y
+--- a/arch/mips/ath25/ar2315.c
++++ b/arch/mips/ath25/ar2315.c
+@@ -134,6 +134,10 @@ static void ar2315_irq_dispatch(void)
+
+ if (pending & CAUSEF_IP3)
+ do_IRQ(AR2315_IRQ_WLAN0);
++#ifdef CONFIG_PCI_AR2315
++ else if (pending & CAUSEF_IP5)
++ do_IRQ(AR2315_IRQ_LCBUS_PCI);
++#endif
+ else if (pending & CAUSEF_IP2)
+ do_IRQ(AR2315_IRQ_MISC);
+ else if (pending & CAUSEF_IP7)
+@@ -299,10 +303,62 @@ void __init ar2315_plat_mem_setup(void)
+ _machine_restart = ar2315_restart;
+ }
+
++#ifdef CONFIG_PCI_AR2315
++static struct resource ar2315_pci_res[] = {
++ {
++ .name = "ar2315-pci-ctrl",
++ .flags = IORESOURCE_MEM,
++ .start = AR2315_PCI_BASE,
++ .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
++ },
++ {
++ .name = "ar2315-pci-ext",
++ .flags = IORESOURCE_MEM,
++ .start = AR2315_PCI_EXT_BASE,
++ .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
++ },
++ {
++ .name = "ar2315-pci",
++ .flags = IORESOURCE_IRQ,
++ .start = AR2315_IRQ_LCBUS_PCI,
++ .end = AR2315_IRQ_LCBUS_PCI,
++ },
++};
++#endif
++
+ void __init ar2315_arch_init(void)
+ {
+ unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
+ AR2315_MISC_IRQ_UART0);
+
+ ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
++
++#ifdef CONFIG_PCI_AR2315
++ if (ath25_soc == ATH25_SOC_AR2315) {
++ /* Reset PCI DMA logic */
++ ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
++ msleep(20);
++ ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
++ msleep(20);
++
++ /* Configure endians */
++ ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
++ AR2315_CONFIG_PCIAHB_BRIDGE);
++
++ /* Configure as PCI host with DMA */
++ ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
++ (AR2315_PCICLK_IN_FREQ_DIV_6 <<
++ AR2315_PCICLK_DIV_S));
++ ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
++ ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
++ AR2315_IF_MASK, AR2315_IF_PCI |
++ AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
++ (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
++ AR2315_IF_PCI_CLK_SHIFT));
++
++ platform_device_register_simple("ar2315-pci", -1,
++ ar2315_pci_res,
++ ARRAY_SIZE(ar2315_pci_res));
++ }
++#endif
+ }
--- /dev/null
+--- a/arch/mips/ath25/Kconfig
++++ b/arch/mips/ath25/Kconfig
+@@ -1,6 +1,7 @@
+ config SOC_AR5312
+ bool "Atheros AR5312/AR2312+ SoC support"
+ depends on ATH25
++ select GPIO_AR5312
+ default y
+
+ config SOC_AR2315
+--- a/arch/mips/ath25/ar5312.c
++++ b/arch/mips/ath25/ar5312.c
+@@ -22,6 +22,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/mtd/physmap.h>
+ #include <linux/reboot.h>
++#include <linux/gpio.h>
+ #include <asm/bootinfo.h>
+ #include <asm/reboot.h>
+ #include <asm/time.h>
+@@ -180,6 +181,22 @@ static struct platform_device ar5312_phy
+ .num_resources = 1,
+ };
+
++static struct resource ar5312_gpio_res[] = {
++ {
++ .name = "ar5312-gpio",
++ .flags = IORESOURCE_MEM,
++ .start = AR5312_GPIO_BASE,
++ .end = AR5312_GPIO_BASE + AR5312_GPIO_SIZE - 1,
++ },
++};
++
++static struct platform_device ar5312_gpio = {
++ .name = "ar5312-gpio",
++ .id = -1,
++ .resource = ar5312_gpio_res,
++ .num_resources = ARRAY_SIZE(ar5312_gpio_res),
++};
++
+ static void __init ar5312_flash_init(void)
+ {
+ void __iomem *flashctl_base;
+@@ -247,6 +264,8 @@ void __init ar5312_init_devices(void)
+
+ platform_device_register(&ar5312_physmap_flash);
+
++ platform_device_register(&ar5312_gpio);
++
+ switch (ath25_soc) {
+ case ATH25_SOC_AR5312:
+ if (!ath25_board.radio)
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -112,6 +112,13 @@ config GPIO_MAX730X
+
+ comment "Memory mapped GPIO drivers:"
+
++config GPIO_AR5312
++ bool "AR5312 SoC GPIO support"
++ default y if SOC_AR5312
++ depends on SOC_AR5312
++ help
++ Say yes here to enable GPIO support for Atheros AR5312/AR2312+ SoCs.
++
+ config GPIO_CLPS711X
+ tristate "CLPS711X GPIO support"
+ depends on ARCH_CLPS711X || COMPILE_TEST
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
+ obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
+ obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
+ obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
++obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
+ obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
+ obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
+ obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
+--- /dev/null
++++ b/drivers/gpio/gpio-ar5312.c
+@@ -0,0 +1,121 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++
++#define DRIVER_NAME "ar5312-gpio"
++
++#define AR5312_GPIO_DO 0x00 /* output register */
++#define AR5312_GPIO_DI 0x04 /* intput register */
++#define AR5312_GPIO_CR 0x08 /* control register */
++
++#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
++#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
++#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
++#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
++#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
++
++#define AR5312_GPIO_NUM 8
++
++static void __iomem *ar5312_mem;
++
++static inline u32 ar5312_gpio_reg_read(unsigned reg)
++{
++ return __raw_readl(ar5312_mem + reg);
++}
++
++static inline void ar5312_gpio_reg_write(unsigned reg, u32 val)
++{
++ __raw_writel(val, ar5312_mem + reg);
++}
++
++static inline void ar5312_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
++{
++ ar5312_gpio_reg_write(reg, (ar5312_gpio_reg_read(reg) & ~mask) | val);
++}
++
++static int ar5312_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
++{
++ return (ar5312_gpio_reg_read(AR5312_GPIO_DI) >> gpio) & 1;
++}
++
++static void ar5312_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
++{
++ u32 reg = ar5312_gpio_reg_read(AR5312_GPIO_DO);
++
++ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
++ ar5312_gpio_reg_write(AR5312_GPIO_DO, reg);
++}
++
++static int ar5312_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
++{
++ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 0, 1 << gpio);
++ return 0;
++}
++
++static int ar5312_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
++{
++ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 1 << gpio, 0);
++ ar5312_gpio_set_val(chip, gpio, val);
++ return 0;
++}
++
++static struct gpio_chip ar5312_gpio_chip = {
++ .label = DRIVER_NAME,
++ .direction_input = ar5312_gpio_dir_in,
++ .direction_output = ar5312_gpio_dir_out,
++ .set = ar5312_gpio_set_val,
++ .get = ar5312_gpio_get_val,
++ .base = 0,
++ .ngpio = AR5312_GPIO_NUM,
++};
++
++static int ar5312_gpio_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct resource *res;
++ int ret;
++
++ if (ar5312_mem)
++ return -EBUSY;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ ar5312_mem = devm_ioremap_resource(dev, res);
++ if (IS_ERR(ar5312_mem))
++ return PTR_ERR(ar5312_mem);
++
++ ar5312_gpio_chip.dev = dev;
++ ret = gpiochip_add(&ar5312_gpio_chip);
++ if (ret) {
++ dev_err(dev, "failed to add gpiochip\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static struct platform_driver ar5312_gpio_driver = {
++ .probe = ar5312_gpio_probe,
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ }
++};
++
++static int __init ar5312_gpio_init(void)
++{
++ return platform_driver_register(&ar5312_gpio_driver);
++}
++subsys_initcall(ar5312_gpio_init);
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -107,6 +107,7 @@ config ATH25
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_HAS_EARLY_PRINTK
++ select ARCH_REQUIRE_GPIOLIB
+ help
+ Support for Atheros AR231x and Atheros AR531x based boards
+
--- /dev/null
+--- a/arch/mips/ath25/Kconfig
++++ b/arch/mips/ath25/Kconfig
+@@ -7,6 +7,7 @@ config SOC_AR5312
+ config SOC_AR2315
+ bool "Atheros AR2315+ SoC support"
+ depends on ATH25
++ select GPIO_AR2315
+ default y
+
+ config PCI_AR2315
+--- a/arch/mips/ath25/ar2315.c
++++ b/arch/mips/ath25/ar2315.c
+@@ -21,6 +21,8 @@
+ #include <linux/interrupt.h>
+ #include <linux/platform_device.h>
+ #include <linux/reboot.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
+ #include <asm/bootinfo.h>
+ #include <asm/reboot.h>
+ #include <asm/time.h>
+@@ -167,11 +169,42 @@ void __init ar2315_arch_init_irq(void)
+ ar2315_misc_irq_domain = domain;
+ }
+
++static struct resource ar2315_gpio_res[] = {
++ {
++ .name = "ar2315-gpio",
++ .flags = IORESOURCE_MEM,
++ .start = AR2315_RST_BASE + AR2315_GPIO,
++ .end = AR2315_RST_BASE + AR2315_GPIO + 0x10 - 1,
++ },
++ {
++ .name = "ar2315-gpio",
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "ar2315-gpio-irq-base",
++ .flags = IORESOURCE_IRQ,
++ .start = AR231X_GPIO_IRQ_BASE,
++ .end = AR231X_GPIO_IRQ_BASE,
++ }
++};
++
++static struct platform_device ar2315_gpio = {
++ .id = -1,
++ .name = "ar2315-gpio",
++ .resource = ar2315_gpio_res,
++ .num_resources = ARRAY_SIZE(ar2315_gpio_res)
++};
++
+ void __init ar2315_init_devices(void)
+ {
+ /* Find board configuration */
+ ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
+
++ ar2315_gpio_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
++ AR2315_MISC_IRQ_GPIO);
++ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
++ platform_device_register(&ar2315_gpio);
++
+ ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
+ }
+
+@@ -187,8 +220,8 @@ static void ar2315_restart(char *command
+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
+ * a workaround. Give it some time to attempt a gpio based hardware
+ * reset (atheros reference design workaround) */
+-
+- /* TODO: implement the GPIO reset workaround */
++ gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
++ mdelay(100);
+
+ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
+ * workaround. Attempt to jump to the mips reset location -
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -112,6 +112,13 @@ config GPIO_MAX730X
+
+ comment "Memory mapped GPIO drivers:"
+
++config GPIO_AR2315
++ bool "AR2315 SoC GPIO support"
++ default y if SOC_AR2315
++ depends on SOC_AR2315
++ help
++ Say yes here to enable GPIO support for Atheros AR2315+ SoCs.
++
+ config GPIO_AR5312
+ bool "AR5312 SoC GPIO support"
+ default y if SOC_AR5312
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
+ obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
+ obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
+ obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
++obj-$(CONFIG_GPIO_AR2315) += gpio-ar2315.o
+ obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
+ obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
+ obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
+--- /dev/null
++++ b/drivers/gpio/gpio-ar2315.c
+@@ -0,0 +1,233 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
++ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/irq.h>
++
++#define DRIVER_NAME "ar2315-gpio"
++
++#define AR2315_GPIO_DI 0x0000
++#define AR2315_GPIO_DO 0x0008
++#define AR2315_GPIO_DIR 0x0010
++#define AR2315_GPIO_INT 0x0018
++
++#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
++#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
++#define AR2315_GPIO_DIR_I(x) (0) /* input */
++
++#define AR2315_GPIO_INT_NUM_M 0x3F /* mask for GPIO num */
++#define AR2315_GPIO_INT_TRIG(x) ((x) << 6) /* interrupt trigger */
++#define AR2315_GPIO_INT_TRIG_M (0x3 << 6) /* mask for int trig */
++
++#define AR2315_GPIO_INT_TRIG_OFF 0 /* Triggerring off */
++#define AR2315_GPIO_INT_TRIG_LOW 1 /* Low Level Triggered */
++#define AR2315_GPIO_INT_TRIG_HIGH 2 /* High Level Triggered */
++#define AR2315_GPIO_INT_TRIG_EDGE 3 /* Edge Triggered */
++
++#define AR2315_GPIO_NUM 22
++
++static u32 ar2315_gpio_intmask;
++static u32 ar2315_gpio_intval;
++static unsigned ar2315_gpio_irq_base;
++static void __iomem *ar2315_mem;
++
++static inline u32 ar2315_gpio_reg_read(unsigned reg)
++{
++ return __raw_readl(ar2315_mem + reg);
++}
++
++static inline void ar2315_gpio_reg_write(unsigned reg, u32 val)
++{
++ __raw_writel(val, ar2315_mem + reg);
++}
++
++static inline void ar2315_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
++{
++ ar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val);
++}
++
++static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
++{
++ u32 pend;
++ int bit = -1;
++
++ /* only do one gpio interrupt at a time */
++ pend = ar2315_gpio_reg_read(AR2315_GPIO_DI);
++ pend ^= ar2315_gpio_intval;
++ pend &= ar2315_gpio_intmask;
++
++ if (pend) {
++ bit = fls(pend) - 1;
++ pend &= ~(1 << bit);
++ ar2315_gpio_intval ^= (1 << bit);
++ }
++
++ /* Enable interrupt with edge detection */
++ if ((ar2315_gpio_reg_read(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
++ AR2315_GPIO_DIR_I(bit))
++ return;
++
++ if (bit >= 0)
++ generic_handle_irq(ar2315_gpio_irq_base + bit);
++}
++
++static void ar2315_gpio_int_setup(unsigned gpio, int trig)
++{
++ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_INT);
++
++ reg &= ~(AR2315_GPIO_INT_NUM_M | AR2315_GPIO_INT_TRIG_M);
++ reg |= gpio | AR2315_GPIO_INT_TRIG(trig);
++ ar2315_gpio_reg_write(AR2315_GPIO_INT, reg);
++}
++
++static void ar2315_gpio_irq_unmask(struct irq_data *d)
++{
++ unsigned gpio = d->irq - ar2315_gpio_irq_base;
++ u32 dir = ar2315_gpio_reg_read(AR2315_GPIO_DIR);
++
++ /* Enable interrupt with edge detection */
++ if ((dir & AR2315_GPIO_DIR_M(gpio)) != AR2315_GPIO_DIR_I(gpio))
++ return;
++
++ ar2315_gpio_intmask |= (1 << gpio);
++ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_EDGE);
++}
++
++static void ar2315_gpio_irq_mask(struct irq_data *d)
++{
++ unsigned gpio = d->irq - ar2315_gpio_irq_base;
++
++ /* Disable interrupt */
++ ar2315_gpio_intmask &= ~(1 << gpio);
++ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_OFF);
++}
++
++static struct irq_chip ar2315_gpio_irq_chip = {
++ .name = DRIVER_NAME,
++ .irq_unmask = ar2315_gpio_irq_unmask,
++ .irq_mask = ar2315_gpio_irq_mask,
++};
++
++static void ar2315_gpio_irq_init(unsigned irq)
++{
++ unsigned i;
++
++ ar2315_gpio_intval = ar2315_gpio_reg_read(AR2315_GPIO_DI);
++ for (i = 0; i < AR2315_GPIO_NUM; i++) {
++ unsigned _irq = ar2315_gpio_irq_base + i;
++
++ irq_set_chip_and_handler(_irq, &ar2315_gpio_irq_chip,
++ handle_level_irq);
++ }
++ irq_set_chained_handler(irq, ar2315_gpio_irq_handler);
++}
++
++static int ar2315_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
++{
++ return (ar2315_gpio_reg_read(AR2315_GPIO_DI) >> gpio) & 1;
++}
++
++static void ar2315_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
++{
++ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_DO);
++
++ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
++ ar2315_gpio_reg_write(AR2315_GPIO_DO, reg);
++}
++
++static int ar2315_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
++{
++ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 1 << gpio, 0);
++ return 0;
++}
++
++static int ar2315_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
++{
++ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 0, 1 << gpio);
++ ar2315_gpio_set_val(chip, gpio, val);
++ return 0;
++}
++
++static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
++{
++ return ar2315_gpio_irq_base + gpio;
++}
++
++static struct gpio_chip ar2315_gpio_chip = {
++ .label = DRIVER_NAME,
++ .direction_input = ar2315_gpio_dir_in,
++ .direction_output = ar2315_gpio_dir_out,
++ .set = ar2315_gpio_set_val,
++ .get = ar2315_gpio_get_val,
++ .to_irq = ar2315_gpio_to_irq,
++ .base = 0,
++ .ngpio = AR2315_GPIO_NUM,
++};
++
++static int ar2315_gpio_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct resource *res;
++ unsigned irq;
++ int ret;
++
++ if (ar2315_mem)
++ return -EBUSY;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
++ "ar2315-gpio-irq-base");
++ if (!res) {
++ dev_err(dev, "not found GPIO IRQ base\n");
++ return -ENXIO;
++ }
++ ar2315_gpio_irq_base = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, DRIVER_NAME);
++ if (!res) {
++ dev_err(dev, "not found IRQ number\n");
++ return -ENXIO;
++ }
++ irq = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, DRIVER_NAME);
++ ar2315_mem = devm_ioremap_resource(dev, res);
++ if (IS_ERR(ar2315_mem))
++ return PTR_ERR(ar2315_mem);
++
++ ar2315_gpio_chip.dev = dev;
++ ret = gpiochip_add(&ar2315_gpio_chip);
++ if (ret) {
++ dev_err(dev, "failed to add gpiochip\n");
++ return ret;
++ }
++
++ ar2315_gpio_irq_init(irq);
++
++ return 0;
++}
++
++static struct platform_driver ar2315_gpio_driver = {
++ .probe = ar2315_gpio_probe,
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ }
++};
++
++static int __init ar2315_gpio_init(void)
++{
++ return platform_driver_register(&ar2315_gpio_driver);
++}
++subsys_initcall(ar2315_gpio_init);
+--- a/arch/mips/ath25/devices.h
++++ b/arch/mips/ath25/devices.h
+@@ -3,6 +3,11 @@
+
+ #include <linux/cpu.h>
+
++#define AR231X_GPIO_IRQ_BASE 0x30
++
++/* GPIO number for AR2315/16 reset issue workaround */
++#define AR2315_RESET_GPIO 5
++
+ #define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
+
+ #define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
+--- a/arch/mips/ath25/ar2315_regs.h
++++ b/arch/mips/ath25/ar2315_regs.h
+@@ -315,6 +315,9 @@
+ #define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
+ #define AR2315_MEM_CFG_BANKADDR_BITS_S 3
+
++/* GPIO MMR base address */
++#define AR2315_GPIO 0x0088
++
+ /*
+ * Local Bus Interface Registers
+ */
--- /dev/null
+--- a/drivers/net/ethernet/atheros/Makefile
++++ b/drivers/net/ethernet/atheros/Makefile
+@@ -7,3 +7,4 @@ obj-$(CONFIG_ATL2) += atlx/
+ obj-$(CONFIG_ATL1E) += atl1e/
+ obj-$(CONFIG_ATL1C) += atl1c/
+ obj-$(CONFIG_ALX) += alx/
++obj-$(CONFIG_NET_AR231X) += ar231x/
+--- a/drivers/net/ethernet/atheros/Kconfig
++++ b/drivers/net/ethernet/atheros/Kconfig
+@@ -5,7 +5,7 @@
+ config NET_VENDOR_ATHEROS
+ bool "Atheros devices"
+ default y
+- depends on PCI
++ depends on (PCI || ATH25)
+ ---help---
+ If you have a network (Ethernet) card belonging to this class, say Y
+ and read the Ethernet-HOWTO, available from
+@@ -80,4 +80,10 @@ config ALX
+ To compile this driver as a module, choose M here. The module
+ will be called alx.
+
++config NET_AR231X
++ tristate "Atheros AR231X built-in Ethernet support"
++ depends on ATH25
++ help
++ Support for the AR231x/531x ethernet controller
++
+ endif # NET_VENDOR_ATHEROS
+--- /dev/null
++++ b/drivers/net/ethernet/atheros/ar231x/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_NET_AR231X) += ar231x.o
+--- /dev/null
++++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
+@@ -0,0 +1,1206 @@
++/*
++ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
++ *
++ * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++ *
++ * Thanks to Atheros for providing hardware and documentation
++ * enabling me to write this driver.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * Additional credits:
++ * This code is taken from John Taylor's Sibyte driver and then
++ * modified for the AR2313.
++ */
++
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/errno.h>
++#include <linux/ioport.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/interrupt.h>
++#include <linux/skbuff.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/mm.h>
++#include <linux/mii.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++
++#define AR2313_MTU 1692
++#define AR2313_PRIOS 1
++#define AR2313_QUEUES (2*AR2313_PRIOS)
++#define AR2313_DESCR_ENTRIES 64
++
++#ifndef min
++#define min(a, b) (((a) < (b)) ? (a) : (b))
++#endif
++
++#ifndef SMP_CACHE_BYTES
++#define SMP_CACHE_BYTES L1_CACHE_BYTES
++#endif
++
++#define AR2313_MBOX_SET_BIT 0x8
++
++#include "ar231x.h"
++
++/**
++ * New interrupt handler strategy:
++ *
++ * An old interrupt handler worked using the traditional method of
++ * replacing an skbuff with a new one when a packet arrives. However
++ * the rx rings do not need to contain a static number of buffer
++ * descriptors, thus it makes sense to move the memory allocation out
++ * of the main interrupt handler and do it in a bottom half handler
++ * and only allocate new buffers when the number of buffers in the
++ * ring is below a certain threshold. In order to avoid starving the
++ * NIC under heavy load it is however necessary to force allocation
++ * when hitting a minimum threshold. The strategy for alloction is as
++ * follows:
++ *
++ * RX_LOW_BUF_THRES - allocate buffers in the bottom half
++ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
++ * the buffers in the interrupt handler
++ * RX_RING_THRES - maximum number of buffers in the rx ring
++ *
++ * One advantagous side effect of this allocation approach is that the
++ * entire rx processing can be done without holding any spin lock
++ * since the rx rings and registers are totally independent of the tx
++ * ring and its registers. This of course includes the kmalloc's of
++ * new skb's. Thus start_xmit can run in parallel with rx processing
++ * and the memory allocation on SMP systems.
++ *
++ * Note that running the skb reallocation in a bottom half opens up
++ * another can of races which needs to be handled properly. In
++ * particular it can happen that the interrupt handler tries to run
++ * the reallocation while the bottom half is either running on another
++ * CPU or was interrupted on the same CPU. To get around this the
++ * driver uses bitops to prevent the reallocation routines from being
++ * reentered.
++ *
++ * TX handling can also be done without holding any spin lock, wheee
++ * this is fun! since tx_csm is only written to by the interrupt
++ * handler.
++ */
++
++/**
++ * Threshold values for RX buffer allocation - the low water marks for
++ * when to start refilling the rings are set to 75% of the ring
++ * sizes. It seems to make sense to refill the rings entirely from the
++ * intrrupt handler once it gets below the panic threshold, that way
++ * we don't risk that the refilling is moved to another CPU when the
++ * one running the interrupt handler just got the slab code hot in its
++ * cache.
++ */
++#define RX_RING_SIZE AR2313_DESCR_ENTRIES
++#define RX_PANIC_THRES (RX_RING_SIZE/4)
++#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
++#define CRC_LEN 4
++#define RX_OFFSET 2
++
++#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
++#define VLAN_HDR 4
++#else
++#define VLAN_HDR 0
++#endif
++
++#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
++ RX_OFFSET)
++
++#ifdef MODULE
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
++MODULE_DESCRIPTION("AR231x Ethernet driver");
++#endif
++
++#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
++
++/* prototypes */
++static void ar231x_halt(struct net_device *dev);
++static void rx_tasklet_func(unsigned long data);
++static void rx_tasklet_cleanup(struct net_device *dev);
++static void ar231x_multicast_list(struct net_device *dev);
++static void ar231x_tx_timeout(struct net_device *dev);
++
++static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
++static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
++ u16 value);
++static int ar231x_mdiobus_reset(struct mii_bus *bus);
++static int ar231x_mdiobus_probe(struct net_device *dev);
++static void ar231x_adjust_link(struct net_device *dev);
++
++#ifndef ERR
++#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
++#endif
++
++#ifdef CONFIG_NET_POLL_CONTROLLER
++static void
++ar231x_netpoll(struct net_device *dev)
++{
++ unsigned long flags;
++
++ local_irq_save(flags);
++ ar231x_interrupt(dev->irq, dev);
++ local_irq_restore(flags);
++}
++#endif
++
++static const struct net_device_ops ar231x_ops = {
++ .ndo_open = ar231x_open,
++ .ndo_stop = ar231x_close,
++ .ndo_start_xmit = ar231x_start_xmit,
++ .ndo_set_rx_mode = ar231x_multicast_list,
++ .ndo_do_ioctl = ar231x_ioctl,
++ .ndo_change_mtu = eth_change_mtu,
++ .ndo_validate_addr = eth_validate_addr,
++ .ndo_set_mac_address = eth_mac_addr,
++ .ndo_tx_timeout = ar231x_tx_timeout,
++#ifdef CONFIG_NET_POLL_CONTROLLER
++ .ndo_poll_controller = ar231x_netpoll,
++#endif
++};
++
++static int ar231x_probe(struct platform_device *pdev)
++{
++ struct net_device *dev;
++ struct ar231x_private *sp;
++ struct resource *res;
++ unsigned long ar_eth_base;
++ char buf[64];
++
++ dev = alloc_etherdev(sizeof(struct ar231x_private));
++
++ if (dev == NULL) {
++ printk(KERN_ERR
++ "ar231x: Unable to allocate net_device structure!\n");
++ return -ENOMEM;
++ }
++
++ platform_set_drvdata(pdev, dev);
++
++ sp = netdev_priv(dev);
++ sp->dev = dev;
++ sp->cfg = pdev->dev.platform_data;
++
++ sprintf(buf, "eth%d_membase", pdev->id);
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
++ if (!res)
++ return -ENODEV;
++
++ sp->link = 0;
++ ar_eth_base = res->start;
++
++ sprintf(buf, "eth%d_irq", pdev->id);
++ dev->irq = platform_get_irq_byname(pdev, buf);
++
++ spin_lock_init(&sp->lock);
++
++ dev->features |= NETIF_F_HIGHDMA;
++ dev->netdev_ops = &ar231x_ops;
++
++ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long)dev);
++ tasklet_disable(&sp->rx_tasklet);
++
++ sp->eth_regs = ioremap_nocache(ar_eth_base, sizeof(*sp->eth_regs));
++ if (!sp->eth_regs) {
++ printk("Can't remap eth registers\n");
++ return -ENXIO;
++ }
++
++ /**
++ * When there's only one MAC, PHY regs are typically on ENET0,
++ * even though the MAC might be on ENET1.
++ * So remap PHY regs separately.
++ */
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth0_mii");
++ if (!res) {
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
++ "eth1_mii");
++ if (!res)
++ return -ENODEV;
++ }
++ sp->phy_regs = ioremap_nocache(res->start, resource_size(res));
++ if (!sp->phy_regs) {
++ printk("Can't remap phy registers\n");
++ return -ENXIO;
++ }
++
++ sp->dma_regs = ioremap_nocache(ar_eth_base + 0x1000,
++ sizeof(*sp->dma_regs));
++ if (!sp->dma_regs) {
++ printk("Can't remap DMA registers\n");
++ return -ENXIO;
++ }
++ dev->base_addr = ar_eth_base + 0x1000;
++
++ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
++ sp->name[sizeof(sp->name) - 1] = '\0';
++ memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
++
++ if (ar231x_init(dev)) {
++ /* ar231x_init() calls ar231x_init_cleanup() on error */
++ kfree(dev);
++ return -ENODEV;
++ }
++
++ if (register_netdev(dev)) {
++ printk("%s: register_netdev failed\n", __func__);
++ return -1;
++ }
++
++ printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
++ dev->irq);
++
++ sp->mii_bus = mdiobus_alloc();
++ if (sp->mii_bus == NULL)
++ return -1;
++
++ sp->mii_bus->priv = dev;
++ sp->mii_bus->read = ar231x_mdiobus_read;
++ sp->mii_bus->write = ar231x_mdiobus_write;
++ sp->mii_bus->reset = ar231x_mdiobus_reset;
++ sp->mii_bus->name = "ar231x_eth_mii";
++ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
++ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
++ *sp->mii_bus->irq = PHY_POLL;
++
++ mdiobus_register(sp->mii_bus);
++
++ if (ar231x_mdiobus_probe(dev) != 0) {
++ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
++ rx_tasklet_cleanup(dev);
++ ar231x_init_cleanup(dev);
++ unregister_netdev(dev);
++ kfree(dev);
++ return -ENODEV;
++ }
++
++ /* start link poll timer */
++ ar231x_setup_timer(dev);
++
++ return 0;
++}
++
++static void ar231x_multicast_list(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ unsigned int filter;
++
++ filter = sp->eth_regs->mac_control;
++
++ if (dev->flags & IFF_PROMISC)
++ filter |= MAC_CONTROL_PR;
++ else
++ filter &= ~MAC_CONTROL_PR;
++ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
++ filter |= MAC_CONTROL_PM;
++ else
++ filter &= ~MAC_CONTROL_PM;
++
++ sp->eth_regs->mac_control = filter;
++}
++
++static void rx_tasklet_cleanup(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++
++ /**
++ * Tasklet may be scheduled. Need to get it removed from the list
++ * since we're about to free the struct.
++ */
++
++ sp->unloading = 1;
++ tasklet_enable(&sp->rx_tasklet);
++ tasklet_kill(&sp->rx_tasklet);
++}
++
++static int ar231x_remove(struct platform_device *pdev)
++{
++ struct net_device *dev = platform_get_drvdata(pdev);
++ struct ar231x_private *sp = netdev_priv(dev);
++
++ rx_tasklet_cleanup(dev);
++ ar231x_init_cleanup(dev);
++ unregister_netdev(dev);
++ mdiobus_unregister(sp->mii_bus);
++ mdiobus_free(sp->mii_bus);
++ kfree(dev);
++ return 0;
++}
++
++/**
++ * Restart the AR2313 ethernet controller.
++ */
++static int ar231x_restart(struct net_device *dev)
++{
++ /* disable interrupts */
++ disable_irq(dev->irq);
++
++ /* stop mac */
++ ar231x_halt(dev);
++
++ /* initialize */
++ ar231x_init(dev);
++
++ /* enable interrupts */
++ enable_irq(dev->irq);
++
++ return 0;
++}
++
++static struct platform_driver ar231x_driver = {
++ .driver.name = "ar231x-eth",
++ .probe = ar231x_probe,
++ .remove = ar231x_remove,
++};
++
++module_platform_driver(ar231x_driver);
++
++static void ar231x_free_descriptors(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++
++ if (sp->rx_ring != NULL) {
++ kfree((void *)KSEG0ADDR(sp->rx_ring));
++ sp->rx_ring = NULL;
++ sp->tx_ring = NULL;
++ }
++}
++
++static int ar231x_allocate_descriptors(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ int size;
++ int j;
++ ar231x_descr_t *space;
++
++ if (sp->rx_ring != NULL) {
++ printk("%s: already done.\n", __func__);
++ return 0;
++ }
++
++ size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
++ space = kmalloc(size, GFP_KERNEL);
++ if (space == NULL)
++ return 1;
++
++ /* invalidate caches */
++ dma_cache_inv((unsigned int)space, size);
++
++ /* now convert pointer to KSEG1 */
++ space = (ar231x_descr_t *)KSEG1ADDR(space);
++
++ memset((void *)space, 0, size);
++
++ sp->rx_ring = space;
++ space += AR2313_DESCR_ENTRIES;
++
++ sp->tx_ring = space;
++ space += AR2313_DESCR_ENTRIES;
++
++ /* Initialize the transmit Descriptors */
++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
++ ar231x_descr_t *td = &sp->tx_ring[j];
++
++ td->status = 0;
++ td->devcs = DMA_TX1_CHAINED;
++ td->addr = 0;
++ td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
++ }
++
++ return 0;
++}
++
++/**
++ * Generic cleanup handling data allocated during init. Used when the
++ * module is unloaded or if an error occurs during initialization
++ */
++static void ar231x_init_cleanup(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ struct sk_buff *skb;
++ int j;
++
++ ar231x_free_descriptors(dev);
++
++ if (sp->eth_regs)
++ iounmap((void *)sp->eth_regs);
++ if (sp->dma_regs)
++ iounmap((void *)sp->dma_regs);
++ if (sp->phy_regs)
++ iounmap((void *)sp->phy_regs);
++
++ if (sp->rx_skb) {
++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
++ skb = sp->rx_skb[j];
++ if (skb) {
++ sp->rx_skb[j] = NULL;
++ dev_kfree_skb(skb);
++ }
++ }
++ kfree(sp->rx_skb);
++ sp->rx_skb = NULL;
++ }
++
++ if (sp->tx_skb) {
++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
++ skb = sp->tx_skb[j];
++ if (skb) {
++ sp->tx_skb[j] = NULL;
++ dev_kfree_skb(skb);
++ }
++ }
++ kfree(sp->tx_skb);
++ sp->tx_skb = NULL;
++ }
++}
++
++static int ar231x_setup_timer(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++
++ init_timer(&sp->link_timer);
++
++ sp->link_timer.function = ar231x_link_timer_fn;
++ sp->link_timer.data = (int)dev;
++ sp->link_timer.expires = jiffies + HZ;
++
++ add_timer(&sp->link_timer);
++ return 0;
++}
++
++static void ar231x_link_timer_fn(unsigned long data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ struct ar231x_private *sp = netdev_priv(dev);
++
++ /**
++ * See if the link status changed.
++ * This was needed to make sure we set the PHY to the
++ * autonegotiated value of half or full duplex.
++ */
++ ar231x_check_link(dev);
++
++ /**
++ * Loop faster when we don't have link.
++ * This was needed to speed up the AP bootstrap time.
++ */
++ if (sp->link == 0)
++ mod_timer(&sp->link_timer, jiffies + HZ / 2);
++ else
++ mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
++}
++
++static void ar231x_check_link(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ u16 phy_data;
++
++ phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
++ if (sp->phy_data != phy_data) {
++ if (phy_data & BMSR_LSTATUS) {
++ /**
++ * Link is present, ready link partner ability to
++ * deterine duplexity.
++ */
++ int duplex = 0;
++ u16 reg;
++
++ sp->link = 1;
++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
++ MII_BMCR);
++ if (reg & BMCR_ANENABLE) {
++ /* auto neg enabled */
++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
++ MII_LPA);
++ duplex = reg & (LPA_100FULL | LPA_10FULL) ?
++ 1 : 0;
++ } else {
++ /* no auto neg, just read duplex config */
++ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
++ }
++
++ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
++ dev->name, (duplex) ? "full" : "half");
++
++ if (duplex) {
++ /* full duplex */
++ sp->eth_regs->mac_control =
++ (sp->eth_regs->mac_control |
++ MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
++ } else {
++ /* half duplex */
++ sp->eth_regs->mac_control =
++ (sp->eth_regs->mac_control |
++ MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
++ }
++ } else {
++ /* no link */
++ sp->link = 0;
++ }
++ sp->phy_data = phy_data;
++ }
++}
++
++static int ar231x_reset_reg(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ unsigned int ethsal, ethsah;
++ unsigned int flags;
++
++ sp->cfg->reset_set(sp->cfg->reset_mac);
++ mdelay(10);
++ sp->cfg->reset_clear(sp->cfg->reset_mac);
++ mdelay(10);
++ sp->cfg->reset_set(sp->cfg->reset_phy);
++ mdelay(10);
++ sp->cfg->reset_clear(sp->cfg->reset_phy);
++ mdelay(10);
++
++ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
++ mdelay(10);
++ sp->dma_regs->bus_mode =
++ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
++
++ /* enable interrupts */
++ sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
++ DMA_STATUS_RI | DMA_STATUS_TI |
++ DMA_STATUS_FBE;
++ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
++ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
++ sp->dma_regs->control =
++ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
++
++ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
++ sp->eth_regs->vlan_tag = (0x8100);
++
++ /* Enable Ethernet Interface */
++ flags = (MAC_CONTROL_TE | /* transmit enable */
++ MAC_CONTROL_PM | /* pass mcast */
++ MAC_CONTROL_F | /* full duplex */
++ MAC_CONTROL_HBD); /* heart beat disabled */
++
++ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
++ flags |= MAC_CONTROL_PR;
++ }
++ sp->eth_regs->mac_control = flags;
++
++ /* Set all Ethernet station address registers to their initial values */
++ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
++
++ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
++
++ sp->eth_regs->mac_addr[0] = ethsah;
++ sp->eth_regs->mac_addr[1] = ethsal;
++
++ mdelay(10);
++
++ return 0;
++}
++
++static int ar231x_init(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ int ecode = 0;
++
++ /* Allocate descriptors */
++ if (ar231x_allocate_descriptors(dev)) {
++ printk("%s: %s: ar231x_allocate_descriptors failed\n",
++ dev->name, __func__);
++ ecode = -EAGAIN;
++ goto init_error;
++ }
++
++ /* Get the memory for the skb rings */
++ if (sp->rx_skb == NULL) {
++ sp->rx_skb =
++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
++ GFP_KERNEL);
++ if (!(sp->rx_skb)) {
++ printk("%s: %s: rx_skb kmalloc failed\n",
++ dev->name, __func__);
++ ecode = -EAGAIN;
++ goto init_error;
++ }
++ }
++ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
++
++ if (sp->tx_skb == NULL) {
++ sp->tx_skb =
++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
++ GFP_KERNEL);
++ if (!(sp->tx_skb)) {
++ printk("%s: %s: tx_skb kmalloc failed\n",
++ dev->name, __func__);
++ ecode = -EAGAIN;
++ goto init_error;
++ }
++ }
++ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
++
++ /**
++ * Set tx_csm before we start receiving interrupts, otherwise
++ * the interrupt handler might think it is supposed to process
++ * tx ints before we are up and running, which may cause a null
++ * pointer access in the int handler.
++ */
++ sp->rx_skbprd = 0;
++ sp->cur_rx = 0;
++ sp->tx_prd = 0;
++ sp->tx_csm = 0;
++
++ /* Zero the stats before starting the interface */
++ memset(&dev->stats, 0, sizeof(dev->stats));
++
++ /**
++ * We load the ring here as there seem to be no way to tell the
++ * firmware to wipe the ring without re-initializing it.
++ */
++ ar231x_load_rx_ring(dev, RX_RING_SIZE);
++
++ /* Init hardware */
++ ar231x_reset_reg(dev);
++
++ /* Get the IRQ */
++ ecode = request_irq(dev->irq, &ar231x_interrupt, IRQF_DISABLED,
++ dev->name, dev);
++ if (ecode) {
++ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
++ dev->name, __func__, dev->irq);
++ goto init_error;
++ }
++
++ tasklet_enable(&sp->rx_tasklet);
++
++ return 0;
++
++init_error:
++ ar231x_init_cleanup(dev);
++ return ecode;
++}
++
++/**
++ * Load the rx ring.
++ *
++ * Loading rings is safe without holding the spin lock since this is
++ * done only before the device is enabled, thus no interrupts are
++ * generated and by the interrupt handler/tasklet handler.
++ */
++static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ short i, idx;
++
++ idx = sp->rx_skbprd;
++
++ for (i = 0; i < nr_bufs; i++) {
++ struct sk_buff *skb;
++ ar231x_descr_t *rd;
++
++ if (sp->rx_skb[idx])
++ break;
++
++ skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
++ if (!skb) {
++ printk("\n\n\n\n %s: No memory in system\n\n\n\n",
++ __func__);
++ break;
++ }
++
++ /* Make sure IP header starts on a fresh cache line */
++ skb->dev = dev;
++ sp->rx_skb[idx] = skb;
++
++ rd = (ar231x_descr_t *)&sp->rx_ring[idx];
++
++ /* initialize dma descriptor */
++ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
++ DMA_RX1_CHAINED);
++ rd->addr = virt_to_phys(skb->data);
++ rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
++ rd->status = DMA_RX_OWN;
++
++ idx = DSC_NEXT(idx);
++ }
++
++ if (i)
++ sp->rx_skbprd = idx;
++}
++
++#define AR2313_MAX_PKTS_PER_CALL 64
++
++static int ar231x_rx_int(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ struct sk_buff *skb, *skb_new;
++ ar231x_descr_t *rxdesc;
++ unsigned int status;
++ u32 idx;
++ int pkts = 0;
++ int rval;
++
++ idx = sp->cur_rx;
++
++ /* process at most the entire ring and then wait for another int */
++ while (1) {
++ rxdesc = &sp->rx_ring[idx];
++ status = rxdesc->status;
++
++ if (status & DMA_RX_OWN) {
++ /* SiByte owns descriptor or descr not yet filled in */
++ rval = 0;
++ break;
++ }
++
++ if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
++ rval = 1;
++ break;
++ }
++
++ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
++ dev->stats.rx_errors++;
++ dev->stats.rx_dropped++;
++
++ /* add statistics counters */
++ if (status & DMA_RX_ERR_CRC)
++ dev->stats.rx_crc_errors++;
++ if (status & DMA_RX_ERR_COL)
++ dev->stats.rx_over_errors++;
++ if (status & DMA_RX_ERR_LENGTH)
++ dev->stats.rx_length_errors++;
++ if (status & DMA_RX_ERR_RUNT)
++ dev->stats.rx_over_errors++;
++ if (status & DMA_RX_ERR_DESC)
++ dev->stats.rx_over_errors++;
++
++ } else {
++ /* alloc new buffer. */
++ skb_new = netdev_alloc_skb_ip_align(dev,
++ AR2313_BUFSIZE);
++ if (skb_new != NULL) {
++ skb = sp->rx_skb[idx];
++ /* set skb */
++ skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
++ 0x3fff) - CRC_LEN);
++
++ dev->stats.rx_bytes += skb->len;
++ skb->protocol = eth_type_trans(skb, dev);
++ /* pass the packet to upper layers */
++ netif_rx(skb);
++
++ skb_new->dev = dev;
++ /* reset descriptor's curr_addr */
++ rxdesc->addr = virt_to_phys(skb_new->data);
++
++ dev->stats.rx_packets++;
++ sp->rx_skb[idx] = skb_new;
++ } else {
++ dev->stats.rx_dropped++;
++ }
++ }
++
++ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
++ DMA_RX1_CHAINED);
++ rxdesc->status = DMA_RX_OWN;
++
++ idx = DSC_NEXT(idx);
++ }
++
++ sp->cur_rx = idx;
++
++ return rval;
++}
++
++static void ar231x_tx_int(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ u32 idx;
++ struct sk_buff *skb;
++ ar231x_descr_t *txdesc;
++ unsigned int status = 0;
++
++ idx = sp->tx_csm;
++
++ while (idx != sp->tx_prd) {
++ txdesc = &sp->tx_ring[idx];
++ status = txdesc->status;
++
++ if (status & DMA_TX_OWN) {
++ /* ar231x dma still owns descr */
++ break;
++ }
++ /* done with this descriptor */
++ dma_unmap_single(NULL, txdesc->addr,
++ txdesc->devcs & DMA_TX1_BSIZE_MASK,
++ DMA_TO_DEVICE);
++ txdesc->status = 0;
++
++ if (status & DMA_TX_ERROR) {
++ dev->stats.tx_errors++;
++ dev->stats.tx_dropped++;
++ if (status & DMA_TX_ERR_UNDER)
++ dev->stats.tx_fifo_errors++;
++ if (status & DMA_TX_ERR_HB)
++ dev->stats.tx_heartbeat_errors++;
++ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
++ dev->stats.tx_carrier_errors++;
++ if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
++ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
++ dev->stats.tx_aborted_errors++;
++ } else {
++ /* transmit OK */
++ dev->stats.tx_packets++;
++ }
++
++ skb = sp->tx_skb[idx];
++ sp->tx_skb[idx] = NULL;
++ idx = DSC_NEXT(idx);
++ dev->stats.tx_bytes += skb->len;
++ dev_kfree_skb_irq(skb);
++ }
++
++ sp->tx_csm = idx;
++}
++
++static void rx_tasklet_func(unsigned long data)
++{
++ struct net_device *dev = (struct net_device *)data;
++ struct ar231x_private *sp = netdev_priv(dev);
++
++ if (sp->unloading)
++ return;
++
++ if (ar231x_rx_int(dev)) {
++ tasklet_hi_schedule(&sp->rx_tasklet);
++ } else {
++ unsigned long flags;
++
++ spin_lock_irqsave(&sp->lock, flags);
++ sp->dma_regs->intr_ena |= DMA_STATUS_RI;
++ spin_unlock_irqrestore(&sp->lock, flags);
++ }
++}
++
++static void rx_schedule(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++
++ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
++
++ tasklet_hi_schedule(&sp->rx_tasklet);
++}
++
++static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
++{
++ struct net_device *dev = (struct net_device *)dev_id;
++ struct ar231x_private *sp = netdev_priv(dev);
++ unsigned int status, enabled;
++
++ /* clear interrupt */
++ /* Don't clear RI bit if currently disabled */
++ status = sp->dma_regs->status;
++ enabled = sp->dma_regs->intr_ena;
++ sp->dma_regs->status = status & enabled;
++
++ if (status & DMA_STATUS_NIS) {
++ /* normal status */
++ /**
++ * Don't schedule rx processing if interrupt
++ * is already disabled.
++ */
++ if (status & enabled & DMA_STATUS_RI) {
++ /* receive interrupt */
++ rx_schedule(dev);
++ }
++ if (status & DMA_STATUS_TI) {
++ /* transmit interrupt */
++ ar231x_tx_int(dev);
++ }
++ }
++
++ /* abnormal status */
++ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
++ ar231x_restart(dev);
++
++ return IRQ_HANDLED;
++}
++
++static int ar231x_open(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ unsigned int ethsal, ethsah;
++
++ /* reset the hardware, in case the MAC address changed */
++ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
++
++ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
++
++ sp->eth_regs->mac_addr[0] = ethsah;
++ sp->eth_regs->mac_addr[1] = ethsal;
++
++ mdelay(10);
++
++ dev->mtu = 1500;
++ netif_start_queue(dev);
++
++ sp->eth_regs->mac_control |= MAC_CONTROL_RE;
++
++ return 0;
++}
++
++static void ar231x_tx_timeout(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ unsigned long flags;
++
++ spin_lock_irqsave(&sp->lock, flags);
++ ar231x_restart(dev);
++ spin_unlock_irqrestore(&sp->lock, flags);
++}
++
++static void ar231x_halt(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ int j;
++
++ tasklet_disable(&sp->rx_tasklet);
++
++ /* kill the MAC */
++ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
++ MAC_CONTROL_TE); /* disable Transmits */
++ /* stop dma */
++ sp->dma_regs->control = 0;
++ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
++
++ /* place phy and MAC in reset */
++ sp->cfg->reset_set(sp->cfg->reset_mac);
++ sp->cfg->reset_set(sp->cfg->reset_phy);
++
++ /* free buffers on tx ring */
++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
++ struct sk_buff *skb;
++ ar231x_descr_t *txdesc;
++
++ txdesc = &sp->tx_ring[j];
++ txdesc->descr = 0;
++
++ skb = sp->tx_skb[j];
++ if (skb) {
++ dev_kfree_skb(skb);
++ sp->tx_skb[j] = NULL;
++ }
++ }
++}
++
++/**
++ * close should do nothing. Here's why. It's called when
++ * 'ifconfig bond0 down' is run. If it calls free_irq then
++ * the irq is gone forever ! When bond0 is made 'up' again,
++ * the ar231x_open () does not call request_irq (). Worse,
++ * the call to ar231x_halt() generates a WDOG reset due to
++ * the write to reset register and the box reboots.
++ * Commenting this out is good since it allows the
++ * system to resume when bond0 is made up again.
++ */
++static int ar231x_close(struct net_device *dev)
++{
++#if 0
++ /* Disable interrupts */
++ disable_irq(dev->irq);
++
++ /**
++ * Without (or before) releasing irq and stopping hardware, this
++ * is an absolute non-sense, by the way. It will be reset instantly
++ * by the first irq.
++ */
++ netif_stop_queue(dev);
++
++ /* stop the MAC and DMA engines */
++ ar231x_halt(dev);
++
++ /* release the interrupt */
++ free_irq(dev->irq, dev);
++
++#endif
++ return 0;
++}
++
++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ ar231x_descr_t *td;
++ u32 idx;
++
++ idx = sp->tx_prd;
++ td = &sp->tx_ring[idx];
++
++ if (td->status & DMA_TX_OWN) {
++ /* free skbuf and lie to the caller that we sent it out */
++ dev->stats.tx_dropped++;
++ dev_kfree_skb(skb);
++
++ /* restart transmitter in case locked */
++ sp->dma_regs->xmt_poll = 0;
++ return 0;
++ }
++
++ /* Setup the transmit descriptor. */
++ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
++ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
++ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
++ td->status = DMA_TX_OWN;
++
++ /* kick transmitter last */
++ sp->dma_regs->xmt_poll = 0;
++
++ sp->tx_skb[idx] = skb;
++ idx = DSC_NEXT(idx);
++ sp->tx_prd = idx;
++
++ return 0;
++}
++
++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++
++ switch (cmd) {
++ case SIOCGMIIPHY:
++ case SIOCGMIIREG:
++ case SIOCSMIIREG:
++ return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
++
++ default:
++ break;
++ }
++
++ return -EOPNOTSUPP;
++}
++
++static void ar231x_adjust_link(struct net_device *dev)
++{
++ struct ar231x_private *sp = netdev_priv(dev);
++ unsigned int mc;
++
++ if (!sp->phy_dev->link)
++ return;
++
++ if (sp->phy_dev->duplex != sp->oldduplex) {
++ mc = readl(&sp->eth_regs->mac_control);
++ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
++ if (sp->phy_dev->duplex)
++ mc |= MAC_CONTROL_F;
++ else
++ mc |= MAC_CONTROL_DRO;
++ writel(mc, &sp->eth_regs->mac_control);
++ sp->oldduplex = sp->phy_dev->duplex;
++ }
++}
++
++#define MII_ADDR(phy, reg) \
++ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
++
++static int
++ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
++{
++ struct net_device *const dev = bus->priv;
++ struct ar231x_private *sp = netdev_priv(dev);
++ volatile MII *ethernet = sp->phy_regs;
++
++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
++ while (ethernet->mii_addr & MII_ADDR_BUSY)
++ ;
++ return ethernet->mii_data >> MII_DATA_SHIFT;
++}
++
++static int
++ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
++{
++ struct net_device *const dev = bus->priv;
++ struct ar231x_private *sp = netdev_priv(dev);
++ volatile MII *ethernet = sp->phy_regs;
++
++ while (ethernet->mii_addr & MII_ADDR_BUSY)
++ ;
++ ethernet->mii_data = value << MII_DATA_SHIFT;
++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
++
++ return 0;
++}
++
++static int ar231x_mdiobus_reset(struct mii_bus *bus)
++{
++ struct net_device *const dev = bus->priv;
++
++ ar231x_reset_reg(dev);
++
++ return 0;
++}
++
++static int ar231x_mdiobus_probe(struct net_device *dev)
++{
++ struct ar231x_private *const sp = netdev_priv(dev);
++ struct phy_device *phydev = NULL;
++ int phy_addr;
++
++ /* find the first (lowest address) PHY on the current MAC's MII bus */
++ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
++ if (sp->mii_bus->phy_map[phy_addr]) {
++ phydev = sp->mii_bus->phy_map[phy_addr];
++ sp->phy = phy_addr;
++ break; /* break out with first one found */
++ }
++
++ if (!phydev) {
++ printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
++ return -1;
++ }
++
++ /* now we are supposed to have a proper phydev, to attach to... */
++ BUG_ON(!phydev);
++ BUG_ON(phydev->attached_dev);
++
++ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link,
++ PHY_INTERFACE_MODE_MII);
++
++ if (IS_ERR(phydev)) {
++ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
++ return PTR_ERR(phydev);
++ }
++
++ /* mask with MAC supported features */
++ phydev->supported &= (SUPPORTED_10baseT_Half
++ | SUPPORTED_10baseT_Full
++ | SUPPORTED_100baseT_Half
++ | SUPPORTED_100baseT_Full
++ | SUPPORTED_Autoneg
++ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
++ | SUPPORTED_MII
++ | SUPPORTED_TP);
++
++ phydev->advertising = phydev->supported;
++
++ sp->oldduplex = -1;
++ sp->phy_dev = phydev;
++
++ printk(KERN_INFO "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
++ dev->name, phydev->drv->name, dev_name(&phydev->dev));
++
++ return 0;
++}
++
+--- /dev/null
++++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h
+@@ -0,0 +1,288 @@
++/*
++ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
++ *
++ * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++ *
++ * Thanks to Atheros for providing hardware and documentation
++ * enabling me to write this driver.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef _AR2313_H_
++#define _AR2313_H_
++
++#include <linux/interrupt.h>
++#include <generated/autoconf.h>
++#include <linux/bitops.h>
++#include <ath25_platform.h>
++
++/* probe link timer - 5 secs */
++#define LINK_TIMER (5*HZ)
++
++#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
++#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
++#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
++
++#define AR2313_TX_TIMEOUT (HZ/4)
++
++/* Rings */
++#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
++#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
++
++#define AR2313_MBGET 2
++#define AR2313_MBSET 3
++#define AR2313_PCI_RECONFIG 4
++#define AR2313_PCI_DUMP 5
++#define AR2313_TEST_PANIC 6
++#define AR2313_TEST_NULLPTR 7
++#define AR2313_READ_DATA 8
++#define AR2313_WRITE_DATA 9
++#define AR2313_GET_VERSION 10
++#define AR2313_TEST_HANG 11
++#define AR2313_SYNC 12
++
++#define DMA_RX_ERR_CRC BIT(1)
++#define DMA_RX_ERR_DRIB BIT(2)
++#define DMA_RX_ERR_MII BIT(3)
++#define DMA_RX_EV2 BIT(5)
++#define DMA_RX_ERR_COL BIT(6)
++#define DMA_RX_LONG BIT(7)
++#define DMA_RX_LS BIT(8) /* last descriptor */
++#define DMA_RX_FS BIT(9) /* first descriptor */
++#define DMA_RX_MF BIT(10) /* multicast frame */
++#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
++#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
++#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
++#define DMA_RX_ERROR BIT(15) /* error summary */
++#define DMA_RX_LEN_MASK 0x3fff0000
++#define DMA_RX_LEN_SHIFT 16
++#define DMA_RX_FILT BIT(30)
++#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
++
++#define DMA_RX1_BSIZE_MASK 0x000007ff
++#define DMA_RX1_BSIZE_SHIFT 0
++#define DMA_RX1_CHAINED BIT(24)
++#define DMA_RX1_RER BIT(25)
++
++#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
++#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
++#define DMA_TX_COL_MASK 0x78
++#define DMA_TX_COL_SHIFT 3
++#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
++#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
++#define DMA_TX_ERR_LATE BIT(9) /* late collision */
++#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
++#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
++#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
++#define DMA_TX_ERROR BIT(15) /* frame aborted */
++#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
++
++#define DMA_TX1_BSIZE_MASK 0x000007ff
++#define DMA_TX1_BSIZE_SHIFT 0
++#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
++#define DMA_TX1_TER BIT(25) /* transmit end of ring */
++#define DMA_TX1_FS BIT(29) /* first segment */
++#define DMA_TX1_LS BIT(30) /* last segment */
++#define DMA_TX1_IC BIT(31) /* interrupt on completion */
++
++#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
++
++#define MAC_CONTROL_RE BIT(2) /* receive enable */
++#define MAC_CONTROL_TE BIT(3) /* transmit enable */
++#define MAC_CONTROL_DC BIT(5) /* Deferral check */
++#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
++#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
++#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
++#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
++#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
++#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
++#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
++#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
++#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
++#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
++#define MAC_CONTROL_PM BIT(19) /* pass multicast */
++#define MAC_CONTROL_F BIT(20) /* full-duplex */
++#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
++#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
++#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
++#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
++
++#define MII_ADDR_BUSY BIT(0)
++#define MII_ADDR_WRITE BIT(1)
++#define MII_ADDR_REG_SHIFT 6
++#define MII_ADDR_PHY_SHIFT 11
++#define MII_DATA_SHIFT 0
++
++#define FLOW_CONTROL_FCE BIT(1)
++
++#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
++#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
++#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
++#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
++
++#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
++#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
++#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
++#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
++#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
++#define DMA_STATUS_RI BIT(6) /* receive interrupt */
++#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
++#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
++#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
++#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
++#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
++#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
++#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
++#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
++#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
++#define DMA_STATUS_EB_SHIFT 23 /* error bits */
++
++#define DMA_CONTROL_SR BIT(1) /* start receive */
++#define DMA_CONTROL_ST BIT(13) /* start transmit */
++#define DMA_CONTROL_SF BIT(21) /* store and forward */
++
++typedef struct {
++ volatile unsigned int status; /* OWN, Device control and status. */
++ volatile unsigned int devcs; /* pkt Control bits + Length */
++ volatile unsigned int addr; /* Current Address. */
++ volatile unsigned int descr; /* Next descriptor in chain. */
++} ar231x_descr_t;
++
++/**
++ * New Combo structure for Both Eth0 AND eth1
++ *
++ * Don't directly access MII related regs since phy chip could be actually
++ * connected to another ethernet block.
++ */
++typedef struct {
++ volatile unsigned int mac_control; /* 0x00 */
++ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
++ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
++ volatile unsigned int __mii_addr; /* 0x14 */
++ volatile unsigned int __mii_data; /* 0x18 */
++ volatile unsigned int flow_control; /* 0x1c */
++ volatile unsigned int vlan_tag; /* 0x20 */
++ volatile unsigned int pad[7]; /* 0x24 - 0x3c */
++ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
++} ETHERNET_STRUCT;
++
++typedef struct {
++ volatile unsigned int mii_addr;
++ volatile unsigned int mii_data;
++} MII;
++
++/********************************************************************
++ * Interrupt controller
++ ********************************************************************/
++
++typedef struct {
++ volatile unsigned int wdog_control; /* 0x08 */
++ volatile unsigned int wdog_timer; /* 0x0c */
++ volatile unsigned int misc_status; /* 0x10 */
++ volatile unsigned int misc_mask; /* 0x14 */
++ volatile unsigned int global_status; /* 0x18 */
++ volatile unsigned int reserved; /* 0x1c */
++ volatile unsigned int reset_control; /* 0x20 */
++} INTERRUPT;
++
++/********************************************************************
++ * DMA controller
++ ********************************************************************/
++typedef struct {
++ volatile unsigned int bus_mode; /* 0x00 (CSR0) */
++ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
++ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
++ volatile unsigned int rcv_base; /* 0x0c (CSR3) */
++ volatile unsigned int xmt_base; /* 0x10 (CSR4) */
++ volatile unsigned int status; /* 0x14 (CSR5) */
++ volatile unsigned int control; /* 0x18 (CSR6) */
++ volatile unsigned int intr_ena; /* 0x1c (CSR7) */
++ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
++ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
++ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
++ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
++} DMA;
++
++/**
++ * Struct private for the Sibyte.
++ *
++ * Elements are grouped so variables used by the tx handling goes
++ * together, and will go into the same cache lines etc. in order to
++ * avoid cache line contention between the rx and tx handling on SMP.
++ *
++ * Frequently accessed variables are put at the beginning of the
++ * struct to help the compiler generate better/shorter code.
++ */
++struct ar231x_private {
++ struct net_device *dev;
++ int version;
++ u32 mb[2];
++
++ volatile MII *phy_regs;
++ volatile ETHERNET_STRUCT *eth_regs;
++ volatile DMA *dma_regs;
++ struct ar231x_eth *cfg;
++
++ spinlock_t lock; /* Serialise access to device */
++
++ /* RX and TX descriptors, must be adjacent */
++ ar231x_descr_t *rx_ring;
++ ar231x_descr_t *tx_ring;
++
++ struct sk_buff **rx_skb;
++ struct sk_buff **tx_skb;
++
++ /* RX elements */
++ u32 rx_skbprd;
++ u32 cur_rx;
++
++ /* TX elements */
++ u32 tx_prd;
++ u32 tx_csm;
++
++ /* Misc elements */
++ char name[48];
++ struct {
++ u32 address;
++ u32 length;
++ char *mapping;
++ } desc;
++
++ struct timer_list link_timer;
++ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
++ unsigned short mac;
++ unsigned short link; /* 0 - link down, 1 - link up */
++ u16 phy_data;
++
++ struct tasklet_struct rx_tasklet;
++ int unloading;
++
++ struct phy_device *phy_dev;
++ struct mii_bus *mii_bus;
++ int oldduplex;
++};
++
++/* Prototypes */
++static int ar231x_init(struct net_device *dev);
++#ifdef TX_TIMEOUT
++static void ar231x_tx_timeout(struct net_device *dev);
++#endif
++static int ar231x_restart(struct net_device *dev);
++static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
++static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
++static int ar231x_open(struct net_device *dev);
++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
++static int ar231x_close(struct net_device *dev);
++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
++static void ar231x_init_cleanup(struct net_device *dev);
++static int ar231x_setup_timer(struct net_device *dev);
++static void ar231x_link_timer_fn(unsigned long data);
++static void ar231x_check_link(struct net_device *dev);
++
++#endif /* _AR2313_H_ */
+--- a/arch/mips/ath25/ar2315_regs.h
++++ b/arch/mips/ath25/ar2315_regs.h
+@@ -57,6 +57,9 @@
+ #define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
+ #define AR2315_PCI_EXT_SIZE 0x40000000
+
++/* MII registers offset inside Ethernet MMR region */
++#define AR2315_ENET0_MII_BASE (AR2315_ENET0_BASE + 0x14)
++
+ /*
+ * Configuration registers
+ */
+--- a/arch/mips/ath25/ar5312_regs.h
++++ b/arch/mips/ath25/ar5312_regs.h
+@@ -64,6 +64,10 @@
+ #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
+ #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
+
++/* MII registers offset inside Ethernet MMR region */
++#define AR5312_ENET0_MII_BASE (AR5312_ENET0_BASE + 0x14)
++#define AR5312_ENET1_MII_BASE (AR5312_ENET1_BASE + 0x14)
++
+ /* Reset/Timer Block Address Map */
+ #define AR5312_TIMER 0x0000 /* countdown timer */
+ #define AR5312_RELOAD 0x0004 /* timer reload value */
+--- a/arch/mips/ath25/ar2315.c
++++ b/arch/mips/ath25/ar2315.c
+@@ -136,6 +136,8 @@ static void ar2315_irq_dispatch(void)
+
+ if (pending & CAUSEF_IP3)
+ do_IRQ(AR2315_IRQ_WLAN0);
++ else if (pending & CAUSEF_IP4)
++ do_IRQ(AR2315_IRQ_ENET0);
+ #ifdef CONFIG_PCI_AR2315
+ else if (pending & CAUSEF_IP5)
+ do_IRQ(AR2315_IRQ_LCBUS_PCI);
+@@ -169,6 +171,29 @@ void __init ar2315_arch_init_irq(void)
+ ar2315_misc_irq_domain = domain;
+ }
+
++static void ar2315_device_reset_set(u32 mask)
++{
++ u32 val;
++
++ val = ar2315_rst_reg_read(AR2315_RESET);
++ ar2315_rst_reg_write(AR2315_RESET, val | mask);
++}
++
++static void ar2315_device_reset_clear(u32 mask)
++{
++ u32 val;
++
++ val = ar2315_rst_reg_read(AR2315_RESET);
++ ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
++}
++
++static struct ar231x_eth ar2315_eth_data = {
++ .reset_set = ar2315_device_reset_set,
++ .reset_clear = ar2315_device_reset_clear,
++ .reset_mac = AR2315_RESET_ENET0,
++ .reset_phy = AR2315_RESET_EPHY0,
++};
++
+ static struct resource ar2315_gpio_res[] = {
+ {
+ .name = "ar2315-gpio",
+@@ -205,6 +230,11 @@ void __init ar2315_init_devices(void)
+ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
+ platform_device_register(&ar2315_gpio);
+
++ ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
++ ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
++ AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
++ &ar2315_eth_data);
++
+ ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
+ }
+
+--- a/arch/mips/ath25/ar5312.c
++++ b/arch/mips/ath25/ar5312.c
+@@ -132,6 +132,10 @@ static void ar5312_irq_dispatch(void)
+
+ if (pending & CAUSEF_IP2)
+ do_IRQ(AR5312_IRQ_WLAN0);
++ else if (pending & CAUSEF_IP3)
++ do_IRQ(AR5312_IRQ_ENET0);
++ else if (pending & CAUSEF_IP4)
++ do_IRQ(AR5312_IRQ_ENET1);
+ else if (pending & CAUSEF_IP5)
+ do_IRQ(AR5312_IRQ_WLAN1);
+ else if (pending & CAUSEF_IP6)
+@@ -163,6 +167,36 @@ void __init ar5312_arch_init_irq(void)
+ ar5312_misc_irq_domain = domain;
+ }
+
++static void ar5312_device_reset_set(u32 mask)
++{
++ u32 val;
++
++ val = ar5312_rst_reg_read(AR5312_RESET);
++ ar5312_rst_reg_write(AR5312_RESET, val | mask);
++}
++
++static void ar5312_device_reset_clear(u32 mask)
++{
++ u32 val;
++
++ val = ar5312_rst_reg_read(AR5312_RESET);
++ ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
++}
++
++static struct ar231x_eth ar5312_eth0_data = {
++ .reset_set = ar5312_device_reset_set,
++ .reset_clear = ar5312_device_reset_clear,
++ .reset_mac = AR5312_RESET_ENET0,
++ .reset_phy = AR5312_RESET_EPHY0,
++};
++
++static struct ar231x_eth ar5312_eth1_data = {
++ .reset_set = ar5312_device_reset_set,
++ .reset_clear = ar5312_device_reset_clear,
++ .reset_mac = AR5312_RESET_ENET1,
++ .reset_phy = AR5312_RESET_EPHY1,
++};
++
+ static struct physmap_flash_data ar5312_flash_data = {
+ .width = 2,
+ };
+@@ -243,6 +277,7 @@ static void __init ar5312_flash_init(voi
+ void __init ar5312_init_devices(void)
+ {
+ struct ath25_boarddata *config;
++ u8 *c;
+
+ ar5312_flash_init();
+
+@@ -266,8 +301,30 @@ void __init ar5312_init_devices(void)
+
+ platform_device_register(&ar5312_gpio);
+
++ /* Fix up MAC addresses if necessary */
++ if (is_broadcast_ether_addr(config->enet0_mac))
++ ether_addr_copy(config->enet0_mac, config->enet1_mac);
++
++ /* If ENET0 and ENET1 have the same mac address,
++ * increment the one from ENET1 */
++ if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
++ c = config->enet1_mac + 5;
++ while ((c >= config->enet1_mac) && !(++(*c)))
++ c--;
++ }
++
+ switch (ath25_soc) {
+ case ATH25_SOC_AR5312:
++ ar5312_eth0_data.macaddr = config->enet0_mac;
++ ath25_add_ethernet(0, AR5312_ENET0_BASE, "eth0_mii",
++ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0,
++ &ar5312_eth0_data);
++
++ ar5312_eth1_data.macaddr = config->enet1_mac;
++ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth1_mii",
++ AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1,
++ &ar5312_eth1_data);
++
+ if (!ath25_board.radio)
+ return;
+
+@@ -276,8 +333,18 @@ void __init ar5312_init_devices(void)
+
+ ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
+ break;
++ /*
++ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
++ * of ENET1. Atheros calls it 'twisted' for a reason :)
++ */
+ case ATH25_SOC_AR2312:
+ case ATH25_SOC_AR2313:
++ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
++ ar5312_eth1_data.macaddr = config->enet0_mac;
++ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth0_mii",
++ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1,
++ &ar5312_eth1_data);
++
+ if (!ath25_board.radio)
+ return;
+ break;
+--- a/arch/mips/ath25/devices.h
++++ b/arch/mips/ath25/devices.h
+@@ -32,6 +32,8 @@ extern struct ar231x_board_config ath25_
+ extern void (*ath25_irq_dispatch)(void);
+
+ int ath25_find_config(phys_addr_t offset, unsigned long size);
++int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
++ int irq, void *pdata);
+ void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
+ int ath25_add_wmac(int nr, u32 base, int irq);
+
+--- a/arch/mips/ath25/devices.c
++++ b/arch/mips/ath25/devices.c
+@@ -12,6 +12,51 @@
+ struct ar231x_board_config ath25_board;
+ enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
+
++static struct resource ath25_eth0_res[] = {
++ {
++ .name = "eth0_membase",
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "eth0_mii",
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "eth0_irq",
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct resource ath25_eth1_res[] = {
++ {
++ .name = "eth1_membase",
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "eth1_mii",
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "eth1_irq",
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device ath25_eth[] = {
++ {
++ .id = 0,
++ .name = "ar231x-eth",
++ .resource = ath25_eth0_res,
++ .num_resources = ARRAY_SIZE(ath25_eth0_res)
++ },
++ {
++ .id = 1,
++ .name = "ar231x-eth",
++ .resource = ath25_eth1_res,
++ .num_resources = ARRAY_SIZE(ath25_eth1_res)
++ }
++};
++
+ static struct resource ath25_wmac0_res[] = {
+ {
+ .name = "wmac0_membase",
+@@ -70,6 +115,25 @@ const char *get_system_type(void)
+ return soc_type_strings[ath25_soc];
+ }
+
++int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
++ u32 mii_base, int irq, void *pdata)
++{
++ struct resource *res;
++
++ ath25_eth[nr].dev.platform_data = pdata;
++ res = &ath25_eth[nr].resource[0];
++ res->start = base;
++ res->end = base + 0x2000 - 1;
++ res++;
++ res->name = mii_name;
++ res->start = mii_base;
++ res->end = mii_base + 8 - 1;
++ res++;
++ res->start = irq;
++ res->end = irq;
++ return platform_device_register(&ath25_eth[nr]);
++}
++
+ void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
+ {
+ struct uart_port s;
+--- a/arch/mips/include/asm/mach-ath25/ath25_platform.h
++++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
+@@ -70,4 +70,15 @@ struct ar231x_board_config {
+ const char *radio;
+ };
+
++/*
++ * Platform device information for the Ethernet MAC
++ */
++struct ar231x_eth {
++ void (*reset_set)(u32);
++ void (*reset_clear)(u32);
++ u32 reset_mac;
++ u32 reset_phy;
++ char *macaddr;
++};
++
+ #endif /* __ASM_MACH_ATH25_PLATFORM_H */
--- /dev/null
+--- a/drivers/mtd/devices/Kconfig
++++ b/drivers/mtd/devices/Kconfig
+@@ -120,6 +120,10 @@ config MTD_BCM47XXSFLASH
+ registered by bcma as platform devices. This enables driver for
+ serial flash memories (only read-only mode is implemented).
+
++config MTD_AR2315
++ tristate "Atheros AR2315+ SPI Flash support"
++ depends on SOC_AR2315
++
+ config MTD_SLRAM
+ tristate "Uncached system RAM"
+ help
+--- a/drivers/mtd/devices/Makefile
++++ b/drivers/mtd/devices/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataf
+ obj-$(CONFIG_MTD_M25P80) += m25p80.o
+ obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o
+ obj-$(CONFIG_MTD_SST25L) += sst25l.o
++obj-$(CONFIG_MTD_AR2315) += ar2315.o
+ obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
+ obj-$(CONFIG_MTD_ST_SPI_FSM) += st_spi_fsm.o
+
+--- /dev/null
++++ b/drivers/mtd/devices/ar2315.c
+@@ -0,0 +1,459 @@
++
++/*
++ * MTD driver for the SPI Flash Memory support on Atheros AR2315
++ *
++ * Copyright (c) 2005-2006 Atheros Communications Inc.
++ * Copyright (C) 2006-2007 FON Technology, SL.
++ * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
++ *
++ * This code is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/errno.h>
++#include <linux/slab.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/platform_device.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/mutex.h>
++
++#include "ar2315_spiflash.h"
++
++#define DRIVER_NAME "ar2315-spiflash"
++
++#define busy_wait(_priv, _condition, _wait) do { \
++ while (_condition) { \
++ if (_wait > 1) \
++ msleep(_wait); \
++ else if ((_wait == 1) && need_resched()) \
++ schedule(); \
++ else \
++ udelay(1); \
++ } \
++} while (0)
++
++enum {
++ FLASH_NONE,
++ FLASH_1MB,
++ FLASH_2MB,
++ FLASH_4MB,
++ FLASH_8MB,
++ FLASH_16MB,
++};
++
++/* Flash configuration table */
++struct flashconfig {
++ u32 byte_cnt;
++ u32 sector_cnt;
++ u32 sector_size;
++};
++
++static const struct flashconfig flashconfig_tbl[] = {
++ [FLASH_NONE] = { 0, 0, 0},
++ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,
++ STM_1MB_SECTOR_SIZE},
++ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,
++ STM_2MB_SECTOR_SIZE},
++ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,
++ STM_4MB_SECTOR_SIZE},
++ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,
++ STM_8MB_SECTOR_SIZE},
++ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,
++ STM_16MB_SECTOR_SIZE}
++};
++
++/* Mapping of generic opcodes to STM serial flash opcodes */
++enum {
++ SPI_WRITE_ENABLE,
++ SPI_WRITE_DISABLE,
++ SPI_RD_STATUS,
++ SPI_WR_STATUS,
++ SPI_RD_DATA,
++ SPI_FAST_RD_DATA,
++ SPI_PAGE_PROGRAM,
++ SPI_SECTOR_ERASE,
++ SPI_BULK_ERASE,
++ SPI_DEEP_PWRDOWN,
++ SPI_RD_SIG,
++};
++
++struct opcodes {
++ __u16 code;
++ __s8 tx_cnt;
++ __s8 rx_cnt;
++};
++
++static const struct opcodes stm_opcodes[] = {
++ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
++ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
++ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
++ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
++ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
++ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
++ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
++ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
++ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
++ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
++ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
++};
++
++/* Driver private data structure */
++struct spiflash_priv {
++ struct mtd_info mtd;
++ void __iomem *readaddr; /* memory mapped data for read */
++ void __iomem *mmraddr; /* memory mapped register space */
++ struct mutex lock; /* serialize registers access */
++};
++
++#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
++
++enum {
++ FL_READY,
++ FL_READING,
++ FL_ERASING,
++ FL_WRITING
++};
++
++/*****************************************************************************/
++
++static u32
++spiflash_read_reg(struct spiflash_priv *priv, int reg)
++{
++ return ioread32(priv->mmraddr + reg);
++}
++
++static void
++spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
++{
++ iowrite32(data, priv->mmraddr + reg);
++}
++
++static u32
++spiflash_wait_busy(struct spiflash_priv *priv)
++{
++ u32 reg;
++
++ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
++ SPI_CTL_BUSY, 0);
++ return reg;
++}
++
++static u32
++spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
++{
++ const struct opcodes *op;
++ u32 reg, mask;
++
++ op = &stm_opcodes[opcode];
++ reg = spiflash_wait_busy(priv);
++ spiflash_write_reg(priv, SPI_FLASH_OPCODE,
++ ((u32)op->code) | (addr << 8));
++
++ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
++ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
++
++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
++ spiflash_wait_busy(priv);
++
++ if (!op->rx_cnt)
++ return 0;
++
++ reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
++
++ switch (op->rx_cnt) {
++ case 1:
++ mask = 0x000000ff;
++ break;
++ case 2:
++ mask = 0x0000ffff;
++ break;
++ case 3:
++ mask = 0x00ffffff;
++ break;
++ default:
++ mask = 0xffffffff;
++ break;
++ }
++ reg &= mask;
++
++ return reg;
++}
++
++/*
++ * Probe SPI flash device
++ * Function returns 0 for failure.
++ * and flashconfig_tbl array index for success.
++ */
++static int
++spiflash_probe_chip(struct platform_device *pdev, struct spiflash_priv *priv)
++{
++ u32 sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
++ int flash_size;
++
++ switch (sig) {
++ case STM_8MBIT_SIGNATURE:
++ flash_size = FLASH_1MB;
++ break;
++ case STM_16MBIT_SIGNATURE:
++ flash_size = FLASH_2MB;
++ break;
++ case STM_32MBIT_SIGNATURE:
++ flash_size = FLASH_4MB;
++ break;
++ case STM_64MBIT_SIGNATURE:
++ flash_size = FLASH_8MB;
++ break;
++ case STM_128MBIT_SIGNATURE:
++ flash_size = FLASH_16MB;
++ break;
++ default:
++ dev_warn(&pdev->dev, "read of flash device signature failed!\n");
++ return 0;
++ }
++
++ return flash_size;
++}
++
++static void
++spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
++{
++ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
++ SPI_STATUS_WIP, timeout);
++}
++
++static int
++spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
++{
++ struct spiflash_priv *priv = to_spiflash(mtd);
++ const struct opcodes *op;
++ u32 temp, reg;
++
++ if (instr->addr + instr->len > mtd->size)
++ return -EINVAL;
++
++ mutex_lock(&priv->lock);
++
++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
++ reg = spiflash_wait_busy(priv);
++
++ op = &stm_opcodes[SPI_SECTOR_ERASE];
++ temp = ((u32)instr->addr << 8) | (u32)(op->code);
++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
++
++ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
++ reg |= op->tx_cnt | SPI_CTL_START;
++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
++
++ spiflash_wait_complete(priv, 20);
++
++ mutex_unlock(&priv->lock);
++
++ instr->state = MTD_ERASE_DONE;
++ mtd_erase_callback(instr);
++
++ return 0;
++}
++
++static int
++spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
++ u_char *buf)
++{
++ struct spiflash_priv *priv = to_spiflash(mtd);
++
++ if (!len)
++ return 0;
++
++ if (from + len > mtd->size)
++ return -EINVAL;
++
++ *retlen = len;
++
++ mutex_lock(&priv->lock);
++
++ memcpy_fromio(buf, priv->readaddr + from, len);
++
++ mutex_unlock(&priv->lock);
++
++ return 0;
++}
++
++static int
++spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
++ const u8 *buf)
++{
++ struct spiflash_priv *priv = to_spiflash(mtd);
++ u32 opcode, bytes_left;
++
++ *retlen = 0;
++
++ if (!len)
++ return 0;
++
++ if (to + len > mtd->size)
++ return -EINVAL;
++
++ bytes_left = len;
++
++ do {
++ u32 read_len, reg, page_offset, spi_data = 0;
++
++ read_len = min(bytes_left, sizeof(u32));
++
++ /* 32-bit writes cannot span across a page boundary
++ * (256 bytes). This types of writes require two page
++ * program operations to handle it correctly. The STM part
++ * will write the overflow data to the beginning of the
++ * current page as opposed to the subsequent page.
++ */
++ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
++
++ if (page_offset > STM_PAGE_SIZE)
++ read_len -= (page_offset - STM_PAGE_SIZE);
++
++ mutex_lock(&priv->lock);
++
++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
++ spi_data = 0;
++ switch (read_len) {
++ case 4:
++ spi_data |= buf[3] << 24;
++ /* fall through */
++ case 3:
++ spi_data |= buf[2] << 16;
++ /* fall through */
++ case 2:
++ spi_data |= buf[1] << 8;
++ /* fall through */
++ case 1:
++ spi_data |= buf[0] & 0xff;
++ break;
++ default:
++ break;
++ }
++
++ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
++ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
++ (to & 0x00ffffff) << 8;
++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
++
++ reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
++ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
++ reg |= (read_len + 4) | SPI_CTL_START;
++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
++
++ spiflash_wait_complete(priv, 1);
++
++ mutex_unlock(&priv->lock);
++
++ bytes_left -= read_len;
++ to += read_len;
++ buf += read_len;
++
++ *retlen += read_len;
++ } while (bytes_left != 0);
++
++ return 0;
++}
++
++#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
++static const char * const part_probe_types[] = {
++ "cmdlinepart", "RedBoot", "MyLoader", NULL
++};
++#endif
++
++static int
++spiflash_probe(struct platform_device *pdev)
++{
++ struct spiflash_priv *priv;
++ struct mtd_info *mtd;
++ struct resource *res;
++ int index;
++ int result = 0;
++
++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ mutex_init(&priv->lock);
++ mtd = &priv->mtd;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ priv->mmraddr = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(priv->mmraddr)) {
++ dev_warn(&pdev->dev, "failed to map flash MMR\n");
++ return PTR_ERR(priv->mmraddr);
++ }
++
++ index = spiflash_probe_chip(pdev, priv);
++ if (!index) {
++ dev_warn(&pdev->dev, "found no flash device\n");
++ return -ENODEV;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ priv->readaddr = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(priv->readaddr)) {
++ dev_warn(&pdev->dev, "failed to map flash read mem\n");
++ return PTR_ERR(priv->readaddr);
++ }
++
++ platform_set_drvdata(pdev, priv);
++ mtd->name = "spiflash";
++ mtd->type = MTD_NORFLASH;
++ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
++ mtd->size = flashconfig_tbl[index].byte_cnt;
++ mtd->erasesize = flashconfig_tbl[index].sector_size;
++ mtd->writesize = 1;
++ mtd->numeraseregions = 0;
++ mtd->eraseregions = NULL;
++ mtd->_erase = spiflash_erase;
++ mtd->_read = spiflash_read;
++ mtd->_write = spiflash_write;
++ mtd->owner = THIS_MODULE;
++
++ dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10);
++
++#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
++ /* parse redboot partitions */
++
++ result = mtd_device_parse_register(mtd, part_probe_types,
++ NULL, NULL, 0);
++#endif
++
++ return result;
++}
++
++static int
++spiflash_remove(struct platform_device *pdev)
++{
++ struct spiflash_priv *priv = platform_get_drvdata(pdev);
++
++ mtd_device_unregister(&priv->mtd);
++
++ return 0;
++}
++
++static struct platform_driver spiflash_driver = {
++ .driver.name = DRIVER_NAME,
++ .probe = spiflash_probe,
++ .remove = spiflash_remove,
++};
++
++module_platform_driver(spiflash_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("OpenWrt.org");
++MODULE_AUTHOR("Atheros Communications Inc");
++MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros AR2315+ SOC");
++MODULE_ALIAS("platform:" DRIVER_NAME);
++
+--- /dev/null
++++ b/drivers/mtd/devices/ar2315_spiflash.h
+@@ -0,0 +1,106 @@
++/*
++ * Atheros AR2315 SPI Flash Memory support header file.
++ *
++ * Copyright (c) 2005, Atheros Communications Inc.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++ *
++ * This code is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#ifndef __AR2315_SPIFLASH_H
++#define __AR2315_SPIFLASH_H
++
++#define STM_PAGE_SIZE 256
++
++#define SFI_WRITE_BUFFER_SIZE 4
++#define SFI_FLASH_ADDR_MASK 0x00ffffff
++
++#define STM_8MBIT_SIGNATURE 0x13
++#define STM_M25P80_BYTE_COUNT 1048576
++#define STM_M25P80_SECTOR_COUNT 16
++#define STM_M25P80_SECTOR_SIZE 0x10000
++
++#define STM_16MBIT_SIGNATURE 0x14
++#define STM_M25P16_BYTE_COUNT 2097152
++#define STM_M25P16_SECTOR_COUNT 32
++#define STM_M25P16_SECTOR_SIZE 0x10000
++
++#define STM_32MBIT_SIGNATURE 0x15
++#define STM_M25P32_BYTE_COUNT 4194304
++#define STM_M25P32_SECTOR_COUNT 64
++#define STM_M25P32_SECTOR_SIZE 0x10000
++
++#define STM_64MBIT_SIGNATURE 0x16
++#define STM_M25P64_BYTE_COUNT 8388608
++#define STM_M25P64_SECTOR_COUNT 128
++#define STM_M25P64_SECTOR_SIZE 0x10000
++
++#define STM_128MBIT_SIGNATURE 0x17
++#define STM_M25P128_BYTE_COUNT 16777216
++#define STM_M25P128_SECTOR_COUNT 256
++#define STM_M25P128_SECTOR_SIZE 0x10000
++
++#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
++#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
++#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
++#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
++#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
++#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
++#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
++#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
++#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
++#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
++#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
++#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
++#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
++#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
++#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
++
++/*
++ * ST Microelectronics Opcodes for Serial Flash
++ */
++
++#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
++#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
++#define STM_OP_RD_STATUS 0x05 /* Read Status */
++#define STM_OP_WR_STATUS 0x01 /* Write Status */
++#define STM_OP_RD_DATA 0x03 /* Read Data */
++#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
++#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
++#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
++#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
++#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
++#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
++
++#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
++#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
++#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
++#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
++#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
++#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
++
++/*
++ * SPI Flash Interface Registers
++ */
++
++#define SPI_FLASH_CTL 0x00
++#define SPI_FLASH_OPCODE 0x04
++#define SPI_FLASH_DATA 0x08
++
++#define SPI_CTL_START 0x00000100
++#define SPI_CTL_BUSY 0x00010000
++#define SPI_CTL_TXCNT_MASK 0x0000000f
++#define SPI_CTL_RXCNT_MASK 0x000000f0
++#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
++#define SPI_CTL_SIZE_MASK 0x00060000
++
++#define SPI_CTL_CLK_SEL_MASK 0x03000000
++#define SPI_OPCODE_MASK 0x000000ff
++
++#define SPI_STATUS_WIP STM_STATUS_WIP
++
++#endif
+--- a/arch/mips/ath25/ar2315.c
++++ b/arch/mips/ath25/ar2315.c
+@@ -220,6 +220,28 @@ static struct platform_device ar2315_gpi
+ .num_resources = ARRAY_SIZE(ar2315_gpio_res)
+ };
+
++static struct resource ar2315_spiflash_res[] = {
++ {
++ .name = "spiflash_read",
++ .flags = IORESOURCE_MEM,
++ .start = AR2315_SPI_READ_BASE,
++ .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1,
++ },
++ {
++ .name = "spiflash_mmr",
++ .flags = IORESOURCE_MEM,
++ .start = AR2315_SPI_MMR_BASE,
++ .end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1,
++ },
++};
++
++static struct platform_device ar2315_spiflash = {
++ .id = 0,
++ .name = "ar2315-spiflash",
++ .resource = ar2315_spiflash_res,
++ .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
++};
++
+ void __init ar2315_init_devices(void)
+ {
+ /* Find board configuration */
+@@ -230,6 +252,8 @@ void __init ar2315_init_devices(void)
+ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
+ platform_device_register(&ar2315_gpio);
+
++ platform_device_register(&ar2315_spiflash);
++
+ ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
+ ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
+ AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
--- /dev/null
+--- /dev/null
++++ b/drivers/watchdog/ar2315-wtd.c
+@@ -0,0 +1,209 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
++ *
++ * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
++ * Based on EP93xx and ifxmips wdt driver
++ */
++
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/miscdevice.h>
++#include <linux/watchdog.h>
++#include <linux/fs.h>
++#include <linux/ioport.h>
++#include <linux/notifier.h>
++#include <linux/reboot.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/uaccess.h>
++
++#define DRIVER_NAME "ar2315-wdt"
++
++#define CLOCK_RATE 40000000
++#define HEARTBEAT(x) (x < 1 || x > 90 ? 20 : x)
++
++#define WDT_REG_TIMER 0x00
++#define WDT_REG_CTRL 0x04
++
++#define WDT_CTRL_ACT_NONE 0x00000000 /* No action */
++#define WDT_CTRL_ACT_NMI 0x00000001 /* NMI on watchdog */
++#define WDT_CTRL_ACT_RESET 0x00000002 /* reset on watchdog */
++
++static int wdt_timeout = 20;
++static int started;
++static int in_use;
++static void __iomem *wdt_base;
++
++static inline void ar2315_wdt_wr(unsigned reg, u32 val)
++{
++ iowrite32(val, wdt_base + reg);
++}
++
++static void
++ar2315_wdt_enable(void)
++{
++ ar2315_wdt_wr(WDT_REG_TIMER, wdt_timeout * CLOCK_RATE);
++}
++
++static ssize_t
++ar2315_wdt_write(struct file *file, const char __user *data, size_t len,
++ loff_t *ppos)
++{
++ if (len)
++ ar2315_wdt_enable();
++ return len;
++}
++
++static int
++ar2315_wdt_open(struct inode *inode, struct file *file)
++{
++ if (in_use)
++ return -EBUSY;
++ ar2315_wdt_enable();
++ in_use = 1;
++ started = 1;
++ return nonseekable_open(inode, file);
++}
++
++static int
++ar2315_wdt_release(struct inode *inode, struct file *file)
++{
++ in_use = 0;
++ return 0;
++}
++
++static irqreturn_t
++ar2315_wdt_interrupt(int irq, void *dev)
++{
++ struct platform_device *pdev = (struct platform_device *)dev;
++
++ if (started) {
++ dev_crit(&pdev->dev, "watchdog expired, rebooting system\n");
++ emergency_restart();
++ } else {
++ ar2315_wdt_wr(WDT_REG_CTRL, 0);
++ ar2315_wdt_wr(WDT_REG_TIMER, 0);
++ }
++ return IRQ_HANDLED;
++}
++
++static struct watchdog_info ident = {
++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
++ .identity = "ar2315 Watchdog",
++};
++
++static long
++ar2315_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ int new_wdt_timeout;
++ int ret = -ENOIOCTLCMD;
++
++ switch (cmd) {
++ case WDIOC_GETSUPPORT:
++ ret = copy_to_user((void __user *)arg, &ident, sizeof(ident)) ?
++ -EFAULT : 0;
++ break;
++ case WDIOC_KEEPALIVE:
++ ar2315_wdt_enable();
++ ret = 0;
++ break;
++ case WDIOC_SETTIMEOUT:
++ ret = get_user(new_wdt_timeout, (int __user *)arg);
++ if (ret)
++ break;
++ wdt_timeout = HEARTBEAT(new_wdt_timeout);
++ ar2315_wdt_enable();
++ break;
++ case WDIOC_GETTIMEOUT:
++ ret = put_user(wdt_timeout, (int __user *)arg);
++ break;
++ }
++ return ret;
++}
++
++static const struct file_operations ar2315_wdt_fops = {
++ .owner = THIS_MODULE,
++ .llseek = no_llseek,
++ .write = ar2315_wdt_write,
++ .unlocked_ioctl = ar2315_wdt_ioctl,
++ .open = ar2315_wdt_open,
++ .release = ar2315_wdt_release,
++};
++
++static struct miscdevice ar2315_wdt_miscdev = {
++ .minor = WATCHDOG_MINOR,
++ .name = "watchdog",
++ .fops = &ar2315_wdt_fops,
++};
++
++static int
++ar2315_wdt_probe(struct platform_device *dev)
++{
++ struct resource *mem_res, *irq_res;
++ int ret = 0;
++
++ if (wdt_base)
++ return -EBUSY;
++
++ irq_res = platform_get_resource(dev, IORESOURCE_IRQ, 0);
++ if (!irq_res) {
++ dev_err(&dev->dev, "no IRQ resource\n");
++ return -ENOENT;
++ }
++
++ mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
++ wdt_base = devm_ioremap_resource(&dev->dev, mem_res);
++ if (IS_ERR(wdt_base))
++ return PTR_ERR(wdt_base);
++
++ ret = devm_request_irq(&dev->dev, irq_res->start, ar2315_wdt_interrupt,
++ IRQF_DISABLED, DRIVER_NAME, dev);
++ if (ret) {
++ dev_err(&dev->dev, "failed to register inetrrupt\n");
++ goto out;
++ }
++
++ ret = misc_register(&ar2315_wdt_miscdev);
++ if (ret)
++ dev_err(&dev->dev, "failed to register miscdev\n");
++
++out:
++ return ret;
++}
++
++static int
++ar2315_wdt_remove(struct platform_device *dev)
++{
++ misc_deregister(&ar2315_wdt_miscdev);
++ return 0;
++}
++
++static struct platform_driver ar2315_wdt_driver = {
++ .probe = ar2315_wdt_probe,
++ .remove = ar2315_wdt_remove,
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ },
++};
++
++module_platform_driver(ar2315_wdt_driver);
++
++MODULE_DESCRIPTION("Atheros AR2315 hardware watchdog driver");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRIVER_NAME);
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -1257,6 +1257,13 @@ config RALINK_WDT
+ help
+ Hardware driver for the Ralink SoC Watchdog Timer.
+
++config AR2315_WDT
++ tristate "Atheros AR2315+ WiSoCs Watchdog Timer"
++ depends on ATH25
++ help
++ Hardware driver for the built-in watchdog timer on the Atheros
++ AR2315/AR2316 WiSoCs.
++
+ # PARISC Architecture
+
+ # POWERPC Architecture
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -138,6 +138,7 @@ obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o
+ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o
+ obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
+ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
++obj-$(CONFIG_AR2315_WDT) += ar2315-wtd.o
+ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+ obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
+ octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
+--- a/arch/mips/ath25/ar2315.c
++++ b/arch/mips/ath25/ar2315.c
+@@ -220,6 +220,24 @@ static struct platform_device ar2315_gpi
+ .num_resources = ARRAY_SIZE(ar2315_gpio_res)
+ };
+
++static struct resource ar2315_wdt_res[] = {
++ {
++ .flags = IORESOURCE_MEM,
++ .start = AR2315_RST_BASE + AR2315_WDT_TIMER,
++ .end = AR2315_RST_BASE + AR2315_WDT_TIMER + 8 - 1,
++ },
++ {
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device ar2315_wdt = {
++ .id = 0,
++ .name = "ar2315-wdt",
++ .resource = ar2315_wdt_res,
++ .num_resources = ARRAY_SIZE(ar2315_wdt_res)
++};
++
+ static struct resource ar2315_spiflash_res[] = {
+ {
+ .name = "spiflash_read",
+@@ -252,6 +270,11 @@ void __init ar2315_init_devices(void)
+ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
+ platform_device_register(&ar2315_gpio);
+
++ ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
++ AR2315_MISC_IRQ_WATCHDOG);
++ ar2315_wdt_res[1].end = ar2315_wdt_res[1].start;
++ platform_device_register(&ar2315_wdt);
++
+ platform_device_register(&ar2315_spiflash);
+
+ ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
--- /dev/null
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -30,6 +30,8 @@
+ #include <linux/mtd/partitions.h>
+ #include <linux/module.h>
+
++#define BOARD_CONFIG_PART "boardconfig"
++
+ struct fis_image_desc {
+ unsigned char name[16]; // Null terminated name
+ uint32_t flash_base; // Address within FLASH of image
+@@ -60,6 +62,7 @@ static int parse_redboot_partitions(stru
+ struct mtd_partition **pparts,
+ struct mtd_part_parser_data *data)
+ {
++ unsigned long max_offset = 0;
+ int nrparts = 0;
+ struct fis_image_desc *buf;
+ struct mtd_partition *parts;
+@@ -225,14 +228,15 @@ static int parse_redboot_partitions(stru
+ }
+ }
+ #endif
+- parts = kzalloc(sizeof(*parts)*nrparts + nulllen + namelen, GFP_KERNEL);
++ parts = kzalloc(sizeof(*parts) * (nrparts + 1) + nulllen + namelen +
++ sizeof(BOARD_CONFIG_PART), GFP_KERNEL);
+
+ if (!parts) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+- nullname = (char *)&parts[nrparts];
++ nullname = (char *)&parts[nrparts + 1];
+ #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
+ if (nulllen > 0) {
+ strcpy(nullname, nullstring);
+@@ -251,6 +255,8 @@ static int parse_redboot_partitions(stru
+ }
+ #endif
+ for ( ; i<nrparts; i++) {
++ if (max_offset < buf[i].flash_base + buf[i].size)
++ max_offset = buf[i].flash_base + buf[i].size;
+ parts[i].size = fl->img->size;
+ parts[i].offset = fl->img->flash_base;
+ parts[i].name = names;
+@@ -284,6 +290,13 @@ static int parse_redboot_partitions(stru
+ fl = fl->next;
+ kfree(tmp_fl);
+ }
++ if (master->size - max_offset >= master->erasesize) {
++ parts[nrparts].size = master->size - max_offset;
++ parts[nrparts].offset = max_offset;
++ parts[nrparts].name = names;
++ strcpy(names, BOARD_CONFIG_PART);
++ nrparts++;
++ }
+ ret = nrparts;
+ *pparts = parts;
+ out:
--- /dev/null
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -79,12 +79,18 @@ static int parse_redboot_partitions(stru
+ static char nullstring[] = "unallocated";
+ #endif
+
++ buf = vmalloc(master->erasesize);
++ if (!buf)
++ return -ENOMEM;
++
++ restart:
+ if ( directory < 0 ) {
+ offset = master->size + directory * master->erasesize;
+ while (mtd_block_isbad(master, offset)) {
+ if (!offset) {
+ nogood:
+ printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
++ vfree(buf);
+ return -EIO;
+ }
+ offset -= master->erasesize;
+@@ -97,10 +103,6 @@ static int parse_redboot_partitions(stru
+ goto nogood;
+ }
+ }
+- buf = vmalloc(master->erasesize);
+-
+- if (!buf)
+- return -ENOMEM;
+
+ printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
+ master->name, offset);
+@@ -173,6 +175,11 @@ static int parse_redboot_partitions(stru
+ }
+ if (i == numslots) {
+ /* Didn't find it */
++ if (offset + master->erasesize < master->size) {
++ /* not at the end of the flash yet, maybe next block */
++ directory++;
++ goto restart;
++ }
+ printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
+ master->name);
+ ret = 0;
--- /dev/null
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -58,6 +58,22 @@ static inline int redboot_checksum(struc
+ return 1;
+ }
+
++static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset)
++{
++ struct mtd_erase_region_info *regions = mtd->eraseregions;
++ int i;
++
++ for (i = 0; i < mtd->numeraseregions; i++) {
++ if (regions[i].offset +
++ regions[i].numblocks * regions[i].erasesize <= offset)
++ continue;
++
++ return regions[i].erasesize;
++ }
++
++ return mtd->erasesize;
++}
++
+ static int parse_redboot_partitions(struct mtd_info *master,
+ struct mtd_partition **pparts,
+ struct mtd_part_parser_data *data)
+@@ -74,6 +90,7 @@ static int parse_redboot_partitions(stru
+ int namelen = 0;
+ int nulllen = 0;
+ int numslots;
++ int first_slot;
+ unsigned long offset;
+ #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
+ static char nullstring[] = "unallocated";
+@@ -186,7 +203,10 @@ static int parse_redboot_partitions(stru
+ goto out;
+ }
+
+- for (i = 0; i < numslots; i++) {
++ first_slot = (buf[i].flash_base & (master->erasesize - 1)) /
++ sizeof(struct fis_image_desc);
++
++ for (i = first_slot; i < first_slot + numslots; i++) {
+ struct fis_list *new_fl, **prev;
+
+ if (buf[i].name[0] == 0xff) {
+@@ -262,12 +282,13 @@ static int parse_redboot_partitions(stru
+ }
+ #endif
+ for ( ; i<nrparts; i++) {
+- if (max_offset < buf[i].flash_base + buf[i].size)
+- max_offset = buf[i].flash_base + buf[i].size;
+ parts[i].size = fl->img->size;
+ parts[i].offset = fl->img->flash_base;
+ parts[i].name = names;
+
++ if (max_offset < parts[i].offset + parts[i].size)
++ max_offset = parts[i].offset + parts[i].size;
++
+ strcpy(names, fl->img->name);
+ #ifdef CONFIG_MTD_REDBOOT_PARTS_READONLY
+ if (!memcmp(names, "RedBoot", 8) ||
+@@ -297,7 +318,9 @@ static int parse_redboot_partitions(stru
+ fl = fl->next;
+ kfree(tmp_fl);
+ }
+- if (master->size - max_offset >= master->erasesize) {
++
++ if (master->size - max_offset >=
++ mtd_get_offset_erasesize(master, max_offset)) {
+ parts[nrparts].size = master->size - max_offset;
+ parts[nrparts].offset = max_offset;
+ parts[nrparts].name = names;
--- /dev/null
+--- a/arch/mips/ath25/Makefile
++++ b/arch/mips/ath25/Makefile
+@@ -8,7 +8,7 @@
+ # Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
+ #
+
+-obj-y += board.o prom.o devices.o
++obj-y += board.o prom.o devices.o reset.o
+
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+
+--- /dev/null
++++ b/arch/mips/ath25/reset.c
+@@ -0,0 +1,57 @@
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/platform_device.h>
++#include <linux/gpio_keys.h>
++#include <linux/input.h>
++#include <ath25_platform.h>
++#include "devices.h"
++
++static int __init
++ar231x_init_reset(void)
++{
++ struct platform_device *pdev;
++ struct gpio_keys_platform_data pdata;
++ struct gpio_keys_button *p;
++ int err;
++
++ if (ath25_board.config->reset_config_gpio == 0xffff)
++ return -ENODEV;
++
++ p = kzalloc(sizeof(*p), GFP_KERNEL);
++ if (!p)
++ goto err;
++
++ p->desc = "reset";
++ p->type = EV_KEY;
++ p->code = KEY_RESTART;
++ p->debounce_interval = 60;
++ p->gpio = ath25_board.config->reset_config_gpio;
++
++ memset(&pdata, 0, sizeof(pdata));
++ pdata.poll_interval = 20;
++ pdata.buttons = p;
++ pdata.nbuttons = 1;
++
++ pdev = platform_device_alloc("gpio-keys-polled", 0);
++ if (!pdev)
++ goto err_free;
++
++ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
++ if (err)
++ goto err_put_pdev;
++
++ err = platform_device_add(pdev);
++ if (err)
++ goto err_put_pdev;
++
++ return 0;
++
++err_put_pdev:
++ platform_device_put(pdev);
++err_free:
++ kfree(p);
++err:
++ return -ENOMEM;
++}
++
++module_init(ar231x_init_reset);
--- /dev/null
+--- a/drivers/net/ethernet/atheros/ar231x/ar231x.c
++++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
+@@ -135,6 +135,7 @@ static int ar231x_mdiobus_write(struct m
+ static int ar231x_mdiobus_reset(struct mii_bus *bus);
+ static int ar231x_mdiobus_probe(struct net_device *dev);
+ static void ar231x_adjust_link(struct net_device *dev);
++static bool no_phy;
+
+ #ifndef ERR
+ #define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
+@@ -167,6 +168,32 @@ static const struct net_device_ops ar231
+ #endif
+ };
+
++static int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id)
++{
++ int phy_reg;
++
++ /**
++ * Grab the bits from PHYIR1, and put them
++ * in the upper half.
++ */
++ phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
++
++ if (phy_reg < 0)
++ return -EIO;
++
++ *phy_id = (phy_reg & 0xffff) << 16;
++
++ /* Grab the bits from PHYIR2, and put them in the lower half */
++ phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
++
++ if (phy_reg < 0)
++ return -EIO;
++
++ *phy_id |= (phy_reg & 0xffff);
++
++ return 0;
++}
++
+ static int ar231x_probe(struct platform_device *pdev)
+ {
+ struct net_device *dev;
+@@ -273,6 +300,24 @@ static int ar231x_probe(struct platform_
+
+ mdiobus_register(sp->mii_bus);
+
++ /**
++ * Workaround for Micrel switch, which is only available on
++ * one PHY and cannot be configured through MDIO.
++ */
++ if (!no_phy) {
++ u32 phy_id = 0;
++
++ get_phy_id(sp->mii_bus, 1, &phy_id);
++ if (phy_id == 0x00221450)
++ no_phy = true;
++ }
++ if (no_phy) {
++ sp->link = 1;
++ netif_carrier_on(dev);
++ return 0;
++ }
++ no_phy = true;
++
+ if (ar231x_mdiobus_probe(dev) != 0) {
+ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
+ rx_tasklet_cleanup(dev);
+@@ -329,8 +374,10 @@ static int ar231x_remove(struct platform
+ rx_tasklet_cleanup(dev);
+ ar231x_init_cleanup(dev);
+ unregister_netdev(dev);
+- mdiobus_unregister(sp->mii_bus);
+- mdiobus_free(sp->mii_bus);
++ if (sp->mii_bus) {
++ mdiobus_unregister(sp->mii_bus);
++ mdiobus_free(sp->mii_bus);
++ }
+ kfree(dev);
+ return 0;
+ }
+@@ -1079,6 +1126,9 @@ static int ar231x_ioctl(struct net_devic
+ {
+ struct ar231x_private *sp = netdev_priv(dev);
+
++ if (!sp->phy_dev)
++ return -ENODEV;
++
+ switch (cmd) {
+ case SIOCGMIIPHY:
+ case SIOCGMIIREG:
--- /dev/null
+--- a/arch/mips/ath25/ar2315.c
++++ b/arch/mips/ath25/ar2315.c
+@@ -23,6 +23,7 @@
+ #include <linux/reboot.h>
+ #include <linux/delay.h>
+ #include <linux/gpio.h>
++#include <linux/leds.h>
+ #include <asm/bootinfo.h>
+ #include <asm/reboot.h>
+ #include <asm/time.h>
+@@ -260,6 +261,50 @@ static struct platform_device ar2315_spi
+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
+ };
+
++#ifdef CONFIG_LEDS_GPIO
++static struct gpio_led ar2315_leds[6];
++static struct gpio_led_platform_data ar2315_led_data = {
++ .leds = (void *)ar2315_leds,
++};
++
++static struct platform_device ar2315_gpio_leds = {
++ .name = "leds-gpio",
++ .id = -1,
++ .dev = {
++ .platform_data = (void *)&ar2315_led_data,
++ }
++};
++
++static void __init ar2315_init_gpio_leds(void)
++{
++ static char led_names[6][6];
++ int i, led = 0;
++
++ ar2315_led_data.num_leds = 0;
++ for (i = 1; i < 8; i++) {
++ if ((i == AR2315_RESET_GPIO) ||
++ (i == ath25_board.config->reset_config_gpio))
++ continue;
++
++ if (i == ath25_board.config->sys_led_gpio)
++ strcpy(led_names[led], "wlan");
++ else
++ sprintf(led_names[led], "gpio%d", i);
++
++ ar2315_leds[led].name = led_names[led];
++ ar2315_leds[led].gpio = i;
++ ar2315_leds[led].active_low = 0;
++ led++;
++ }
++ ar2315_led_data.num_leds = led;
++ platform_device_register(&ar2315_gpio_leds);
++}
++#else
++static inline void ar2315_init_gpio_leds(void)
++{
++}
++#endif
++
+ void __init ar2315_init_devices(void)
+ {
+ /* Find board configuration */
+@@ -270,6 +315,8 @@ void __init ar2315_init_devices(void)
+ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
+ platform_device_register(&ar2315_gpio);
+
++ ar2315_init_gpio_leds();
++
+ ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
+ AR2315_MISC_IRQ_WATCHDOG);
+ ar2315_wdt_res[1].end = ar2315_wdt_res[1].start;
+--- a/arch/mips/ath25/ar5312.c
++++ b/arch/mips/ath25/ar5312.c
+@@ -23,6 +23,7 @@
+ #include <linux/mtd/physmap.h>
+ #include <linux/reboot.h>
+ #include <linux/gpio.h>
++#include <linux/leds.h>
+ #include <asm/bootinfo.h>
+ #include <asm/reboot.h>
+ #include <asm/time.h>
+@@ -231,6 +232,23 @@ static struct platform_device ar5312_gpi
+ .num_resources = ARRAY_SIZE(ar5312_gpio_res),
+ };
+
++#ifdef CONFIG_LEDS_GPIO
++static struct gpio_led ar5312_leds[] = {
++ { .name = "wlan", .gpio = 0, .active_low = 1, },
++};
++
++static const struct gpio_led_platform_data ar5312_led_data = {
++ .num_leds = ARRAY_SIZE(ar5312_leds),
++ .leds = (void *)ar5312_leds,
++};
++
++static struct platform_device ar5312_gpio_leds = {
++ .name = "leds-gpio",
++ .id = -1,
++ .dev.platform_data = (void *)&ar5312_led_data,
++};
++#endif
++
+ static void __init ar5312_flash_init(void)
+ {
+ void __iomem *flashctl_base;
+@@ -301,6 +319,11 @@ void __init ar5312_init_devices(void)
+
+ platform_device_register(&ar5312_gpio);
+
++#ifdef CONFIG_LEDS_GPIO
++ ar5312_leds[0].gpio = config->sys_led_gpio;
++ platform_device_register(&ar5312_gpio_leds);
++#endif
++
+ /* Fix up MAC addresses if necessary */
+ if (is_broadcast_ether_addr(config->enet0_mac))
+ ether_addr_copy(config->enet0_mac, config->enet1_mac);
+++ /dev/null
-#
-# Copyright (C) 2006-2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=mips
-BOARD:=atheros
-BOARDNAME:=Atheros AR231x/AR5312
-FEATURES:=squashfs low_mem
-
-KERNEL_PATCHVER:=3.18
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES += wpad-mini kmod-ath5k swconfig kmod-gpio-button-hotplug
-
-define Target/Description
- Build firmware images for Atheros SoC boards
-endef
-
-$(eval $(call BuildTarget))
+++ /dev/null
-config system
- option hostname OpenWrt
- option timezone UTC
-
-config timeserver ntp
- list server 0.openwrt.pool.ntp.org
- list server 1.openwrt.pool.ntp.org
- list server 2.openwrt.pool.ntp.org
- list server 3.openwrt.pool.ntp.org
-
-config button
- option button reset
- option action released
- option handler "logger reboot"
- option min 0
- option max 4
-
-config button
- option button reset
- option action released
- option handler "logger factory default"
- option min 5
- option max 30
+++ /dev/null
-. /lib/functions.sh
-do_button () {
- local button
- local action
- local handler
- local min
- local max
-
- config_get button $1 button
- config_get action $1 action
- config_get handler $1 handler
- config_get min $1 min
- config_get max $1 max
-
- [ "$ACTION" = "$action" -a "$BUTTON" = "$button" -a -n "$handler" ] && {
- [ -z "$min" -o -z "$max" ] && eval $handler
- [ -n "$min" -a -n "$max" ] && {
- [ $min -le $SEEN -a $max -ge $SEEN ] && eval $handler
- }
- }
-}
-
-config_load system
-config_foreach do_button button
+++ /dev/null
-#!/bin/sh
-# Copyright 2012 OpenWrt.org
-#
-
-. /lib/functions/uci-defaults.sh
-
-ucidef_set_led_netdev "wlan" "wlan" "wlan" "wlan0"
-
-ucidef_commit_leds
-
-exit 0
+++ /dev/null
-#!/bin/sh
-if [ -e "/sys/bus/mdio_bus/drivers/IC+ IP175C/0:00" -o \
- -e "/sys/bus/mdio_bus/drivers/IC+ IP17xx/0:00" ] && \
- [ -x /sbin/swconfig ];
-then
- uci batch <<EOF
-set network.eth0=switch
-set network.eth0.name=eth0
-set network.eth0.reset=1
-set network.eth0.enable_vlan=1
-set network.eth0_1=switch_vlan
-set network.eth0_1.device=eth0
-set network.eth0_1.vlan=1
-set network.eth0_1.ports="0 1 2 3 5t"
-set network.eth0_2=switch_vlan
-set network.eth0_2.device=eth0
-set network.eth0_2.vlan=2
-set network.eth0_2.ports="4 5t"
-EOF
- HAS_SWITCH=1
-fi
-
-if [ -n "$HAS_SWITCH" -o \
- -e "/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00" -o \
- -e "/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10" ]; then
- uci batch <<EOF
-set network.lan.ifname=eth0.1
-set network.wan=interface
-set network.wan.ifname=eth0.2
-set network.wan.proto=dhcp
-commit network
-EOF
- HAS_SWITCH=1
-fi
-
-[ -z "$HAS_SWITCH" -a -d /sys/class/net/eth1 ] && {
- uci batch <<EOF
-set network.wan=interface
-set network.wan.ifname=eth1
-set network.wan.proto=dhcp
-commit network
-EOF
-}
-
-uci commit network
+++ /dev/null
-#!/bin/sh
-
-# reset button only supported on ar5315+ at the moment
-preinit_ip() {
- if [ -z "$pi_ifname" ]; then
- grep -q 'Atheros AR231[567]' /proc/cpuinfo && {
- if [ -e "/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00" -o \
- -e "/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10" ]; then
- vconfig set_name_type DEV_PLUS_VID_NO_PAD
- ifconfig eth0 up
- vconfig add eth0 1
- ifname=eth0.1
- else
- ifname=eth0
- fi
- pi_ifname=$ifname
- }
- fi
- [ -n "$pi_ifname" ] && grep -q "$pi_ifname" /proc/net/dev && {
- ifconfig $pi_ifname $pi_ip netmask $pi_netmask broadcast $pi_broadcast up
- }
-}
-
-
-# reset button only supported on ar5315+ at the moment
-
-preinit_ip_deconfig() {
- if [ -e "/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00" -o \
- -e "/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10" ]; then
- vconfig rem eth0.1 2>/dev/null
- ifconfig $pi_ifname down
- elif [ -n "$pi_ifname" ]; then
- ifconfig $pi_ifname 0.0.0.0
- fi
-}
+++ /dev/null
-CI_BLKSZ=65536
-CI_LDADR=0x80041000
-
-platform_find_partitions() {
- local first dev size erasesize name
- while read dev size erasesize name; do
- name=${name#'"'}; name=${name%'"'}
- case "$name" in
- vmlinux.bin.l7|kernel|linux|rootfs)
- if [ -z "$first" ]; then
- first="$name"
- else
- echo "$erasesize:$first:$name"
- break
- fi
- ;;
- esac
- done < /proc/mtd
-}
-
-platform_find_kernelpart() {
- local part
- for part in "${1%:*}" "${1#*:}"; do
- case "$part" in
- vmlinux.bin.l7|kernel|linux)
- echo "$part"
- break
- ;;
- esac
- done
-}
-
-platform_check_image() {
- [ "$#" -gt 1 ] && return 1
-
- case "$(get_magic_word "$1")" in
- # Combined Image
- 4349)
- local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null)
- local md5_chk=$(dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}"
-
- if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then
- return 0
- else
- echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)"
- return 1
- fi
- ;;
- *)
- echo "Invalid image. Use combined .img files on this platform"
- return 1
- ;;
- esac
-}
-
-platform_do_upgrade() {
- local partitions=$(platform_find_partitions)
- local kernelpart=$(platform_find_kernelpart "${partitions#*:}")
- local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}"
- local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null)
- local kern_blocks=$(($kern_length / $CI_BLKSZ))
- local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ))
-
- if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \
- [ ${kern_blocks:-0} -gt 0 ] && \
- [ ${root_blocks:-0} -gt ${kern_blocks:-0} ] && \
- [ ${erase_size:-0} -gt 0 ];
- then
- local append=""
- [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR"
-
- ( dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null; \
- dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null ) | \
- mtd -r $append -F$kernelpart:$kern_length:$CI_LDADR,rootfs write - $partitions
- fi
-}
+++ /dev/null
-CONFIG_ADM6996_PHY=y
-CONFIG_AR2315_WDT=y
-CONFIG_AR8216_PHY=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-# CONFIG_ARCH_HAS_SG_CHAIN is not set
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ATH25=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-CONFIG_CPU_MIPSR1=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_AR2315=y
-CONFIG_GPIO_AR5312=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IP17XX_PHY=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_LEDS_GPIO=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_AR2315=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_MYLOADER_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MVSWITCH_PHY=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_AR231X=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-# CONFIG_NO_IOPORT_MAP is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_AR2315=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_RCU_STALL_COMMON is not set
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SOC_AR2315=y
-CONFIG_SOC_AR5312=y
-# CONFIG_SWAP is not set
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_USB_SUPPORT=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2006-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/BuildKernel
- cp $(KDIR)/vmlinux.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.elf
- gzip -9 -c $(KDIR)/vmlinux > $(KDIR)/vmlinux.bin.gz
- $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.bin.l7
- dd if=$(KDIR)/vmlinux.bin.l7 of=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma bs=65536 conv=sync
- dd if=$(KDIR)/vmlinux.bin.gz of=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.gz bs=65536 conv=sync
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
-endef
-
-define Image/Build
- $(call Image/Build/$(1))
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync
-
- -$(STAGING_DIR_HOST)/bin/mkfwimage \
- -B XS2 -v XS2.ar2316.OpenWrt.$(REVISION) \
- -k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \
- -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
- -o $(BIN_DIR)/$(IMG_PREFIX)-ubnt2-$(1).bin
-
- -$(STAGING_DIR_HOST)/bin/mkfwimage \
- -B XS5 -v XS5.ar2313.OpenWrt.$(REVISION) \
- -k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \
- -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
- -o $(BIN_DIR)/$(IMG_PREFIX)-ubnt5-$(1).bin
-
- -$(STAGING_DIR_HOST)/bin/mkfwimage \
- -B XS2-8 -v XS2.ar2316.OpenWrt.$(REVISION) \
- -k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \
- -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
- -o $(BIN_DIR)/$(IMG_PREFIX)-ubnt2-pico2-$(1).bin
-
- -$(STAGING_DIR_HOST)/bin/mkmylofw -B np25g \
- -p0x020000:0x130000:ah:0x80041000:linux:$(KDIR)/vmlinux.bin.gz \
- -p0x150000:0x2a0000:::rootfs:$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
- $(BIN_DIR)/$(IMG_PREFIX)-np25g-$(1).bin
-
- -$(STAGING_DIR_HOST)/bin/mkmylofw -B wpe53g \
- -p0x020000:0x130000:ah:0x80041000:linux:$(KDIR)/vmlinux.bin.gz \
- -p0x150000:0x2a0000:::rootfs:$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
- $(BIN_DIR)/$(IMG_PREFIX)-wpe53g-$(1).bin
-
- -sh $(TOPDIR)/scripts/combined-image.sh \
- "$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma" \
- "$(BIN_DIR)/$(IMG_PREFIX)-root.$(1)" \
- "$(BIN_DIR)/$(IMG_PREFIX)-combined.$(1).img"
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -96,6 +96,19 @@ config AR7
- Support for the Texas Instruments AR7 System-on-a-Chip
- family: TNETD7100, 7200 and 7300.
-
-+config ATH25
-+ bool "Atheros AR231x/AR531x SoC support"
-+ select CEVT_R4K
-+ select CSRC_R4K
-+ select DMA_NONCOHERENT
-+ select IRQ_CPU
-+ select IRQ_DOMAIN
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ help
-+ Support for Atheros AR231x and Atheros AR531x based boards
-+
- config ATH79
- bool "Atheros AR71XX/AR724X/AR913X based boards"
- select ARCH_REQUIRE_GPIOLIB
-@@ -835,6 +848,7 @@ config MIPS_PARAVIRT
- endchoice
-
- source "arch/mips/alchemy/Kconfig"
-+source "arch/mips/ath25/Kconfig"
- source "arch/mips/ath79/Kconfig"
- source "arch/mips/bcm47xx/Kconfig"
- source "arch/mips/bcm63xx/Kconfig"
---- a/arch/mips/Kbuild.platforms
-+++ b/arch/mips/Kbuild.platforms
-@@ -2,6 +2,7 @@
-
- platforms += alchemy
- platforms += ar7
-+platforms += ath25
- platforms += ath79
- platforms += bcm47xx
- platforms += bcm63xx
---- /dev/null
-+++ b/arch/mips/ath25/Platform
-@@ -0,0 +1,6 @@
-+#
-+# Atheros AR531X/AR231X WiSoC
-+#
-+platform-$(CONFIG_ATH25) += ath25/
-+cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
-+load-$(CONFIG_ATH25) += 0xffffffff80041000
---- /dev/null
-+++ b/arch/mips/ath25/Kconfig
-@@ -0,0 +1,9 @@
-+config SOC_AR5312
-+ bool "Atheros AR5312/AR2312+ SoC support"
-+ depends on ATH25
-+ default y
-+
-+config SOC_AR2315
-+ bool "Atheros AR2315+ SoC support"
-+ depends on ATH25
-+ default y
---- /dev/null
-+++ b/arch/mips/ath25/Makefile
-@@ -0,0 +1,13 @@
-+#
-+# This file is subject to the terms and conditions of the GNU General Public
-+# License. See the file "COPYING" in the main directory of this archive
-+# for more details.
-+#
-+# Copyright (C) 2006 FON Technology, SL.
-+# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
-+#
-+
-+obj-y += board.o prom.o devices.o
-+obj-$(CONFIG_SOC_AR5312) += ar5312.o
-+obj-$(CONFIG_SOC_AR2315) += ar2315.o
---- /dev/null
-+++ b/arch/mips/ath25/board.c
-@@ -0,0 +1,234 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
-+ * Copyright (C) 2006 FON Technology, SL.
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <asm/irq_cpu.h>
-+#include <asm/reboot.h>
-+#include <asm/bootinfo.h>
-+#include <asm/time.h>
-+
-+#include <ath25_platform.h>
-+#include "devices.h"
-+#include "ar5312.h"
-+#include "ar2315.h"
-+
-+void (*ath25_irq_dispatch)(void);
-+
-+static inline bool check_radio_magic(const void __iomem *addr)
-+{
-+ addr += 0x7a; /* offset for flash magic */
-+ return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
-+}
-+
-+static inline bool check_notempty(const void __iomem *addr)
-+{
-+ return __raw_readl(addr) != 0xffffffff;
-+}
-+
-+static inline bool check_board_data(const void __iomem *addr, bool broken)
-+{
-+ /* config magic found */
-+ if (__raw_readl(addr) == ATH25_BD_MAGIC)
-+ return true;
-+
-+ if (!broken)
-+ return false;
-+
-+ /* broken board data detected, use radio data to find the
-+ * offset, user will fix this */
-+
-+ if (check_radio_magic(addr + 0x1000))
-+ return true;
-+ if (check_radio_magic(addr + 0xf8))
-+ return true;
-+
-+ return false;
-+}
-+
-+static const void __iomem * __init find_board_config(const void __iomem *limit,
-+ const bool broken)
-+{
-+ const void __iomem *addr;
-+ const void __iomem *begin = limit - 0x1000;
-+ const void __iomem *end = limit - 0x30000;
-+
-+ for (addr = begin; addr >= end; addr -= 0x1000)
-+ if (check_board_data(addr, broken))
-+ return addr;
-+
-+ return NULL;
-+}
-+
-+static const void __iomem * __init find_radio_config(const void __iomem *limit,
-+ const void __iomem *bcfg)
-+{
-+ const void __iomem *rcfg, *begin, *end;
-+
-+ /*
-+ * Now find the start of Radio Configuration data, using heuristics:
-+ * Search forward from Board Configuration data by 0x1000 bytes
-+ * at a time until we find non-0xffffffff.
-+ */
-+ begin = bcfg + 0x1000;
-+ end = limit;
-+ for (rcfg = begin; rcfg < end; rcfg += 0x1000)
-+ if (check_notempty(rcfg) && check_radio_magic(rcfg))
-+ return rcfg;
-+
-+ /* AR2316 relocates radio config to new location */
-+ begin = bcfg + 0xf8;
-+ end = limit - 0x1000 + 0xf8;
-+ for (rcfg = begin; rcfg < end; rcfg += 0x1000)
-+ if (check_notempty(rcfg) && check_radio_magic(rcfg))
-+ return rcfg;
-+
-+ return NULL;
-+}
-+
-+/*
-+ * NB: Search region size could be larger than the actual flash size,
-+ * but this shouldn't be a problem here, because the flash
-+ * will simply be mapped multiple times.
-+ */
-+int __init ath25_find_config(phys_addr_t base, unsigned long size)
-+{
-+ const void __iomem *flash_base, *flash_limit;
-+ struct ath25_boarddata *config;
-+ unsigned int rcfg_size;
-+ int broken_boarddata = 0;
-+ const void __iomem *bcfg, *rcfg;
-+ u8 *board_data;
-+ u8 *radio_data;
-+ u8 *mac_addr;
-+ u32 offset;
-+
-+ flash_base = ioremap_nocache(base, size);
-+ flash_limit = flash_base + size;
-+
-+ ath25_board.config = NULL;
-+ ath25_board.radio = NULL;
-+
-+ /* Copy the board and radio data to RAM, because accessing the mapped
-+ * memory of the flash directly after booting is not safe */
-+
-+ /* Try to find valid board and radio data */
-+ bcfg = find_board_config(flash_limit, false);
-+
-+ /* If that fails, try to at least find valid radio data */
-+ if (!bcfg) {
-+ bcfg = find_board_config(flash_limit, true);
-+ broken_boarddata = 1;
-+ }
-+
-+ if (!bcfg) {
-+ pr_warn("WARNING: No board configuration data found!\n");
-+ goto error;
-+ }
-+
-+ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
-+ ath25_board.config = (struct ath25_boarddata *)board_data;
-+ memcpy_fromio(board_data, bcfg, 0x100);
-+ if (broken_boarddata) {
-+ pr_warn("WARNING: broken board data detected\n");
-+ config = ath25_board.config;
-+ if (is_zero_ether_addr(config->enet0_mac)) {
-+ pr_info("Fixing up empty mac addresses\n");
-+ config->reset_config_gpio = 0xffff;
-+ config->sys_led_gpio = 0xffff;
-+ random_ether_addr(config->wlan0_mac);
-+ config->wlan0_mac[0] &= ~0x06;
-+ random_ether_addr(config->enet0_mac);
-+ random_ether_addr(config->enet1_mac);
-+ }
-+ }
-+
-+ /* Radio config starts 0x100 bytes after board config, regardless
-+ * of what the physical layout on the flash chip looks like */
-+
-+ rcfg = find_radio_config(flash_limit, bcfg);
-+ if (!rcfg) {
-+ pr_warn("WARNING: Could not find Radio Configuration data\n");
-+ goto error;
-+ }
-+
-+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
-+ ath25_board.radio = radio_data;
-+ offset = radio_data - board_data;
-+ pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
-+ offset);
-+ rcfg_size = BOARD_CONFIG_BUFSZ - offset;
-+ memcpy_fromio(radio_data, rcfg, rcfg_size);
-+
-+ mac_addr = &radio_data[0x1d * 2];
-+ if (is_broadcast_ether_addr(mac_addr)) {
-+ pr_info("Radio MAC is blank; using board-data\n");
-+ ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
-+ }
-+
-+ iounmap(flash_base);
-+
-+ return 0;
-+
-+error:
-+ iounmap(flash_base);
-+ return -ENODEV;
-+}
-+
-+static void ath25_halt(void)
-+{
-+ local_irq_disable();
-+ unreachable();
-+}
-+
-+void __init plat_mem_setup(void)
-+{
-+ _machine_halt = ath25_halt;
-+ pm_power_off = ath25_halt;
-+
-+ if (is_ar5312())
-+ ar5312_plat_mem_setup();
-+ else
-+ ar2315_plat_mem_setup();
-+
-+ /* Disable data watchpoints */
-+ write_c0_watchlo0(0);
-+}
-+
-+asmlinkage void plat_irq_dispatch(void)
-+{
-+ ath25_irq_dispatch();
-+}
-+
-+void __init plat_time_init(void)
-+{
-+ if (is_ar5312())
-+ ar5312_plat_time_init();
-+ else
-+ ar2315_plat_time_init();
-+}
-+
-+unsigned int __cpuinit get_c0_compare_int(void)
-+{
-+ return CP0_LEGACY_COMPARE_IRQ;
-+}
-+
-+void __init arch_init_irq(void)
-+{
-+ clear_c0_status(ST0_IM);
-+ mips_cpu_irq_init();
-+
-+ /* Initialize interrupt controllers */
-+ if (is_ar5312())
-+ ar5312_arch_init_irq();
-+ else
-+ ar2315_arch_init_irq();
-+}
---- /dev/null
-+++ b/arch/mips/ath25/prom.c
-@@ -0,0 +1,26 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright MontaVista Software Inc
-+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
-+ * Copyright (C) 2006 FON Technology, SL.
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-+ */
-+
-+/*
-+ * Prom setup file for AR5312/AR231x SoCs
-+ */
-+
-+#include <linux/init.h>
-+#include <asm/bootinfo.h>
-+
-+void __init prom_init(void)
-+{
-+}
-+
-+void __init prom_free_prom_memory(void)
-+{
-+}
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
-@@ -0,0 +1,73 @@
-+#ifndef __ASM_MACH_ATH25_PLATFORM_H
-+#define __ASM_MACH_ATH25_PLATFORM_H
-+
-+#include <linux/etherdevice.h>
-+
-+/*
-+ * This is board-specific data that is stored in a "fixed" location in flash.
-+ * It is shared across operating systems, so it should not be changed lightly.
-+ * The main reason we need it is in order to extract the ethernet MAC
-+ * address(es).
-+ */
-+struct ath25_boarddata {
-+ u32 magic; /* board data is valid */
-+#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
-+ u16 cksum; /* checksum (starting with BD_REV 2) */
-+ u16 rev; /* revision of this struct */
-+#define BD_REV 4
-+ char board_name[64]; /* Name of board */
-+ u16 major; /* Board major number */
-+ u16 minor; /* Board minor number */
-+ u32 flags; /* Board configuration */
-+#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
-+#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
-+#define BD_UART1 0x00000004 /* UART1 is stuffed */
-+#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
-+#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
-+#define BD_SYSLED 0x00000020 /* System LED stuffed */
-+#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
-+#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
-+#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
-+#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
-+#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
-+#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
-+#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
-+#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
-+#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
-+#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
-+#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
-+#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
-+ u16 reset_config_gpio; /* Reset factory GPIO pin */
-+ u16 sys_led_gpio; /* System LED GPIO pin */
-+
-+ u32 cpu_freq; /* CPU core frequency in Hz */
-+ u32 sys_freq; /* System frequency in Hz */
-+ u32 cnt_freq; /* Calculated C0_COUNT frequency */
-+
-+ u8 wlan0_mac[ETH_ALEN];
-+ u8 enet0_mac[ETH_ALEN];
-+ u8 enet1_mac[ETH_ALEN];
-+
-+ u16 pci_id; /* Pseudo PCIID for common code */
-+ u16 mem_cap; /* cap bank1 in MB */
-+
-+ /* version 3 */
-+ u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
-+};
-+
-+#define BOARD_CONFIG_BUFSZ 0x1000
-+
-+/*
-+ * Platform device information for the Wireless MAC
-+ */
-+struct ar231x_board_config {
-+ u16 devid;
-+
-+ /* board config data */
-+ struct ath25_boarddata *config;
-+
-+ /* radio calibration data */
-+ const char *radio;
-+};
-+
-+#endif /* __ASM_MACH_ATH25_PLATFORM_H */
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
-@@ -0,0 +1,64 @@
-+/*
-+ * Atheros AR231x/AR531x SoC specific CPU feature overrides
-+ *
-+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * This file was derived from: include/asm-mips/cpu-features.h
-+ * Copyright (C) 2003, 2004 Ralf Baechle
-+ * Copyright (C) 2004 Maciej W. Rozycki
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ */
-+#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
-+#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
-+
-+/*
-+ * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
-+ */
-+#define cpu_has_tlb 1
-+#define cpu_has_4kex 1
-+#define cpu_has_3k_cache 0
-+#define cpu_has_4k_cache 1
-+#define cpu_has_tx39_cache 0
-+#define cpu_has_sb1_cache 0
-+#define cpu_has_fpu 0
-+#define cpu_has_32fpr 0
-+#define cpu_has_counter 1
-+#define cpu_has_ejtag 1
-+
-+#if !defined(CONFIG_SOC_AR5312)
-+# define cpu_has_llsc 1
-+#else
-+/*
-+ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
-+ * ll/sc instructions.
-+ */
-+# define cpu_has_llsc 0
-+#endif
-+
-+#define cpu_has_mips16 0
-+#define cpu_has_mdmx 0
-+#define cpu_has_mips3d 0
-+#define cpu_has_smartmips 0
-+
-+#define cpu_has_mips32r1 1
-+
-+#if !defined(CONFIG_SOC_AR5312)
-+# define cpu_has_mips32r2 1
-+#endif
-+
-+#define cpu_has_mips64r1 0
-+#define cpu_has_mips64r2 0
-+
-+#define cpu_has_dsp 0
-+#define cpu_has_mipsmt 0
-+
-+#define cpu_has_64bits 0
-+#define cpu_has_64bit_zero_reg 0
-+#define cpu_has_64bit_gp_regs 0
-+#define cpu_has_64bit_addresses 0
-+
-+#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
-@@ -0,0 +1,82 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
-+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
-+ *
-+ */
-+#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
-+#define __ASM_MACH_ATH25_DMA_COHERENCE_H
-+
-+#include <linux/device.h>
-+
-+/*
-+ * We need some arbitrary non-zero value to be programmed to the BAR1 register
-+ * of PCI host controller to enable DMA. The same value should be used as the
-+ * offset to calculate the physical address of DMA buffer for PCI devices.
-+ */
-+#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
-+
-+static inline dma_addr_t ath25_dev_offset(struct device *dev)
-+{
-+#ifdef CONFIG_PCI
-+ extern struct bus_type pci_bus_type;
-+
-+ if (dev && dev->bus == &pci_bus_type)
-+ return AR2315_PCI_HOST_SDRAM_BASEADDR;
-+#endif
-+ return 0;
-+}
-+
-+static inline dma_addr_t
-+plat_map_dma_mem(struct device *dev, void *addr, size_t size)
-+{
-+ return virt_to_phys(addr) + ath25_dev_offset(dev);
-+}
-+
-+static inline dma_addr_t
-+plat_map_dma_mem_page(struct device *dev, struct page *page)
-+{
-+ return page_to_phys(page) + ath25_dev_offset(dev);
-+}
-+
-+static inline unsigned long
-+plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
-+{
-+ return dma_addr - ath25_dev_offset(dev);
-+}
-+
-+static inline void
-+plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
-+ enum dma_data_direction direction)
-+{
-+}
-+
-+static inline int plat_dma_supported(struct device *dev, u64 mask)
-+{
-+ return 1;
-+}
-+
-+static inline void plat_extra_sync_for_device(struct device *dev)
-+{
-+}
-+
-+static inline int plat_dma_mapping_error(struct device *dev,
-+ dma_addr_t dma_addr)
-+{
-+ return 0;
-+}
-+
-+static inline int plat_device_is_coherent(struct device *dev)
-+{
-+#ifdef CONFIG_DMA_COHERENT
-+ return 1;
-+#endif
-+#ifdef CONFIG_DMA_NONCOHERENT
-+ return 0;
-+#endif
-+}
-+
-+#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath25/gpio.h
-@@ -0,0 +1,16 @@
-+#ifndef __ASM_MACH_ATH25_GPIO_H
-+#define __ASM_MACH_ATH25_GPIO_H
-+
-+#include <asm-generic/gpio.h>
-+
-+#define gpio_get_value __gpio_get_value
-+#define gpio_set_value __gpio_set_value
-+#define gpio_cansleep __gpio_cansleep
-+#define gpio_to_irq __gpio_to_irq
-+
-+static inline int irq_to_gpio(unsigned irq)
-+{
-+ return -EINVAL;
-+}
-+
-+#endif /* __ASM_MACH_ATH25_GPIO_H */
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath25/war.h
-@@ -0,0 +1,25 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
-+ */
-+#ifndef __ASM_MACH_ATH25_WAR_H
-+#define __ASM_MACH_ATH25_WAR_H
-+
-+#define R4600_V1_INDEX_ICACHEOP_WAR 0
-+#define R4600_V1_HIT_CACHEOP_WAR 0
-+#define R4600_V2_HIT_CACHEOP_WAR 0
-+#define R5432_CP0_INTERRUPT_WAR 0
-+#define BCM1250_M3_WAR 0
-+#define SIBYTE_1956_WAR 0
-+#define MIPS4K_ICACHE_REFILL_WAR 0
-+#define MIPS_CACHE_SYNC_WAR 0
-+#define TX49XX_ICACHE_INDEX_INV_WAR 0
-+#define RM9000_CDEX_SMP_WAR 0
-+#define ICACHE_REFILLS_WORKAROUND_WAR 0
-+#define R10000_LLSC_WAR 0
-+#define MIPS34K_MISSED_ITLB_WAR 0
-+
-+#endif /* __ASM_MACH_ATH25_WAR_H */
---- /dev/null
-+++ b/arch/mips/ath25/ar2315_regs.h
-@@ -0,0 +1,410 @@
-+/*
-+ * Register definitions for AR2315+
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
-+ * Copyright (C) 2006 FON Technology, SL.
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
-+ */
-+
-+#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
-+#define __ASM_MACH_ATH25_AR2315_REGS_H
-+
-+/*
-+ * IRQs
-+ */
-+#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
-+#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
-+#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
-+#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
-+#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
-+
-+/*
-+ * Miscellaneous interrupts, which share IP2.
-+ */
-+#define AR2315_MISC_IRQ_UART0 0
-+#define AR2315_MISC_IRQ_I2C_RSVD 1
-+#define AR2315_MISC_IRQ_SPI 2
-+#define AR2315_MISC_IRQ_AHB 3
-+#define AR2315_MISC_IRQ_APB 4
-+#define AR2315_MISC_IRQ_TIMER 5
-+#define AR2315_MISC_IRQ_GPIO 6
-+#define AR2315_MISC_IRQ_WATCHDOG 7
-+#define AR2315_MISC_IRQ_IR_RSVD 8
-+#define AR2315_MISC_IRQ_COUNT 9
-+
-+/*
-+ * Address map
-+ */
-+#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
-+#define AR2315_SPI_READ_SIZE 0x01000000
-+#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
-+#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
-+#define AR2315_PCI_SIZE 0x00001000
-+#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
-+#define AR2315_SDRAMCTL_SIZE 0x00000020
-+#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
-+#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
-+#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
-+#define AR2315_RST_SIZE 0x00000100
-+#define AR2315_UART0_BASE 0x11100000 /* UART MMR */
-+#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
-+#define AR2315_SPI_MMR_SIZE 0x00000010
-+#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
-+#define AR2315_PCI_EXT_SIZE 0x40000000
-+
-+/*
-+ * Configuration registers
-+ */
-+
-+/* Cold reset register */
-+#define AR2315_COLD_RESET 0x0000
-+
-+#define AR2315_RESET_COLD_AHB 0x00000001
-+#define AR2315_RESET_COLD_APB 0x00000002
-+#define AR2315_RESET_COLD_CPU 0x00000004
-+#define AR2315_RESET_COLD_CPUWARM 0x00000008
-+#define AR2315_RESET_SYSTEM (RESET_COLD_CPU |\
-+ RESET_COLD_APB |\
-+ RESET_COLD_AHB) /* full system */
-+#define AR2317_RESET_SYSTEM 0x00000010
-+
-+/* Reset register */
-+#define AR2315_RESET 0x0004
-+
-+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
-+#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BB */
-+#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
-+#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
-+#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset mem control */
-+#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
-+#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
-+#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI iface */
-+#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
-+#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR iface */
-+#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
-+#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 MAC */
-+
-+/* AHB master arbitration control */
-+#define AR2315_AHB_ARB_CTL 0x0008
-+
-+#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
-+#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
-+#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
-+#define AR2315_ARB_LOCAL 0x00000008 /* Local bus */
-+#define AR2315_ARB_PCI 0x00000010 /* PCI bus */
-+#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
-+#define AR2315_ARB_RETRY 0x00000100 /* Retry policy (debug) */
-+
-+/* Config Register */
-+#define AR2315_ENDIAN_CTL 0x000c
-+
-+#define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
-+#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
-+#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
-+#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
-+#define AR2315_CONFIG_MEMCTL 0x00000010 /* Mem controller endian */
-+#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
-+#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
-+#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
-+#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
-+#define AR2315_CONFIG_BIG 0x00000400
-+#define AR2315_CONFIG_PCIAHB 0x00000800
-+#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
-+#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
-+#define AR2315_CONFIG_CPU_DRAM 0x00010000
-+#define AR2315_CONFIG_CPU_PCI 0x00020000
-+#define AR2315_CONFIG_CPU_MMR 0x00040000
-+
-+/* NMI control */
-+#define AR2315_NMI_CTL 0x0010
-+
-+#define AR2315_NMI_EN 1
-+
-+/* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
-+#define AR2315_SREV 0x0014
-+
-+#define AR2315_REV_MAJ 0x000000f0
-+#define AR2315_REV_MAJ_S 4
-+#define AR2315_REV_MIN 0x0000000f
-+#define AR2315_REV_MIN_S 0
-+#define AR2315_REV_CHIP (AR2315_REV_MAJ | AR2315_REV_MIN)
-+
-+/* Interface Enable */
-+#define AR2315_IF_CTL 0x0018
-+
-+#define AR2315_IF_MASK 0x00000007
-+#define AR2315_IF_DISABLED 0 /* Disable all */
-+#define AR2315_IF_PCI 1 /* PCI */
-+#define AR2315_IF_TS_LOCAL 2 /* Local bus */
-+#define AR2315_IF_ALL 3 /* Emulation only */
-+#define AR2315_IF_LOCAL_HOST 0x00000008
-+#define AR2315_IF_PCI_HOST 0x00000010
-+#define AR2315_IF_PCI_INTR 0x00000020
-+#define AR2315_IF_PCI_CLK_MASK 0x00030000
-+#define AR2315_IF_PCI_CLK_INPUT 0
-+#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
-+#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
-+#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
-+#define AR2315_IF_PCI_CLK_SHIFT 16
-+
-+/* APB Interrupt control */
-+#define AR2315_ISR 0x0020
-+#define AR2315_IMR 0x0024
-+#define AR2315_GISR 0x0028
-+
-+#define AR2315_ISR_UART0 0x00000001 /* high speed UART */
-+#define AR2315_ISR_I2C_RSVD 0x00000002 /* I2C bus */
-+#define AR2315_ISR_SPI 0x00000004 /* SPI bus */
-+#define AR2315_ISR_AHB 0x00000008 /* AHB error */
-+#define AR2315_ISR_APB 0x00000010 /* APB error */
-+#define AR2315_ISR_TIMER 0x00000020 /* Timer */
-+#define AR2315_ISR_GPIO 0x00000040 /* GPIO */
-+#define AR2315_ISR_WD 0x00000080 /* Watchdog */
-+#define AR2315_ISR_IR_RSVD 0x00000100 /* IR */
-+
-+#define AR2315_GISR_MISC 0x00000001 /* Misc */
-+#define AR2315_GISR_WLAN0 0x00000002 /* WLAN0 */
-+#define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
-+#define AR2315_GISR_LOCALPCI 0x00000008 /* Local/PCI bus */
-+#define AR2315_GISR_WMACPOLL 0x00000010
-+#define AR2315_GISR_TIMER 0x00000020
-+#define AR2315_GISR_ETHERNET 0x00000040 /* Ethernet */
-+
-+/* Generic timer */
-+#define AR2315_TIMER 0x0030
-+#define AR2315_RELOAD 0x0034
-+
-+/* Watchdog timer */
-+#define AR2315_WDT_TIMER 0x0038
-+#define AR2315_WDT_CTRL 0x003c
-+
-+#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
-+#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
-+#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
-+
-+/* CPU Performance Counters */
-+#define AR2315_PERFCNT0 0x0048
-+#define AR2315_PERFCNT1 0x004c
-+
-+#define AR2315_PERF0_DATAHIT 0x00000001 /* Count Data Cache Hits */
-+#define AR2315_PERF0_DATAMISS 0x00000002 /* Count Data Cache Misses */
-+#define AR2315_PERF0_INSTHIT 0x00000004 /* Count Instruction Cache Hits */
-+#define AR2315_PERF0_INSTMISS 0x00000008 /* Count Instruction Cache Misses */
-+#define AR2315_PERF0_ACTIVE 0x00000010 /* Count Active Processor Cycles */
-+#define AR2315_PERF0_WBHIT 0x00000020 /* Count CPU Write Buffer Hits */
-+#define AR2315_PERF0_WBMISS 0x00000040 /* Count CPU Write Buffer Misses */
-+
-+#define AR2315_PERF1_EB_ARDY 0x00000001 /* Count EB_ARdy signal */
-+#define AR2315_PERF1_EB_AVALID 0x00000002 /* Count EB_AValid signal */
-+#define AR2315_PERF1_EB_WDRDY 0x00000004 /* Count EB_WDRdy signal */
-+#define AR2315_PERF1_EB_RDVAL 0x00000008 /* Count EB_RdVal signal */
-+#define AR2315_PERF1_VRADDR 0x00000010 /* Count valid read address cycles*/
-+#define AR2315_PERF1_VWADDR 0x00000020 /* Count valid write address cycl.*/
-+#define AR2315_PERF1_VWDATA 0x00000040 /* Count valid write data cycles */
-+
-+/* AHB Error Reporting */
-+#define AR2315_AHB_ERR0 0x0050 /* error */
-+#define AR2315_AHB_ERR1 0x0054 /* haddr */
-+#define AR2315_AHB_ERR2 0x0058 /* hwdata */
-+#define AR2315_AHB_ERR3 0x005c /* hrdata */
-+#define AR2315_AHB_ERR4 0x0060 /* status */
-+
-+#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */
-+ /* write 1 to clear all bits in ERR0 */
-+#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
-+#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
-+
-+#define AR2315_PROCERR_HMAST 0x0000000f
-+#define AR2315_PROCERR_HMAST_DFLT 0
-+#define AR2315_PROCERR_HMAST_WMAC 1
-+#define AR2315_PROCERR_HMAST_ENET 2
-+#define AR2315_PROCERR_HMAST_PCIENDPT 3
-+#define AR2315_PROCERR_HMAST_LOCAL 4
-+#define AR2315_PROCERR_HMAST_CPU 5
-+#define AR2315_PROCERR_HMAST_PCITGT 6
-+#define AR2315_PROCERR_HMAST_S 0
-+#define AR2315_PROCERR_HWRITE 0x00000010
-+#define AR2315_PROCERR_HSIZE 0x00000060
-+#define AR2315_PROCERR_HSIZE_S 5
-+#define AR2315_PROCERR_HTRANS 0x00000180
-+#define AR2315_PROCERR_HTRANS_S 7
-+#define AR2315_PROCERR_HBURST 0x00000e00
-+#define AR2315_PROCERR_HBURST_S 9
-+
-+/* Clock Control */
-+#define AR2315_PLLC_CTL 0x0064
-+#define AR2315_PLLV_CTL 0x0068
-+#define AR2315_CPUCLK 0x006c
-+#define AR2315_AMBACLK 0x0070
-+#define AR2315_SYNCCLK 0x0074
-+#define AR2315_DSL_SLEEP_CTL 0x0080
-+#define AR2315_DSL_SLEEP_DUR 0x0084
-+
-+/* PLLc Control fields */
-+#define AR2315_PLLC_REF_DIV_M 0x00000003
-+#define AR2315_PLLC_REF_DIV_S 0
-+#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c
-+#define AR2315_PLLC_FDBACK_DIV_S 2
-+#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080
-+#define AR2315_PLLC_ADD_FDBACK_DIV_S 7
-+#define AR2315_PLLC_CLKC_DIV_M 0x0001c000
-+#define AR2315_PLLC_CLKC_DIV_S 14
-+#define AR2315_PLLC_CLKM_DIV_M 0x00700000
-+#define AR2315_PLLC_CLKM_DIV_S 20
-+
-+/* CPU CLK Control fields */
-+#define AR2315_CPUCLK_CLK_SEL_M 0x00000003
-+#define AR2315_CPUCLK_CLK_SEL_S 0
-+#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c
-+#define AR2315_CPUCLK_CLK_DIV_S 2
-+
-+/* AMBA CLK Control fields */
-+#define AR2315_AMBACLK_CLK_SEL_M 0x00000003
-+#define AR2315_AMBACLK_CLK_SEL_S 0
-+#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
-+#define AR2315_AMBACLK_CLK_DIV_S 2
-+
-+/* PCI Clock Control */
-+#define AR2315_PCICLK 0x00a4
-+
-+#define AR2315_PCICLK_INPUT_M 0x00000003
-+#define AR2315_PCICLK_INPUT_S 0
-+#define AR2315_PCICLK_PLLC_CLKM 0
-+#define AR2315_PCICLK_PLLC_CLKM1 1
-+#define AR2315_PCICLK_PLLC_CLKC 2
-+#define AR2315_PCICLK_REF_CLK 3
-+#define AR2315_PCICLK_DIV_M 0x0000000c
-+#define AR2315_PCICLK_DIV_S 2
-+#define AR2315_PCICLK_IN_FREQ 0
-+#define AR2315_PCICLK_IN_FREQ_DIV_6 1
-+#define AR2315_PCICLK_IN_FREQ_DIV_8 2
-+#define AR2315_PCICLK_IN_FREQ_DIV_10 3
-+
-+/* Observation Control Register */
-+#define AR2315_OCR 0x00b0
-+
-+#define AR2315_OCR_GPIO0_IRIN 0x00000040
-+#define AR2315_OCR_GPIO1_IROUT 0x00000080
-+#define AR2315_OCR_GPIO3_RXCLR 0x00000200
-+
-+/* General Clock Control */
-+#define AR2315_MISCCLK 0x00b4
-+
-+#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
-+#define AR2315_MISCCLK_PROCREFCLK 0x00000002
-+
-+/*
-+ * SDRAM Controller
-+ * - No read or write buffers are included.
-+ */
-+#define AR2315_MEM_CFG 0x0000
-+#define AR2315_MEM_CTRL 0x000c
-+#define AR2315_MEM_REF 0x0010
-+
-+#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000
-+#define AR2315_MEM_CFG_DATA_WIDTH_S 13
-+#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00
-+#define AR2315_MEM_CFG_COL_WIDTH_S 9
-+#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0
-+#define AR2315_MEM_CFG_ROW_WIDTH_S 5
-+#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
-+#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
-+
-+/*
-+ * Local Bus Interface Registers
-+ */
-+#define AR2315_LB_CONFIG 0x0000
-+
-+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
-+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
-+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
-+#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
-+#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
-+#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
-+#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
-+#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
-+#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
-+#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
-+#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
-+#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
-+#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
-+#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
-+#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
-+#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
-+#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
-+#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
-+#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
-+#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
-+#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
-+#define AR2315_LBCONF_INT_CTR3 0x000c0000 /* GND drive, Vdd drive */
-+#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
-+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
-+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
-+
-+#define AR2315_LB_CLKSEL 0x0004
-+
-+#define AR2315_LBCLK_EXT 0x00000001 /* use external clk for lb */
-+
-+#define AR2315_LB_1MS 0x0008
-+
-+#define AR2315_LB1MS_MASK 0x0003ffff /* # of AHB clk cycles in 1ms */
-+
-+#define AR2315_LB_MISCCFG 0x000c
-+
-+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
-+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
-+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
-+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
-+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
-+#define AR2315_LBM_TIMEOUT_M 0x00ffff80
-+#define AR2315_LBM_TIMEOUT_S 7
-+#define AR2315_LBM_PORTMUX 0x07000000
-+
-+#define AR2315_LB_RXTSOFF 0x0010
-+
-+#define AR2315_LB_TX_CHAIN_EN 0x0100
-+
-+#define AR2315_LB_TXEN_0 0x00000001
-+#define AR2315_LB_TXEN_1 0x00000002
-+#define AR2315_LB_TXEN_2 0x00000004
-+#define AR2315_LB_TXEN_3 0x00000008
-+
-+#define AR2315_LB_TX_CHAIN_DIS 0x0104
-+#define AR2315_LB_TX_DESC_PTR 0x0200
-+
-+#define AR2315_LB_RX_CHAIN_EN 0x0400
-+
-+#define AR2315_LB_RXEN 0x00000001
-+
-+#define AR2315_LB_RX_CHAIN_DIS 0x0404
-+#define AR2315_LB_RX_DESC_PTR 0x0408
-+
-+#define AR2315_LB_INT_STATUS 0x0500
-+
-+#define AR2315_LB_INT_TX_DESC 0x00000001
-+#define AR2315_LB_INT_TX_OK 0x00000002
-+#define AR2315_LB_INT_TX_ERR 0x00000004
-+#define AR2315_LB_INT_TX_EOF 0x00000008
-+#define AR2315_LB_INT_RX_DESC 0x00000010
-+#define AR2315_LB_INT_RX_OK 0x00000020
-+#define AR2315_LB_INT_RX_ERR 0x00000040
-+#define AR2315_LB_INT_RX_EOF 0x00000080
-+#define AR2315_LB_INT_TX_TRUNC 0x00000100
-+#define AR2315_LB_INT_TX_STARVE 0x00000200
-+#define AR2315_LB_INT_LB_TIMEOUT 0x00000400
-+#define AR2315_LB_INT_LB_ERR 0x00000800
-+#define AR2315_LB_INT_MBOX_WR 0x00001000
-+#define AR2315_LB_INT_MBOX_RD 0x00002000
-+
-+/* Bit definitions for INT MASK are the same as INT_STATUS */
-+#define AR2315_LB_INT_MASK 0x0504
-+
-+#define AR2315_LB_INT_EN 0x0508
-+#define AR2315_LB_MBOX 0x0600
-+
-+#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
---- /dev/null
-+++ b/arch/mips/ath25/ar5312_regs.h
-@@ -0,0 +1,224 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-+ */
-+
-+#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
-+#define __ASM_MACH_ATH25_AR5312_REGS_H
-+
-+/*
-+ * IRQs
-+ */
-+#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
-+#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
-+#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
-+#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
-+#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
-+
-+/*
-+ * Miscellaneous interrupts, which share IP6.
-+ */
-+#define AR5312_MISC_IRQ_TIMER 0
-+#define AR5312_MISC_IRQ_AHB_PROC 1
-+#define AR5312_MISC_IRQ_AHB_DMA 2
-+#define AR5312_MISC_IRQ_GPIO 3
-+#define AR5312_MISC_IRQ_UART0 4
-+#define AR5312_MISC_IRQ_UART0_DMA 5
-+#define AR5312_MISC_IRQ_WATCHDOG 6
-+#define AR5312_MISC_IRQ_LOCAL 7
-+#define AR5312_MISC_IRQ_SPI 8
-+#define AR5312_MISC_IRQ_COUNT 9
-+
-+/*
-+ * Address Map
-+ *
-+ * The AR5312 supports 2 enet MACS, even though many reference boards only
-+ * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
-+ * PHY or PHY switch. The AR2312 supports 1 enet MAC.
-+ */
-+#define AR5312_WLAN0_BASE 0x18000000
-+#define AR5312_ENET0_BASE 0x18100000
-+#define AR5312_ENET1_BASE 0x18200000
-+#define AR5312_SDRAMCTL_BASE 0x18300000
-+#define AR5312_SDRAMCTL_SIZE 0x00000010
-+#define AR5312_FLASHCTL_BASE 0x18400000
-+#define AR5312_FLASHCTL_SIZE 0x00000010
-+#define AR5312_WLAN1_BASE 0x18500000
-+#define AR5312_UART0_BASE 0x1c000000 /* UART MMR */
-+#define AR5312_GPIO_BASE 0x1c002000
-+#define AR5312_GPIO_SIZE 0x00000010
-+#define AR5312_RST_BASE 0x1c003000
-+#define AR5312_RST_SIZE 0x00000100
-+#define AR5312_FLASH_BASE 0x1e000000
-+#define AR5312_FLASH_SIZE 0x00800000
-+
-+/*
-+ * Need these defines to determine true number of ethernet MACs
-+ */
-+#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
-+#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
-+#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
-+
-+/* Reset/Timer Block Address Map */
-+#define AR5312_TIMER 0x0000 /* countdown timer */
-+#define AR5312_RELOAD 0x0004 /* timer reload value */
-+#define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */
-+#define AR5312_WDT_TIMER 0x000c /* watchdog timer */
-+#define AR5312_ISR 0x0010 /* Intr Status Reg */
-+#define AR5312_IMR 0x0014 /* Intr Mask Reg */
-+#define AR5312_RESET 0x0020
-+#define AR5312_CLOCKCTL1 0x0064
-+#define AR5312_SCRATCH 0x006c
-+#define AR5312_PROCADDR 0x0070
-+#define AR5312_PROC1 0x0074
-+#define AR5312_DMAADDR 0x0078
-+#define AR5312_DMA1 0x007c
-+#define AR5312_ENABLE 0x0080 /* interface enb */
-+#define AR5312_REV 0x0090 /* revision */
-+
-+/* AR5312_WDT_CTRL register bit field definitions */
-+#define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
-+#define AR5312_WDT_CTRL_NMI 0x00000001
-+#define AR5312_WDT_CTRL_RESET 0x00000002
-+
-+/* AR5312_ISR register bit field definitions */
-+#define AR5312_ISR_TIMER 0x00000001
-+#define AR5312_ISR_AHBPROC 0x00000002
-+#define AR5312_ISR_AHBDMA 0x00000004
-+#define AR5312_ISR_GPIO 0x00000008
-+#define AR5312_ISR_UART0 0x00000010
-+#define AR5312_ISR_UART0DMA 0x00000020
-+#define AR5312_ISR_WD 0x00000040
-+#define AR5312_ISR_LOCAL 0x00000080
-+
-+/* AR5312_RESET register bit field definitions */
-+#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
-+#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
-+#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC/BB */
-+#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
-+#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
-+#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 MAC */
-+#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 MAC */
-+#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 */
-+#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
-+#define AR5312_RESET_APB 0x00000400 /* cold reset APB ar5312 */
-+#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
-+#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
-+#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BB */
-+#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the CPU */
-+#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 MAC */
-+#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 BB */
-+#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
-+#define AR5312_RESET_WDOG 0x00100000 /* last reset was a wdt */
-+
-+#define AR5312_RESET_WMAC0_BITS (AR5312_RESET_WLAN0 |\
-+ AR5312_RESET_WARM_WLAN0_MAC |\
-+ AR5312_RESET_WARM_WLAN0_BB)
-+
-+#define AR5312_RESET_WMAC1_BITS (AR5312_RESET_WLAN1 |\
-+ AR5312_RESET_WARM_WLAN1_MAC |\
-+ AR5312_RESET_WARM_WLAN1_BB)
-+
-+/* AR5312_CLOCKCTL1 register bit field definitions */
-+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
-+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
-+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
-+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
-+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
-+
-+/* Valid for AR5312 and AR2312 */
-+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
-+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
-+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
-+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
-+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
-+
-+/* Valid for AR2313 */
-+#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
-+#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
-+#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
-+#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
-+#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
-+
-+/* AR5312_ENABLE register bit field definitions */
-+#define AR5312_ENABLE_WLAN0 0x00000001
-+#define AR5312_ENABLE_ENET0 0x00000002
-+#define AR5312_ENABLE_ENET1 0x00000004
-+#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x00000008/* UART & WLAN1 PIO */
-+#define AR5312_ENABLE_WLAN1_DMA 0x00000010/* WLAN1 DMAs */
-+#define AR5312_ENABLE_WLAN1 (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
-+ AR5312_ENABLE_WLAN1_DMA)
-+
-+/* AR5312_REV register bit field definitions */
-+#define AR5312_REV_WMAC_MAJ 0x0000f000
-+#define AR5312_REV_WMAC_MAJ_S 12
-+#define AR5312_REV_WMAC_MIN 0x00000f00
-+#define AR5312_REV_WMAC_MIN_S 8
-+#define AR5312_REV_MAJ 0x000000f0
-+#define AR5312_REV_MAJ_S 4
-+#define AR5312_REV_MIN 0x0000000f
-+#define AR5312_REV_MIN_S 0
-+#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
-+
-+/* Major revision numbers, bits 7..4 of Revision ID register */
-+#define AR5312_REV_MAJ_AR5312 0x4
-+#define AR5312_REV_MAJ_AR2313 0x5
-+
-+/* Minor revision numbers, bits 3..0 of Revision ID register */
-+#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
-+#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
-+
-+/*
-+ * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
-+ */
-+#define AR5312_FLASHCTL0 0x0000
-+#define AR5312_FLASHCTL1 0x0004
-+#define AR5312_FLASHCTL2 0x0008
-+
-+/* AR5312_FLASHCTL register bit field definitions */
-+#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */
-+#define AR5312_FLASHCTL_IDCY_S 0
-+#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
-+#define AR5312_FLASHCTL_WST1_S 5
-+#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
-+#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
-+#define AR5312_FLASHCTL_WST2_S 11
-+#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */
-+#define AR5312_FLASHCTL_AC_S 16
-+#define AR5312_FLASHCTL_AC_128K 0x00000000
-+#define AR5312_FLASHCTL_AC_256K 0x00010000
-+#define AR5312_FLASHCTL_AC_512K 0x00020000
-+#define AR5312_FLASHCTL_AC_1M 0x00030000
-+#define AR5312_FLASHCTL_AC_2M 0x00040000
-+#define AR5312_FLASHCTL_AC_4M 0x00050000
-+#define AR5312_FLASHCTL_AC_8M 0x00060000
-+#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
-+#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
-+#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */
-+#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */
-+#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */
-+#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */
-+#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
-+#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
-+#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
-+#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */
-+#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */
-+#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
-+#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */
-+
-+/*
-+ * ARM SDRAM Controller -- just enough to determine memory size
-+ */
-+#define AR5312_MEM_CFG1 0x0004
-+
-+#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */
-+#define AR5312_MEM_CFG1_AC0_S 8
-+#define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */
-+#define AR5312_MEM_CFG1_AC1_S 12
-+
-+#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
---- /dev/null
-+++ b/arch/mips/ath25/ar5312.c
-@@ -0,0 +1,393 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
-+ * Copyright (C) 2006 FON Technology, SL.
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
-+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
-+ */
-+
-+/*
-+ * Platform devices for Atheros AR5312 SoCs
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/bitops.h>
-+#include <linux/irqdomain.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/mtd/physmap.h>
-+#include <linux/reboot.h>
-+#include <asm/bootinfo.h>
-+#include <asm/reboot.h>
-+#include <asm/time.h>
-+
-+#include <ath25_platform.h>
-+
-+#include "devices.h"
-+#include "ar5312.h"
-+#include "ar5312_regs.h"
-+
-+static void __iomem *ar5312_rst_base;
-+static struct irq_domain *ar5312_misc_irq_domain;
-+
-+static inline u32 ar5312_rst_reg_read(u32 reg)
-+{
-+ return __raw_readl(ar5312_rst_base + reg);
-+}
-+
-+static inline void ar5312_rst_reg_write(u32 reg, u32 val)
-+{
-+ __raw_writel(val, ar5312_rst_base + reg);
-+}
-+
-+static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
-+{
-+ u32 ret = ar5312_rst_reg_read(reg);
-+
-+ ret &= ~mask;
-+ ret |= val;
-+ ar5312_rst_reg_write(reg, ret);
-+}
-+
-+static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
-+{
-+ u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
-+ u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
-+ u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
-+ u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
-+
-+ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
-+ proc_addr, proc1, dma_addr, dma1);
-+
-+ machine_restart("AHB error"); /* Catastrophic failure */
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction ar5312_ahb_err_interrupt = {
-+ .handler = ar5312_ahb_err_handler,
-+ .name = "ar5312-ahb-error",
-+};
-+
-+static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
-+{
-+ u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
-+ ar5312_rst_reg_read(AR5312_IMR);
-+ unsigned nr, misc_irq = 0;
-+
-+ if (pending) {
-+ struct irq_domain *domain = irq_get_handler_data(irq);
-+
-+ nr = __ffs(pending);
-+ misc_irq = irq_find_mapping(domain, nr);
-+ }
-+
-+ if (misc_irq) {
-+ generic_handle_irq(misc_irq);
-+ if (nr == AR5312_MISC_IRQ_TIMER)
-+ ar5312_rst_reg_read(AR5312_TIMER);
-+ } else {
-+ spurious_interrupt();
-+ }
-+}
-+
-+/* Enable the specified AR5312_MISC_IRQ interrupt */
-+static void ar5312_misc_irq_unmask(struct irq_data *d)
-+{
-+ ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
-+}
-+
-+/* Disable the specified AR5312_MISC_IRQ interrupt */
-+static void ar5312_misc_irq_mask(struct irq_data *d)
-+{
-+ ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
-+ ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
-+}
-+
-+static struct irq_chip ar5312_misc_irq_chip = {
-+ .name = "ar5312-misc",
-+ .irq_unmask = ar5312_misc_irq_unmask,
-+ .irq_mask = ar5312_misc_irq_mask,
-+};
-+
-+static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
-+ irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
-+ return 0;
-+}
-+
-+static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
-+ .map = ar5312_misc_irq_map,
-+};
-+
-+static void ar5312_irq_dispatch(void)
-+{
-+ u32 pending = read_c0_status() & read_c0_cause();
-+
-+ if (pending & CAUSEF_IP2)
-+ do_IRQ(AR5312_IRQ_WLAN0);
-+ else if (pending & CAUSEF_IP5)
-+ do_IRQ(AR5312_IRQ_WLAN1);
-+ else if (pending & CAUSEF_IP6)
-+ do_IRQ(AR5312_IRQ_MISC);
-+ else if (pending & CAUSEF_IP7)
-+ do_IRQ(ATH25_IRQ_CPU_CLOCK);
-+ else
-+ spurious_interrupt();
-+}
-+
-+void __init ar5312_arch_init_irq(void)
-+{
-+ struct irq_domain *domain;
-+ unsigned irq;
-+
-+ ath25_irq_dispatch = ar5312_irq_dispatch;
-+
-+ domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
-+ &ar5312_misc_irq_domain_ops, NULL);
-+ if (!domain)
-+ panic("Failed to add IRQ domain");
-+
-+ irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
-+ setup_irq(irq, &ar5312_ahb_err_interrupt);
-+
-+ irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
-+ irq_set_handler_data(AR5312_IRQ_MISC, domain);
-+
-+ ar5312_misc_irq_domain = domain;
-+}
-+
-+static struct physmap_flash_data ar5312_flash_data = {
-+ .width = 2,
-+};
-+
-+static struct resource ar5312_flash_resource = {
-+ .start = AR5312_FLASH_BASE,
-+ .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device ar5312_physmap_flash = {
-+ .name = "physmap-flash",
-+ .id = 0,
-+ .dev.platform_data = &ar5312_flash_data,
-+ .resource = &ar5312_flash_resource,
-+ .num_resources = 1,
-+};
-+
-+static void __init ar5312_flash_init(void)
-+{
-+ void __iomem *flashctl_base;
-+ u32 ctl;
-+
-+ flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
-+ AR5312_FLASHCTL_SIZE);
-+
-+ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
-+ ctl &= AR5312_FLASHCTL_MW;
-+
-+ /* fixup flash width */
-+ switch (ctl) {
-+ case AR5312_FLASHCTL_MW16:
-+ ar5312_flash_data.width = 2;
-+ break;
-+ case AR5312_FLASHCTL_MW8:
-+ default:
-+ ar5312_flash_data.width = 1;
-+ break;
-+ }
-+
-+ /*
-+ * Configure flash bank 0.
-+ * Assume 8M window size. Flash will be aliased if it's smaller
-+ */
-+ ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
-+ ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
-+ ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
-+ ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
-+ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
-+
-+ /* Disable other flash banks */
-+ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
-+ ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
-+ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
-+ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
-+ ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
-+ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
-+
-+ iounmap(flashctl_base);
-+}
-+
-+void __init ar5312_init_devices(void)
-+{
-+ struct ath25_boarddata *config;
-+
-+ ar5312_flash_init();
-+
-+ /* Locate board/radio config data */
-+ ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
-+ config = ath25_board.config;
-+
-+ /* AR2313 has CPU minor rev. 10 */
-+ if ((current_cpu_data.processor_id & 0xff) == 0x0a)
-+ ath25_soc = ATH25_SOC_AR2313;
-+
-+ /* AR2312 shares the same Silicon ID as AR5312 */
-+ else if (config->flags & BD_ISCASPER)
-+ ath25_soc = ATH25_SOC_AR2312;
-+
-+ /* Everything else is probably AR5312 or compatible */
-+ else
-+ ath25_soc = ATH25_SOC_AR5312;
-+
-+ platform_device_register(&ar5312_physmap_flash);
-+
-+ switch (ath25_soc) {
-+ case ATH25_SOC_AR5312:
-+ if (!ath25_board.radio)
-+ return;
-+
-+ if (!(config->flags & BD_WLAN0))
-+ break;
-+
-+ ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
-+ break;
-+ case ATH25_SOC_AR2312:
-+ case ATH25_SOC_AR2313:
-+ if (!ath25_board.radio)
-+ return;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ if (config->flags & BD_WLAN1)
-+ ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
-+}
-+
-+static void ar5312_restart(char *command)
-+{
-+ /* reset the system */
-+ local_irq_disable();
-+ while (1)
-+ ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
-+}
-+
-+/*
-+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
-+ * to determine the predevisor value.
-+ */
-+static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
-+
-+static unsigned __init ar5312_cpu_frequency(void)
-+{
-+ u32 scratch, devid, clock_ctl1;
-+ u32 predivide_mask, multiplier_mask, doubler_mask;
-+ unsigned predivide_shift, multiplier_shift;
-+ unsigned predivide_select, predivisor, multiplier;
-+
-+ /* Trust the bootrom's idea of cpu frequency. */
-+ scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
-+ if (scratch)
-+ return scratch;
-+
-+ devid = ar5312_rst_reg_read(AR5312_REV);
-+ devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
-+ if (devid == AR5312_REV_MAJ_AR2313) {
-+ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
-+ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
-+ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
-+ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
-+ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
-+ } else { /* AR5312 and AR2312 */
-+ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
-+ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
-+ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
-+ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
-+ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
-+ }
-+
-+ /*
-+ * Clocking is derived from a fixed 40MHz input clock.
-+ *
-+ * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
-+ * sys_freq = cpu_freq / 4 (used for APB clock, serial,
-+ * flash, Timer, Watchdog Timer)
-+ *
-+ * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
-+ *
-+ * So, for example, with a PLL multiplier of 5, we have
-+ *
-+ * cpu_freq = 200MHz
-+ * sys_freq = 50MHz
-+ * cnt_freq = 100MHz
-+ *
-+ * We compute the CPU frequency, based on PLL settings.
-+ */
-+
-+ clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
-+ predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
-+ predivisor = clockctl1_predivide_table[predivide_select];
-+ multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
-+
-+ if (clock_ctl1 & doubler_mask)
-+ multiplier <<= 1;
-+
-+ return (40000000 / predivisor) * multiplier;
-+}
-+
-+static inline unsigned ar5312_sys_frequency(void)
-+{
-+ return ar5312_cpu_frequency() / 4;
-+}
-+
-+void __init ar5312_plat_time_init(void)
-+{
-+ mips_hpt_frequency = ar5312_cpu_frequency() / 2;
-+}
-+
-+void __init ar5312_plat_mem_setup(void)
-+{
-+ void __iomem *sdram_base;
-+ u32 memsize, memcfg, bank0_ac, bank1_ac;
-+ u32 devid;
-+
-+ /* Detect memory size */
-+ sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
-+ AR5312_SDRAMCTL_SIZE);
-+ memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
-+ bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
-+ bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
-+ memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
-+ (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
-+ memsize <<= 20;
-+ add_memory_region(0, memsize, BOOT_MEM_RAM);
-+ iounmap(sdram_base);
-+
-+ ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
-+
-+ devid = ar5312_rst_reg_read(AR5312_REV);
-+ devid >>= AR5312_REV_WMAC_MIN_S;
-+ devid &= AR5312_REV_CHIP;
-+ ath25_board.devid = (u16)devid;
-+
-+ /* Clear any lingering AHB errors */
-+ ar5312_rst_reg_read(AR5312_PROCADDR);
-+ ar5312_rst_reg_read(AR5312_DMAADDR);
-+ ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
-+
-+ _machine_restart = ar5312_restart;
-+}
-+
-+void __init ar5312_arch_init(void)
-+{
-+ unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
-+ AR5312_MISC_IRQ_UART0);
-+
-+ ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
-+}
---- /dev/null
-+++ b/arch/mips/ath25/ar2315.c
-@@ -0,0 +1,308 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
-+ * Copyright (C) 2006 FON Technology, SL.
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
-+ */
-+
-+/*
-+ * Platform devices for Atheros AR2315 SoCs
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/bitops.h>
-+#include <linux/irqdomain.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/reboot.h>
-+#include <asm/bootinfo.h>
-+#include <asm/reboot.h>
-+#include <asm/time.h>
-+
-+#include <ath25_platform.h>
-+
-+#include "devices.h"
-+#include "ar2315.h"
-+#include "ar2315_regs.h"
-+
-+static void __iomem *ar2315_rst_base;
-+static struct irq_domain *ar2315_misc_irq_domain;
-+
-+static inline u32 ar2315_rst_reg_read(u32 reg)
-+{
-+ return __raw_readl(ar2315_rst_base + reg);
-+}
-+
-+static inline void ar2315_rst_reg_write(u32 reg, u32 val)
-+{
-+ __raw_writel(val, ar2315_rst_base + reg);
-+}
-+
-+static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
-+{
-+ u32 ret = ar2315_rst_reg_read(reg);
-+
-+ ret &= ~mask;
-+ ret |= val;
-+ ar2315_rst_reg_write(reg, ret);
-+}
-+
-+static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
-+{
-+ ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
-+ ar2315_rst_reg_read(AR2315_AHB_ERR1);
-+
-+ pr_emerg("AHB fatal error\n");
-+ machine_restart("AHB error"); /* Catastrophic failure */
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction ar2315_ahb_err_interrupt = {
-+ .handler = ar2315_ahb_err_handler,
-+ .name = "ar2315-ahb-error",
-+};
-+
-+static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
-+{
-+ u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
-+ ar2315_rst_reg_read(AR2315_IMR);
-+ unsigned nr, misc_irq = 0;
-+
-+ if (pending) {
-+ struct irq_domain *domain = irq_get_handler_data(irq);
-+
-+ nr = __ffs(pending);
-+ misc_irq = irq_find_mapping(domain, nr);
-+ }
-+
-+ if (misc_irq) {
-+ if (nr == AR2315_MISC_IRQ_GPIO)
-+ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
-+ else if (nr == AR2315_MISC_IRQ_WATCHDOG)
-+ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
-+ generic_handle_irq(misc_irq);
-+ } else {
-+ spurious_interrupt();
-+ }
-+}
-+
-+static void ar2315_misc_irq_unmask(struct irq_data *d)
-+{
-+ ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
-+}
-+
-+static void ar2315_misc_irq_mask(struct irq_data *d)
-+{
-+ ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
-+}
-+
-+static struct irq_chip ar2315_misc_irq_chip = {
-+ .name = "ar2315-misc",
-+ .irq_unmask = ar2315_misc_irq_unmask,
-+ .irq_mask = ar2315_misc_irq_mask,
-+};
-+
-+static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
-+ irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
-+ return 0;
-+}
-+
-+static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
-+ .map = ar2315_misc_irq_map,
-+};
-+
-+/*
-+ * Called when an interrupt is received, this function
-+ * determines exactly which interrupt it was, and it
-+ * invokes the appropriate handler.
-+ *
-+ * Implicitly, we also define interrupt priority by
-+ * choosing which to dispatch first.
-+ */
-+static void ar2315_irq_dispatch(void)
-+{
-+ u32 pending = read_c0_status() & read_c0_cause();
-+
-+ if (pending & CAUSEF_IP3)
-+ do_IRQ(AR2315_IRQ_WLAN0);
-+ else if (pending & CAUSEF_IP2)
-+ do_IRQ(AR2315_IRQ_MISC);
-+ else if (pending & CAUSEF_IP7)
-+ do_IRQ(ATH25_IRQ_CPU_CLOCK);
-+ else
-+ spurious_interrupt();
-+}
-+
-+void __init ar2315_arch_init_irq(void)
-+{
-+ struct irq_domain *domain;
-+ unsigned irq;
-+
-+ ath25_irq_dispatch = ar2315_irq_dispatch;
-+
-+ domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
-+ &ar2315_misc_irq_domain_ops, NULL);
-+ if (!domain)
-+ panic("Failed to add IRQ domain");
-+
-+ irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
-+ setup_irq(irq, &ar2315_ahb_err_interrupt);
-+
-+ irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
-+ irq_set_handler_data(AR2315_IRQ_MISC, domain);
-+
-+ ar2315_misc_irq_domain = domain;
-+}
-+
-+void __init ar2315_init_devices(void)
-+{
-+ /* Find board configuration */
-+ ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
-+
-+ ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
-+}
-+
-+static void ar2315_restart(char *command)
-+{
-+ void (*mips_reset_vec)(void) = (void *)0xbfc00000;
-+
-+ local_irq_disable();
-+
-+ /* try reset the system via reset control */
-+ ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
-+
-+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
-+ * a workaround. Give it some time to attempt a gpio based hardware
-+ * reset (atheros reference design workaround) */
-+
-+ /* TODO: implement the GPIO reset workaround */
-+
-+ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
-+ * workaround. Attempt to jump to the mips reset location -
-+ * the boot loader itself might be able to recover the system */
-+ mips_reset_vec();
-+}
-+
-+/*
-+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
-+ * to determine the predevisor value.
-+ */
-+static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
-+static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
-+
-+static unsigned __init ar2315_sys_clk(u32 clock_ctl)
-+{
-+ unsigned int pllc_ctrl, cpu_div;
-+ unsigned int pllc_out, refdiv, fdiv, divby2;
-+ unsigned int clk_div;
-+
-+ pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
-+ refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
-+ refdiv = clockctl1_predivide_table[refdiv];
-+ fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
-+ divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
-+ pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
-+
-+ /* clkm input selected */
-+ switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
-+ case 0:
-+ case 1:
-+ clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
-+ clk_div = pllc_divide_table[clk_div];
-+ break;
-+ case 2:
-+ clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
-+ clk_div = pllc_divide_table[clk_div];
-+ break;
-+ default:
-+ pllc_out = 40000000;
-+ clk_div = 1;
-+ break;
-+ }
-+
-+ cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
-+ cpu_div = cpu_div * 2 ?: 1;
-+
-+ return pllc_out / (clk_div * cpu_div);
-+}
-+
-+static inline unsigned ar2315_cpu_frequency(void)
-+{
-+ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
-+}
-+
-+static inline unsigned ar2315_apb_frequency(void)
-+{
-+ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
-+}
-+
-+void __init ar2315_plat_time_init(void)
-+{
-+ mips_hpt_frequency = ar2315_cpu_frequency() / 2;
-+}
-+
-+void __init ar2315_plat_mem_setup(void)
-+{
-+ void __iomem *sdram_base;
-+ u32 memsize, memcfg;
-+ u32 devid;
-+ u32 config;
-+
-+ /* Detect memory size */
-+ sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
-+ AR2315_SDRAMCTL_SIZE);
-+ memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
-+ memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
-+ memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
-+ memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
-+ memsize <<= 3;
-+ add_memory_region(0, memsize, BOOT_MEM_RAM);
-+ iounmap(sdram_base);
-+
-+ ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
-+
-+ /* Detect the hardware based on the device ID */
-+ devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
-+ switch (devid) {
-+ case 0x91: /* Need to check */
-+ ath25_soc = ATH25_SOC_AR2318;
-+ break;
-+ case 0x90:
-+ ath25_soc = ATH25_SOC_AR2317;
-+ break;
-+ case 0x87:
-+ ath25_soc = ATH25_SOC_AR2316;
-+ break;
-+ case 0x86:
-+ default:
-+ ath25_soc = ATH25_SOC_AR2315;
-+ break;
-+ }
-+ ath25_board.devid = devid;
-+
-+ /* Clear any lingering AHB errors */
-+ config = read_c0_config();
-+ write_c0_config(config & ~0x3);
-+ ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
-+ ar2315_rst_reg_read(AR2315_AHB_ERR1);
-+ ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
-+
-+ _machine_restart = ar2315_restart;
-+}
-+
-+void __init ar2315_arch_init(void)
-+{
-+ unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
-+ AR2315_MISC_IRQ_UART0);
-+
-+ ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
-+}
---- /dev/null
-+++ b/arch/mips/ath25/ar2315.h
-@@ -0,0 +1,22 @@
-+#ifndef __AR2315_H
-+#define __AR2315_H
-+
-+#ifdef CONFIG_SOC_AR2315
-+
-+void ar2315_arch_init_irq(void);
-+void ar2315_init_devices(void);
-+void ar2315_plat_time_init(void);
-+void ar2315_plat_mem_setup(void);
-+void ar2315_arch_init(void);
-+
-+#else
-+
-+static inline void ar2315_arch_init_irq(void) {}
-+static inline void ar2315_init_devices(void) {}
-+static inline void ar2315_plat_time_init(void) {}
-+static inline void ar2315_plat_mem_setup(void) {}
-+static inline void ar2315_arch_init(void) {}
-+
-+#endif
-+
-+#endif /* __AR2315_H */
---- /dev/null
-+++ b/arch/mips/ath25/ar5312.h
-@@ -0,0 +1,22 @@
-+#ifndef __AR5312_H
-+#define __AR5312_H
-+
-+#ifdef CONFIG_SOC_AR5312
-+
-+void ar5312_arch_init_irq(void);
-+void ar5312_init_devices(void);
-+void ar5312_plat_time_init(void);
-+void ar5312_plat_mem_setup(void);
-+void ar5312_arch_init(void);
-+
-+#else
-+
-+static inline void ar5312_arch_init_irq(void) {}
-+static inline void ar5312_init_devices(void) {}
-+static inline void ar5312_plat_time_init(void) {}
-+static inline void ar5312_plat_mem_setup(void) {}
-+static inline void ar5312_arch_init(void) {}
-+
-+#endif
-+
-+#endif /* __AR5312_H */
---- /dev/null
-+++ b/arch/mips/ath25/devices.h
-@@ -0,0 +1,43 @@
-+#ifndef __ATH25_DEVICES_H
-+#define __ATH25_DEVICES_H
-+
-+#include <linux/cpu.h>
-+
-+#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
-+
-+#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
-+
-+enum ath25_soc_type {
-+ /* handled by ar5312.c */
-+ ATH25_SOC_AR2312,
-+ ATH25_SOC_AR2313,
-+ ATH25_SOC_AR5312,
-+
-+ /* handled by ar2315.c */
-+ ATH25_SOC_AR2315,
-+ ATH25_SOC_AR2316,
-+ ATH25_SOC_AR2317,
-+ ATH25_SOC_AR2318,
-+
-+ ATH25_SOC_UNKNOWN
-+};
-+
-+extern enum ath25_soc_type ath25_soc;
-+extern struct ar231x_board_config ath25_board;
-+extern void (*ath25_irq_dispatch)(void);
-+
-+int ath25_find_config(phys_addr_t offset, unsigned long size);
-+void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
-+int ath25_add_wmac(int nr, u32 base, int irq);
-+
-+static inline bool is_ar2315(void)
-+{
-+ return (current_cpu_data.cputype == CPU_4KEC);
-+}
-+
-+static inline bool is_ar5312(void)
-+{
-+ return !is_ar2315();
-+}
-+
-+#endif
---- /dev/null
-+++ b/arch/mips/ath25/devices.c
-@@ -0,0 +1,125 @@
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/serial_8250.h>
-+#include <linux/platform_device.h>
-+#include <asm/bootinfo.h>
-+
-+#include <ath25_platform.h>
-+#include "devices.h"
-+#include "ar5312.h"
-+#include "ar2315.h"
-+
-+struct ar231x_board_config ath25_board;
-+enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
-+
-+static struct resource ath25_wmac0_res[] = {
-+ {
-+ .name = "wmac0_membase",
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "wmac0_irq",
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct resource ath25_wmac1_res[] = {
-+ {
-+ .name = "wmac1_membase",
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "wmac1_irq",
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device ath25_wmac[] = {
-+ {
-+ .id = 0,
-+ .name = "ar231x-wmac",
-+ .resource = ath25_wmac0_res,
-+ .num_resources = ARRAY_SIZE(ath25_wmac0_res),
-+ .dev.platform_data = &ath25_board,
-+ },
-+ {
-+ .id = 1,
-+ .name = "ar231x-wmac",
-+ .resource = ath25_wmac1_res,
-+ .num_resources = ARRAY_SIZE(ath25_wmac1_res),
-+ .dev.platform_data = &ath25_board,
-+ },
-+};
-+
-+static const char * const soc_type_strings[] = {
-+ [ATH25_SOC_AR5312] = "Atheros AR5312",
-+ [ATH25_SOC_AR2312] = "Atheros AR2312",
-+ [ATH25_SOC_AR2313] = "Atheros AR2313",
-+ [ATH25_SOC_AR2315] = "Atheros AR2315",
-+ [ATH25_SOC_AR2316] = "Atheros AR2316",
-+ [ATH25_SOC_AR2317] = "Atheros AR2317",
-+ [ATH25_SOC_AR2318] = "Atheros AR2318",
-+ [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
-+};
-+
-+const char *get_system_type(void)
-+{
-+ if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
-+ !soc_type_strings[ath25_soc])
-+ return soc_type_strings[ATH25_SOC_UNKNOWN];
-+ return soc_type_strings[ath25_soc];
-+}
-+
-+void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
-+{
-+ struct uart_port s;
-+
-+ memset(&s, 0, sizeof(s));
-+
-+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
-+ s.iotype = UPIO_MEM32;
-+ s.irq = irq;
-+ s.regshift = 2;
-+ s.mapbase = mapbase;
-+ s.uartclk = uartclk;
-+
-+ early_serial_setup(&s);
-+}
-+
-+int __init ath25_add_wmac(int nr, u32 base, int irq)
-+{
-+ struct resource *res;
-+
-+ ath25_wmac[nr].dev.platform_data = &ath25_board;
-+ res = &ath25_wmac[nr].resource[0];
-+ res->start = base;
-+ res->end = base + 0x10000 - 1;
-+ res++;
-+ res->start = irq;
-+ res->end = irq;
-+ return platform_device_register(&ath25_wmac[nr]);
-+}
-+
-+static int __init ath25_register_devices(void)
-+{
-+ if (is_ar5312())
-+ ar5312_init_devices();
-+ else
-+ ar2315_init_devices();
-+
-+ return 0;
-+}
-+
-+device_initcall(ath25_register_devices);
-+
-+static int __init ath25_arch_init(void)
-+{
-+ if (is_ar5312())
-+ ar5312_arch_init();
-+ else
-+ ar2315_arch_init();
-+
-+ return 0;
-+}
-+
-+arch_initcall(ath25_arch_init);
+++ /dev/null
---- /dev/null
-+++ b/arch/mips/ath25/early_printk.c
-@@ -0,0 +1,44 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
-+ */
-+
-+#include <linux/mm.h>
-+#include <linux/io.h>
-+#include <linux/serial_reg.h>
-+
-+#include "devices.h"
-+#include "ar2315_regs.h"
-+#include "ar5312_regs.h"
-+
-+static inline void prom_uart_wr(void __iomem *base, unsigned reg,
-+ unsigned char ch)
-+{
-+ __raw_writel(ch, base + 4 * reg);
-+}
-+
-+static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg)
-+{
-+ return __raw_readl(base + 4 * reg);
-+}
-+
-+void prom_putchar(unsigned char ch)
-+{
-+ static void __iomem *base;
-+
-+ if (unlikely(base == NULL)) {
-+ if (is_ar2315())
-+ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE));
-+ else
-+ base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE));
-+ }
-+
-+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
-+ ;
-+ prom_uart_wr(base, UART_TX, ch);
-+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
-+ ;
-+}
---- a/arch/mips/ath25/Makefile
-+++ b/arch/mips/ath25/Makefile
-@@ -9,5 +9,8 @@
- #
-
- obj-y += board.o prom.o devices.o
-+
-+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-+
- obj-$(CONFIG_SOC_AR5312) += ar5312.o
- obj-$(CONFIG_SOC_AR2315) += ar2315.o
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -106,6 +106,7 @@ config ATH25
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_HAS_EARLY_PRINTK
- help
- Support for Atheros AR231x and Atheros AR531x based boards
-
+++ /dev/null
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
- obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
- ops-bcm63xx.o
- obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
-+obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
- obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
- obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
- obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
---- /dev/null
-+++ b/arch/mips/pci/pci-ar2315.c
-@@ -0,0 +1,511 @@
-+/*
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+/**
-+ * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
-+ * and interrupt. PCI interface supports MMIO access method, but does not
-+ * seem to support I/O ports.
-+ *
-+ * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
-+ * a memory read/write command on the PCI bus. 30 LSBs of address on
-+ * the bus are taken from memory read/write request and 2 MSBs are
-+ * determined by PCI unit configuration.
-+ *
-+ * To work with the configuration space instead of memory is necessary set
-+ * the CFG_SEL bit in the PCI_MISC_CONFIG register.
-+ *
-+ * Devices on the bus can perform DMA requests via chip BAR1. PCI host
-+ * controller BARs are programmend as if an external device is programmed.
-+ * Which means that during configuration, IDSEL pin of the chip should be
-+ * asserted.
-+ *
-+ * We know (and support) only one board that uses the PCI interface -
-+ * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
-+ * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
-+ * and IDSEL pin of AR2315 is connected to AD[16] line.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/platform_device.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/delay.h>
-+#include <linux/bitops.h>
-+#include <linux/irq.h>
-+#include <linux/irqdomain.h>
-+#include <linux/io.h>
-+#include <asm/paccess.h>
-+
-+/*
-+ * PCI Bus Interface Registers
-+ */
-+#define AR2315_PCI_1MS_REG 0x0008
-+
-+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
-+
-+#define AR2315_PCI_MISC_CONFIG 0x000c
-+
-+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
-+#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
-+#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
-+#define AR2315_PCIMISC_RST_MODE 0x00000030
-+#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
-+#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
-+#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
-+#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
-+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
-+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
-+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
-+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
-+ * disable */
-+
-+#define AR2315_PCI_OUT_TSTAMP 0x0010
-+
-+#define AR2315_PCI_UNCACHE_CFG 0x0014
-+
-+#define AR2315_PCI_IN_EN 0x0100
-+
-+#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
-+#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
-+#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
-+#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
-+
-+#define AR2315_PCI_IN_DIS 0x0104
-+
-+#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
-+#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
-+#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
-+#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
-+
-+#define AR2315_PCI_IN_PTR 0x0200
-+
-+#define AR2315_PCI_OUT_EN 0x0400
-+
-+#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
-+
-+#define AR2315_PCI_OUT_DIS 0x0404
-+
-+#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
-+
-+#define AR2315_PCI_OUT_PTR 0x0408
-+
-+/* PCI interrupt status (write one to clear) */
-+#define AR2315_PCI_ISR 0x0500
-+
-+#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
-+#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
-+#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
-+#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
-+#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
-+#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
-+#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
-+#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
-+#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
-+#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
-+#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
-+#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
-+
-+/* PCI interrupt mask */
-+#define AR2315_PCI_IMR 0x0504
-+
-+/* Global PCI interrupt enable */
-+#define AR2315_PCI_IER 0x0508
-+
-+#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
-+#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
-+
-+#define AR2315_PCI_HOST_IN_EN 0x0800
-+#define AR2315_PCI_HOST_IN_DIS 0x0804
-+#define AR2315_PCI_HOST_IN_PTR 0x0810
-+#define AR2315_PCI_HOST_OUT_EN 0x0900
-+#define AR2315_PCI_HOST_OUT_DIS 0x0904
-+#define AR2315_PCI_HOST_OUT_PTR 0x0908
-+
-+/*
-+ * PCI interrupts, which share IP5
-+ * Keep ordered according to AR2315_PCI_INT_XXX bits
-+ */
-+#define AR2315_PCI_IRQ_EXT 25
-+#define AR2315_PCI_IRQ_ABORT 26
-+#define AR2315_PCI_IRQ_COUNT 27
-+
-+/* Arbitrary size of memory region to access the configuration space */
-+#define AR2315_PCI_CFG_SIZE 0x00100000
-+
-+#define AR2315_PCI_HOST_SLOT 3
-+#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
-+
-+/* ??? access BAR */
-+#define AR2315_PCI_HOST_MBAR0 0x10000000
-+/* RAM access BAR */
-+#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
-+/* ??? access BAR */
-+#define AR2315_PCI_HOST_MBAR2 0x30000000
-+
-+struct ar2315_pci_ctrl {
-+ void __iomem *cfg_mem;
-+ void __iomem *mmr_mem;
-+ unsigned irq;
-+ unsigned irq_ext;
-+ struct irq_domain *domain;
-+ struct pci_controller pci_ctrl;
-+ struct resource mem_res;
-+ struct resource io_res;
-+};
-+
-+static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
-+{
-+ struct pci_controller *hose = bus->sysdata;
-+
-+ return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
-+}
-+
-+static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
-+{
-+ return __raw_readl(apc->mmr_mem + reg);
-+}
-+
-+static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
-+ u32 val)
-+{
-+ __raw_writel(val, apc->mmr_mem + reg);
-+}
-+
-+static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
-+ u32 mask, u32 val)
-+{
-+ u32 ret = ar2315_pci_reg_read(apc, reg);
-+
-+ ret &= ~mask;
-+ ret |= val;
-+ ar2315_pci_reg_write(apc, reg, ret);
-+}
-+
-+static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
-+ int where, int size, u32 *ptr, bool write)
-+{
-+ int func = PCI_FUNC(devfn);
-+ int dev = PCI_SLOT(devfn);
-+ u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
-+ u32 mask = 0xffffffff >> 8 * (4 - size);
-+ u32 sh = (where & 3) * 8;
-+ u32 value, isr;
-+
-+ /* Prevent access past the remapped area */
-+ if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ /* Clear pending errors */
-+ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
-+ /* Select Configuration access */
-+ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
-+ AR2315_PCIMISC_CFG_SEL);
-+
-+ mb(); /* PCI must see space change before we begin */
-+
-+ value = __raw_readl(apc->cfg_mem + addr);
-+
-+ isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
-+
-+ if (isr & AR2315_PCI_INT_ABORT)
-+ goto exit_err;
-+
-+ if (write) {
-+ value = (value & ~(mask << sh)) | *ptr << sh;
-+ __raw_writel(value, apc->cfg_mem + addr);
-+ isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
-+ if (isr & AR2315_PCI_INT_ABORT)
-+ goto exit_err;
-+ } else {
-+ *ptr = (value >> sh) & mask;
-+ }
-+
-+ goto exit;
-+
-+exit_err:
-+ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
-+ if (!write)
-+ *ptr = 0xffffffff;
-+
-+exit:
-+ /* Select Memory access */
-+ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
-+ 0);
-+
-+ return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
-+ PCIBIOS_SUCCESSFUL;
-+}
-+
-+static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
-+ unsigned devfn, int where, u32 *val)
-+{
-+ return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
-+ false);
-+}
-+
-+static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
-+ unsigned devfn, int where, u32 val)
-+{
-+ return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
-+ true);
-+}
-+
-+static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
-+ int size, u32 *value)
-+{
-+ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
-+
-+ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
-+}
-+
-+static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
-+ int size, u32 value)
-+{
-+ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
-+
-+ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
-+}
-+
-+static struct pci_ops ar2315_pci_ops = {
-+ .read = ar2315_pci_cfg_read,
-+ .write = ar2315_pci_cfg_write,
-+};
-+
-+static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
-+{
-+ unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
-+ int res;
-+ u32 id;
-+
-+ res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
-+ if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
-+ return -ENODEV;
-+
-+ /* Program MBARs */
-+ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
-+ AR2315_PCI_HOST_MBAR0);
-+ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
-+ AR2315_PCI_HOST_MBAR1);
-+ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
-+ AR2315_PCI_HOST_MBAR2);
-+
-+ /* Run */
-+ ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
-+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
-+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
-+ PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
-+
-+ return 0;
-+}
-+
-+static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
-+{
-+ struct ar2315_pci_ctrl *apc = irq_get_handler_data(irq);
-+ u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
-+ ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
-+ unsigned pci_irq = 0;
-+
-+ if (pending)
-+ pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
-+
-+ if (pci_irq)
-+ generic_handle_irq(pci_irq);
-+ else
-+ spurious_interrupt();
-+}
-+
-+static void ar2315_pci_irq_mask(struct irq_data *d)
-+{
-+ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
-+
-+ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
-+}
-+
-+static void ar2315_pci_irq_mask_ack(struct irq_data *d)
-+{
-+ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
-+ u32 m = BIT(d->hwirq);
-+
-+ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
-+ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
-+}
-+
-+static void ar2315_pci_irq_unmask(struct irq_data *d)
-+{
-+ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
-+
-+ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
-+}
-+
-+static struct irq_chip ar2315_pci_irq_chip = {
-+ .name = "AR2315-PCI",
-+ .irq_mask = ar2315_pci_irq_mask,
-+ .irq_mask_ack = ar2315_pci_irq_mask_ack,
-+ .irq_unmask = ar2315_pci_irq_unmask,
-+};
-+
-+static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
-+ irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
-+ irq_set_chip_data(irq, d->host_data);
-+ return 0;
-+}
-+
-+static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
-+ .map = ar2315_pci_irq_map,
-+};
-+
-+static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
-+{
-+ ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
-+ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
-+ AR2315_PCI_INT_EXT), 0);
-+
-+ apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
-+
-+ irq_set_chained_handler(apc->irq, ar2315_pci_irq_handler);
-+ irq_set_handler_data(apc->irq, apc);
-+
-+ /* Clear any pending Abort or external Interrupts
-+ * and enable interrupt processing */
-+ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
-+ AR2315_PCI_INT_EXT);
-+ ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
-+}
-+
-+static int ar2315_pci_probe(struct platform_device *pdev)
-+{
-+ struct ar2315_pci_ctrl *apc;
-+ struct device *dev = &pdev->dev;
-+ struct resource *res;
-+ int irq, err;
-+
-+ apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
-+ if (!apc)
-+ return -ENOMEM;
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0)
-+ return -EINVAL;
-+ apc->irq = irq;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+ "ar2315-pci-ctrl");
-+ apc->mmr_mem = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(apc->mmr_mem))
-+ return PTR_ERR(apc->mmr_mem);
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+ "ar2315-pci-ext");
-+ if (!res)
-+ return -EINVAL;
-+
-+ apc->mem_res.name = "AR2315 PCI mem space";
-+ apc->mem_res.parent = res;
-+ apc->mem_res.start = res->start;
-+ apc->mem_res.end = res->end;
-+ apc->mem_res.flags = IORESOURCE_MEM;
-+
-+ /* Remap PCI config space */
-+ apc->cfg_mem = devm_ioremap_nocache(dev, res->start,
-+ AR2315_PCI_CFG_SIZE);
-+ if (!apc->cfg_mem) {
-+ dev_err(dev, "failed to remap PCI config space\n");
-+ return -ENOMEM;
-+ }
-+
-+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
-+ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
-+ AR2315_PCIMISC_RST_MODE,
-+ AR2315_PCIRST_LOW);
-+ msleep(100);
-+
-+ /* Bring the PCI out of reset */
-+ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
-+ AR2315_PCIMISC_RST_MODE,
-+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
-+
-+ ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
-+ 0x1E | /* 1GB uncached */
-+ (1 << 5) | /* Enable uncached */
-+ (0x2 << 30) /* Base: 0x80000000 */);
-+ ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
-+
-+ msleep(500);
-+
-+ err = ar2315_pci_host_setup(apc);
-+ if (err)
-+ return err;
-+
-+ apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
-+ &ar2315_pci_irq_domain_ops, apc);
-+ if (!apc->domain) {
-+ dev_err(dev, "failed to add IRQ domain\n");
-+ return -ENOMEM;
-+ }
-+
-+ ar2315_pci_irq_init(apc);
-+
-+ /* PCI controller does not support I/O ports */
-+ apc->io_res.name = "AR2315 IO space";
-+ apc->io_res.start = 0;
-+ apc->io_res.end = 0;
-+ apc->io_res.flags = IORESOURCE_IO,
-+
-+ apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
-+ apc->pci_ctrl.mem_resource = &apc->mem_res,
-+ apc->pci_ctrl.io_resource = &apc->io_res,
-+
-+ register_pci_controller(&apc->pci_ctrl);
-+
-+ dev_info(dev, "register PCI controller\n");
-+
-+ return 0;
-+}
-+
-+static struct platform_driver ar2315_pci_driver = {
-+ .probe = ar2315_pci_probe,
-+ .driver = {
-+ .name = "ar2315-pci",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init ar2315_pci_init(void)
-+{
-+ return platform_driver_register(&ar2315_pci_driver);
-+}
-+arch_initcall(ar2315_pci_init);
-+
-+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
-+
-+ return slot ? 0 : apc->irq_ext;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return 0;
-+}
---- a/arch/mips/ath25/Kconfig
-+++ b/arch/mips/ath25/Kconfig
-@@ -7,3 +7,10 @@ config SOC_AR2315
- bool "Atheros AR2315+ SoC support"
- depends on ATH25
- default y
-+
-+config PCI_AR2315
-+ bool "Atheros AR2315 PCI controller support"
-+ depends on SOC_AR2315
-+ select HW_HAS_PCI
-+ select PCI
-+ default y
---- a/arch/mips/ath25/ar2315.c
-+++ b/arch/mips/ath25/ar2315.c
-@@ -134,6 +134,10 @@ static void ar2315_irq_dispatch(void)
-
- if (pending & CAUSEF_IP3)
- do_IRQ(AR2315_IRQ_WLAN0);
-+#ifdef CONFIG_PCI_AR2315
-+ else if (pending & CAUSEF_IP5)
-+ do_IRQ(AR2315_IRQ_LCBUS_PCI);
-+#endif
- else if (pending & CAUSEF_IP2)
- do_IRQ(AR2315_IRQ_MISC);
- else if (pending & CAUSEF_IP7)
-@@ -299,10 +303,62 @@ void __init ar2315_plat_mem_setup(void)
- _machine_restart = ar2315_restart;
- }
-
-+#ifdef CONFIG_PCI_AR2315
-+static struct resource ar2315_pci_res[] = {
-+ {
-+ .name = "ar2315-pci-ctrl",
-+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_PCI_BASE,
-+ .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
-+ },
-+ {
-+ .name = "ar2315-pci-ext",
-+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_PCI_EXT_BASE,
-+ .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
-+ },
-+ {
-+ .name = "ar2315-pci",
-+ .flags = IORESOURCE_IRQ,
-+ .start = AR2315_IRQ_LCBUS_PCI,
-+ .end = AR2315_IRQ_LCBUS_PCI,
-+ },
-+};
-+#endif
-+
- void __init ar2315_arch_init(void)
- {
- unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
- AR2315_MISC_IRQ_UART0);
-
- ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
-+
-+#ifdef CONFIG_PCI_AR2315
-+ if (ath25_soc == ATH25_SOC_AR2315) {
-+ /* Reset PCI DMA logic */
-+ ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
-+ msleep(20);
-+ ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
-+ msleep(20);
-+
-+ /* Configure endians */
-+ ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
-+ AR2315_CONFIG_PCIAHB_BRIDGE);
-+
-+ /* Configure as PCI host with DMA */
-+ ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
-+ (AR2315_PCICLK_IN_FREQ_DIV_6 <<
-+ AR2315_PCICLK_DIV_S));
-+ ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
-+ ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
-+ AR2315_IF_MASK, AR2315_IF_PCI |
-+ AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
-+ (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
-+ AR2315_IF_PCI_CLK_SHIFT));
-+
-+ platform_device_register_simple("ar2315-pci", -1,
-+ ar2315_pci_res,
-+ ARRAY_SIZE(ar2315_pci_res));
-+ }
-+#endif
- }
+++ /dev/null
---- a/arch/mips/ath25/Kconfig
-+++ b/arch/mips/ath25/Kconfig
-@@ -1,6 +1,7 @@
- config SOC_AR5312
- bool "Atheros AR5312/AR2312+ SoC support"
- depends on ATH25
-+ select GPIO_AR5312
- default y
-
- config SOC_AR2315
---- a/arch/mips/ath25/ar5312.c
-+++ b/arch/mips/ath25/ar5312.c
-@@ -22,6 +22,7 @@
- #include <linux/platform_device.h>
- #include <linux/mtd/physmap.h>
- #include <linux/reboot.h>
-+#include <linux/gpio.h>
- #include <asm/bootinfo.h>
- #include <asm/reboot.h>
- #include <asm/time.h>
-@@ -180,6 +181,22 @@ static struct platform_device ar5312_phy
- .num_resources = 1,
- };
-
-+static struct resource ar5312_gpio_res[] = {
-+ {
-+ .name = "ar5312-gpio",
-+ .flags = IORESOURCE_MEM,
-+ .start = AR5312_GPIO_BASE,
-+ .end = AR5312_GPIO_BASE + AR5312_GPIO_SIZE - 1,
-+ },
-+};
-+
-+static struct platform_device ar5312_gpio = {
-+ .name = "ar5312-gpio",
-+ .id = -1,
-+ .resource = ar5312_gpio_res,
-+ .num_resources = ARRAY_SIZE(ar5312_gpio_res),
-+};
-+
- static void __init ar5312_flash_init(void)
- {
- void __iomem *flashctl_base;
-@@ -247,6 +264,8 @@ void __init ar5312_init_devices(void)
-
- platform_device_register(&ar5312_physmap_flash);
-
-+ platform_device_register(&ar5312_gpio);
-+
- switch (ath25_soc) {
- case ATH25_SOC_AR5312:
- if (!ath25_board.radio)
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -112,6 +112,13 @@ config GPIO_MAX730X
-
- comment "Memory mapped GPIO drivers:"
-
-+config GPIO_AR5312
-+ bool "AR5312 SoC GPIO support"
-+ default y if SOC_AR5312
-+ depends on SOC_AR5312
-+ help
-+ Say yes here to enable GPIO support for Atheros AR5312/AR2312+ SoCs.
-+
- config GPIO_CLPS711X
- tristate "CLPS711X GPIO support"
- depends on ARCH_CLPS711X || COMPILE_TEST
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
- obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
- obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
- obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
-+obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
- obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
- obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
- obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
---- /dev/null
-+++ b/drivers/gpio/gpio-ar5312.c
-@@ -0,0 +1,121 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
-+ * Copyright (C) 2006 FON Technology, SL.
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
-+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/gpio.h>
-+
-+#define DRIVER_NAME "ar5312-gpio"
-+
-+#define AR5312_GPIO_DO 0x00 /* output register */
-+#define AR5312_GPIO_DI 0x04 /* intput register */
-+#define AR5312_GPIO_CR 0x08 /* control register */
-+
-+#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
-+#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
-+#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
-+#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
-+#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
-+
-+#define AR5312_GPIO_NUM 8
-+
-+static void __iomem *ar5312_mem;
-+
-+static inline u32 ar5312_gpio_reg_read(unsigned reg)
-+{
-+ return __raw_readl(ar5312_mem + reg);
-+}
-+
-+static inline void ar5312_gpio_reg_write(unsigned reg, u32 val)
-+{
-+ __raw_writel(val, ar5312_mem + reg);
-+}
-+
-+static inline void ar5312_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
-+{
-+ ar5312_gpio_reg_write(reg, (ar5312_gpio_reg_read(reg) & ~mask) | val);
-+}
-+
-+static int ar5312_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
-+{
-+ return (ar5312_gpio_reg_read(AR5312_GPIO_DI) >> gpio) & 1;
-+}
-+
-+static void ar5312_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
-+{
-+ u32 reg = ar5312_gpio_reg_read(AR5312_GPIO_DO);
-+
-+ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
-+ ar5312_gpio_reg_write(AR5312_GPIO_DO, reg);
-+}
-+
-+static int ar5312_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
-+{
-+ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 0, 1 << gpio);
-+ return 0;
-+}
-+
-+static int ar5312_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
-+{
-+ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 1 << gpio, 0);
-+ ar5312_gpio_set_val(chip, gpio, val);
-+ return 0;
-+}
-+
-+static struct gpio_chip ar5312_gpio_chip = {
-+ .label = DRIVER_NAME,
-+ .direction_input = ar5312_gpio_dir_in,
-+ .direction_output = ar5312_gpio_dir_out,
-+ .set = ar5312_gpio_set_val,
-+ .get = ar5312_gpio_get_val,
-+ .base = 0,
-+ .ngpio = AR5312_GPIO_NUM,
-+};
-+
-+static int ar5312_gpio_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct resource *res;
-+ int ret;
-+
-+ if (ar5312_mem)
-+ return -EBUSY;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ ar5312_mem = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(ar5312_mem))
-+ return PTR_ERR(ar5312_mem);
-+
-+ ar5312_gpio_chip.dev = dev;
-+ ret = gpiochip_add(&ar5312_gpio_chip);
-+ if (ret) {
-+ dev_err(dev, "failed to add gpiochip\n");
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static struct platform_driver ar5312_gpio_driver = {
-+ .probe = ar5312_gpio_probe,
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ }
-+};
-+
-+static int __init ar5312_gpio_init(void)
-+{
-+ return platform_driver_register(&ar5312_gpio_driver);
-+}
-+subsys_initcall(ar5312_gpio_init);
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -107,6 +107,7 @@ config ATH25
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_HAS_EARLY_PRINTK
-+ select ARCH_REQUIRE_GPIOLIB
- help
- Support for Atheros AR231x and Atheros AR531x based boards
-
+++ /dev/null
---- a/arch/mips/ath25/Kconfig
-+++ b/arch/mips/ath25/Kconfig
-@@ -7,6 +7,7 @@ config SOC_AR5312
- config SOC_AR2315
- bool "Atheros AR2315+ SoC support"
- depends on ATH25
-+ select GPIO_AR2315
- default y
-
- config PCI_AR2315
---- a/arch/mips/ath25/ar2315.c
-+++ b/arch/mips/ath25/ar2315.c
-@@ -21,6 +21,8 @@
- #include <linux/interrupt.h>
- #include <linux/platform_device.h>
- #include <linux/reboot.h>
-+#include <linux/delay.h>
-+#include <linux/gpio.h>
- #include <asm/bootinfo.h>
- #include <asm/reboot.h>
- #include <asm/time.h>
-@@ -167,11 +169,42 @@ void __init ar2315_arch_init_irq(void)
- ar2315_misc_irq_domain = domain;
- }
-
-+static struct resource ar2315_gpio_res[] = {
-+ {
-+ .name = "ar2315-gpio",
-+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_RST_BASE + AR2315_GPIO,
-+ .end = AR2315_RST_BASE + AR2315_GPIO + 0x10 - 1,
-+ },
-+ {
-+ .name = "ar2315-gpio",
-+ .flags = IORESOURCE_IRQ,
-+ },
-+ {
-+ .name = "ar2315-gpio-irq-base",
-+ .flags = IORESOURCE_IRQ,
-+ .start = AR231X_GPIO_IRQ_BASE,
-+ .end = AR231X_GPIO_IRQ_BASE,
-+ }
-+};
-+
-+static struct platform_device ar2315_gpio = {
-+ .id = -1,
-+ .name = "ar2315-gpio",
-+ .resource = ar2315_gpio_res,
-+ .num_resources = ARRAY_SIZE(ar2315_gpio_res)
-+};
-+
- void __init ar2315_init_devices(void)
- {
- /* Find board configuration */
- ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
-
-+ ar2315_gpio_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
-+ AR2315_MISC_IRQ_GPIO);
-+ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
-+ platform_device_register(&ar2315_gpio);
-+
- ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
- }
-
-@@ -187,8 +220,8 @@ static void ar2315_restart(char *command
- /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
- * a workaround. Give it some time to attempt a gpio based hardware
- * reset (atheros reference design workaround) */
--
-- /* TODO: implement the GPIO reset workaround */
-+ gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
-+ mdelay(100);
-
- /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
- * workaround. Attempt to jump to the mips reset location -
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -112,6 +112,13 @@ config GPIO_MAX730X
-
- comment "Memory mapped GPIO drivers:"
-
-+config GPIO_AR2315
-+ bool "AR2315 SoC GPIO support"
-+ default y if SOC_AR2315
-+ depends on SOC_AR2315
-+ help
-+ Say yes here to enable GPIO support for Atheros AR2315+ SoCs.
-+
- config GPIO_AR5312
- bool "AR5312 SoC GPIO support"
- default y if SOC_AR5312
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
- obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
- obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
- obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
-+obj-$(CONFIG_GPIO_AR2315) += gpio-ar2315.o
- obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
- obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
- obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
---- /dev/null
-+++ b/drivers/gpio/gpio-ar2315.c
-@@ -0,0 +1,233 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
-+ * Copyright (C) 2006 FON Technology, SL.
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/gpio.h>
-+#include <linux/irq.h>
-+
-+#define DRIVER_NAME "ar2315-gpio"
-+
-+#define AR2315_GPIO_DI 0x0000
-+#define AR2315_GPIO_DO 0x0008
-+#define AR2315_GPIO_DIR 0x0010
-+#define AR2315_GPIO_INT 0x0018
-+
-+#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
-+#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
-+#define AR2315_GPIO_DIR_I(x) (0) /* input */
-+
-+#define AR2315_GPIO_INT_NUM_M 0x3F /* mask for GPIO num */
-+#define AR2315_GPIO_INT_TRIG(x) ((x) << 6) /* interrupt trigger */
-+#define AR2315_GPIO_INT_TRIG_M (0x3 << 6) /* mask for int trig */
-+
-+#define AR2315_GPIO_INT_TRIG_OFF 0 /* Triggerring off */
-+#define AR2315_GPIO_INT_TRIG_LOW 1 /* Low Level Triggered */
-+#define AR2315_GPIO_INT_TRIG_HIGH 2 /* High Level Triggered */
-+#define AR2315_GPIO_INT_TRIG_EDGE 3 /* Edge Triggered */
-+
-+#define AR2315_GPIO_NUM 22
-+
-+static u32 ar2315_gpio_intmask;
-+static u32 ar2315_gpio_intval;
-+static unsigned ar2315_gpio_irq_base;
-+static void __iomem *ar2315_mem;
-+
-+static inline u32 ar2315_gpio_reg_read(unsigned reg)
-+{
-+ return __raw_readl(ar2315_mem + reg);
-+}
-+
-+static inline void ar2315_gpio_reg_write(unsigned reg, u32 val)
-+{
-+ __raw_writel(val, ar2315_mem + reg);
-+}
-+
-+static inline void ar2315_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
-+{
-+ ar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val);
-+}
-+
-+static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
-+{
-+ u32 pend;
-+ int bit = -1;
-+
-+ /* only do one gpio interrupt at a time */
-+ pend = ar2315_gpio_reg_read(AR2315_GPIO_DI);
-+ pend ^= ar2315_gpio_intval;
-+ pend &= ar2315_gpio_intmask;
-+
-+ if (pend) {
-+ bit = fls(pend) - 1;
-+ pend &= ~(1 << bit);
-+ ar2315_gpio_intval ^= (1 << bit);
-+ }
-+
-+ /* Enable interrupt with edge detection */
-+ if ((ar2315_gpio_reg_read(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
-+ AR2315_GPIO_DIR_I(bit))
-+ return;
-+
-+ if (bit >= 0)
-+ generic_handle_irq(ar2315_gpio_irq_base + bit);
-+}
-+
-+static void ar2315_gpio_int_setup(unsigned gpio, int trig)
-+{
-+ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_INT);
-+
-+ reg &= ~(AR2315_GPIO_INT_NUM_M | AR2315_GPIO_INT_TRIG_M);
-+ reg |= gpio | AR2315_GPIO_INT_TRIG(trig);
-+ ar2315_gpio_reg_write(AR2315_GPIO_INT, reg);
-+}
-+
-+static void ar2315_gpio_irq_unmask(struct irq_data *d)
-+{
-+ unsigned gpio = d->irq - ar2315_gpio_irq_base;
-+ u32 dir = ar2315_gpio_reg_read(AR2315_GPIO_DIR);
-+
-+ /* Enable interrupt with edge detection */
-+ if ((dir & AR2315_GPIO_DIR_M(gpio)) != AR2315_GPIO_DIR_I(gpio))
-+ return;
-+
-+ ar2315_gpio_intmask |= (1 << gpio);
-+ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_EDGE);
-+}
-+
-+static void ar2315_gpio_irq_mask(struct irq_data *d)
-+{
-+ unsigned gpio = d->irq - ar2315_gpio_irq_base;
-+
-+ /* Disable interrupt */
-+ ar2315_gpio_intmask &= ~(1 << gpio);
-+ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_OFF);
-+}
-+
-+static struct irq_chip ar2315_gpio_irq_chip = {
-+ .name = DRIVER_NAME,
-+ .irq_unmask = ar2315_gpio_irq_unmask,
-+ .irq_mask = ar2315_gpio_irq_mask,
-+};
-+
-+static void ar2315_gpio_irq_init(unsigned irq)
-+{
-+ unsigned i;
-+
-+ ar2315_gpio_intval = ar2315_gpio_reg_read(AR2315_GPIO_DI);
-+ for (i = 0; i < AR2315_GPIO_NUM; i++) {
-+ unsigned _irq = ar2315_gpio_irq_base + i;
-+
-+ irq_set_chip_and_handler(_irq, &ar2315_gpio_irq_chip,
-+ handle_level_irq);
-+ }
-+ irq_set_chained_handler(irq, ar2315_gpio_irq_handler);
-+}
-+
-+static int ar2315_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
-+{
-+ return (ar2315_gpio_reg_read(AR2315_GPIO_DI) >> gpio) & 1;
-+}
-+
-+static void ar2315_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
-+{
-+ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_DO);
-+
-+ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
-+ ar2315_gpio_reg_write(AR2315_GPIO_DO, reg);
-+}
-+
-+static int ar2315_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
-+{
-+ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 1 << gpio, 0);
-+ return 0;
-+}
-+
-+static int ar2315_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
-+{
-+ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 0, 1 << gpio);
-+ ar2315_gpio_set_val(chip, gpio, val);
-+ return 0;
-+}
-+
-+static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-+{
-+ return ar2315_gpio_irq_base + gpio;
-+}
-+
-+static struct gpio_chip ar2315_gpio_chip = {
-+ .label = DRIVER_NAME,
-+ .direction_input = ar2315_gpio_dir_in,
-+ .direction_output = ar2315_gpio_dir_out,
-+ .set = ar2315_gpio_set_val,
-+ .get = ar2315_gpio_get_val,
-+ .to_irq = ar2315_gpio_to_irq,
-+ .base = 0,
-+ .ngpio = AR2315_GPIO_NUM,
-+};
-+
-+static int ar2315_gpio_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct resource *res;
-+ unsigned irq;
-+ int ret;
-+
-+ if (ar2315_mem)
-+ return -EBUSY;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
-+ "ar2315-gpio-irq-base");
-+ if (!res) {
-+ dev_err(dev, "not found GPIO IRQ base\n");
-+ return -ENXIO;
-+ }
-+ ar2315_gpio_irq_base = res->start;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, DRIVER_NAME);
-+ if (!res) {
-+ dev_err(dev, "not found IRQ number\n");
-+ return -ENXIO;
-+ }
-+ irq = res->start;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, DRIVER_NAME);
-+ ar2315_mem = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(ar2315_mem))
-+ return PTR_ERR(ar2315_mem);
-+
-+ ar2315_gpio_chip.dev = dev;
-+ ret = gpiochip_add(&ar2315_gpio_chip);
-+ if (ret) {
-+ dev_err(dev, "failed to add gpiochip\n");
-+ return ret;
-+ }
-+
-+ ar2315_gpio_irq_init(irq);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver ar2315_gpio_driver = {
-+ .probe = ar2315_gpio_probe,
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ }
-+};
-+
-+static int __init ar2315_gpio_init(void)
-+{
-+ return platform_driver_register(&ar2315_gpio_driver);
-+}
-+subsys_initcall(ar2315_gpio_init);
---- a/arch/mips/ath25/devices.h
-+++ b/arch/mips/ath25/devices.h
-@@ -3,6 +3,11 @@
-
- #include <linux/cpu.h>
-
-+#define AR231X_GPIO_IRQ_BASE 0x30
-+
-+/* GPIO number for AR2315/16 reset issue workaround */
-+#define AR2315_RESET_GPIO 5
-+
- #define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
-
- #define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
---- a/arch/mips/ath25/ar2315_regs.h
-+++ b/arch/mips/ath25/ar2315_regs.h
-@@ -315,6 +315,9 @@
- #define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
- #define AR2315_MEM_CFG_BANKADDR_BITS_S 3
-
-+/* GPIO MMR base address */
-+#define AR2315_GPIO 0x0088
-+
- /*
- * Local Bus Interface Registers
- */
+++ /dev/null
---- a/drivers/net/ethernet/atheros/Makefile
-+++ b/drivers/net/ethernet/atheros/Makefile
-@@ -7,3 +7,4 @@ obj-$(CONFIG_ATL2) += atlx/
- obj-$(CONFIG_ATL1E) += atl1e/
- obj-$(CONFIG_ATL1C) += atl1c/
- obj-$(CONFIG_ALX) += alx/
-+obj-$(CONFIG_NET_AR231X) += ar231x/
---- a/drivers/net/ethernet/atheros/Kconfig
-+++ b/drivers/net/ethernet/atheros/Kconfig
-@@ -5,7 +5,7 @@
- config NET_VENDOR_ATHEROS
- bool "Atheros devices"
- default y
-- depends on PCI
-+ depends on (PCI || ATH25)
- ---help---
- If you have a network (Ethernet) card belonging to this class, say Y
- and read the Ethernet-HOWTO, available from
-@@ -80,4 +80,10 @@ config ALX
- To compile this driver as a module, choose M here. The module
- will be called alx.
-
-+config NET_AR231X
-+ tristate "Atheros AR231X built-in Ethernet support"
-+ depends on ATH25
-+ help
-+ Support for the AR231x/531x ethernet controller
-+
- endif # NET_VENDOR_ATHEROS
---- /dev/null
-+++ b/drivers/net/ethernet/atheros/ar231x/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_NET_AR231X) += ar231x.o
---- /dev/null
-+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
-@@ -0,0 +1,1206 @@
-+/*
-+ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
-+ *
-+ * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
-+ *
-+ * Thanks to Atheros for providing hardware and documentation
-+ * enabling me to write this driver.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * Additional credits:
-+ * This code is taken from John Taylor's Sibyte driver and then
-+ * modified for the AR2313.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/ioport.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/interrupt.h>
-+#include <linux/skbuff.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/mm.h>
-+#include <linux/mii.h>
-+#include <linux/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+
-+#define AR2313_MTU 1692
-+#define AR2313_PRIOS 1
-+#define AR2313_QUEUES (2*AR2313_PRIOS)
-+#define AR2313_DESCR_ENTRIES 64
-+
-+#ifndef min
-+#define min(a, b) (((a) < (b)) ? (a) : (b))
-+#endif
-+
-+#ifndef SMP_CACHE_BYTES
-+#define SMP_CACHE_BYTES L1_CACHE_BYTES
-+#endif
-+
-+#define AR2313_MBOX_SET_BIT 0x8
-+
-+#include "ar231x.h"
-+
-+/**
-+ * New interrupt handler strategy:
-+ *
-+ * An old interrupt handler worked using the traditional method of
-+ * replacing an skbuff with a new one when a packet arrives. However
-+ * the rx rings do not need to contain a static number of buffer
-+ * descriptors, thus it makes sense to move the memory allocation out
-+ * of the main interrupt handler and do it in a bottom half handler
-+ * and only allocate new buffers when the number of buffers in the
-+ * ring is below a certain threshold. In order to avoid starving the
-+ * NIC under heavy load it is however necessary to force allocation
-+ * when hitting a minimum threshold. The strategy for alloction is as
-+ * follows:
-+ *
-+ * RX_LOW_BUF_THRES - allocate buffers in the bottom half
-+ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
-+ * the buffers in the interrupt handler
-+ * RX_RING_THRES - maximum number of buffers in the rx ring
-+ *
-+ * One advantagous side effect of this allocation approach is that the
-+ * entire rx processing can be done without holding any spin lock
-+ * since the rx rings and registers are totally independent of the tx
-+ * ring and its registers. This of course includes the kmalloc's of
-+ * new skb's. Thus start_xmit can run in parallel with rx processing
-+ * and the memory allocation on SMP systems.
-+ *
-+ * Note that running the skb reallocation in a bottom half opens up
-+ * another can of races which needs to be handled properly. In
-+ * particular it can happen that the interrupt handler tries to run
-+ * the reallocation while the bottom half is either running on another
-+ * CPU or was interrupted on the same CPU. To get around this the
-+ * driver uses bitops to prevent the reallocation routines from being
-+ * reentered.
-+ *
-+ * TX handling can also be done without holding any spin lock, wheee
-+ * this is fun! since tx_csm is only written to by the interrupt
-+ * handler.
-+ */
-+
-+/**
-+ * Threshold values for RX buffer allocation - the low water marks for
-+ * when to start refilling the rings are set to 75% of the ring
-+ * sizes. It seems to make sense to refill the rings entirely from the
-+ * intrrupt handler once it gets below the panic threshold, that way
-+ * we don't risk that the refilling is moved to another CPU when the
-+ * one running the interrupt handler just got the slab code hot in its
-+ * cache.
-+ */
-+#define RX_RING_SIZE AR2313_DESCR_ENTRIES
-+#define RX_PANIC_THRES (RX_RING_SIZE/4)
-+#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
-+#define CRC_LEN 4
-+#define RX_OFFSET 2
-+
-+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
-+#define VLAN_HDR 4
-+#else
-+#define VLAN_HDR 0
-+#endif
-+
-+#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
-+ RX_OFFSET)
-+
-+#ifdef MODULE
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
-+MODULE_DESCRIPTION("AR231x Ethernet driver");
-+#endif
-+
-+#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
-+
-+/* prototypes */
-+static void ar231x_halt(struct net_device *dev);
-+static void rx_tasklet_func(unsigned long data);
-+static void rx_tasklet_cleanup(struct net_device *dev);
-+static void ar231x_multicast_list(struct net_device *dev);
-+static void ar231x_tx_timeout(struct net_device *dev);
-+
-+static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
-+static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
-+ u16 value);
-+static int ar231x_mdiobus_reset(struct mii_bus *bus);
-+static int ar231x_mdiobus_probe(struct net_device *dev);
-+static void ar231x_adjust_link(struct net_device *dev);
-+
-+#ifndef ERR
-+#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
-+#endif
-+
-+#ifdef CONFIG_NET_POLL_CONTROLLER
-+static void
-+ar231x_netpoll(struct net_device *dev)
-+{
-+ unsigned long flags;
-+
-+ local_irq_save(flags);
-+ ar231x_interrupt(dev->irq, dev);
-+ local_irq_restore(flags);
-+}
-+#endif
-+
-+static const struct net_device_ops ar231x_ops = {
-+ .ndo_open = ar231x_open,
-+ .ndo_stop = ar231x_close,
-+ .ndo_start_xmit = ar231x_start_xmit,
-+ .ndo_set_rx_mode = ar231x_multicast_list,
-+ .ndo_do_ioctl = ar231x_ioctl,
-+ .ndo_change_mtu = eth_change_mtu,
-+ .ndo_validate_addr = eth_validate_addr,
-+ .ndo_set_mac_address = eth_mac_addr,
-+ .ndo_tx_timeout = ar231x_tx_timeout,
-+#ifdef CONFIG_NET_POLL_CONTROLLER
-+ .ndo_poll_controller = ar231x_netpoll,
-+#endif
-+};
-+
-+static int ar231x_probe(struct platform_device *pdev)
-+{
-+ struct net_device *dev;
-+ struct ar231x_private *sp;
-+ struct resource *res;
-+ unsigned long ar_eth_base;
-+ char buf[64];
-+
-+ dev = alloc_etherdev(sizeof(struct ar231x_private));
-+
-+ if (dev == NULL) {
-+ printk(KERN_ERR
-+ "ar231x: Unable to allocate net_device structure!\n");
-+ return -ENOMEM;
-+ }
-+
-+ platform_set_drvdata(pdev, dev);
-+
-+ sp = netdev_priv(dev);
-+ sp->dev = dev;
-+ sp->cfg = pdev->dev.platform_data;
-+
-+ sprintf(buf, "eth%d_membase", pdev->id);
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
-+ if (!res)
-+ return -ENODEV;
-+
-+ sp->link = 0;
-+ ar_eth_base = res->start;
-+
-+ sprintf(buf, "eth%d_irq", pdev->id);
-+ dev->irq = platform_get_irq_byname(pdev, buf);
-+
-+ spin_lock_init(&sp->lock);
-+
-+ dev->features |= NETIF_F_HIGHDMA;
-+ dev->netdev_ops = &ar231x_ops;
-+
-+ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long)dev);
-+ tasklet_disable(&sp->rx_tasklet);
-+
-+ sp->eth_regs = ioremap_nocache(ar_eth_base, sizeof(*sp->eth_regs));
-+ if (!sp->eth_regs) {
-+ printk("Can't remap eth registers\n");
-+ return -ENXIO;
-+ }
-+
-+ /**
-+ * When there's only one MAC, PHY regs are typically on ENET0,
-+ * even though the MAC might be on ENET1.
-+ * So remap PHY regs separately.
-+ */
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth0_mii");
-+ if (!res) {
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+ "eth1_mii");
-+ if (!res)
-+ return -ENODEV;
-+ }
-+ sp->phy_regs = ioremap_nocache(res->start, resource_size(res));
-+ if (!sp->phy_regs) {
-+ printk("Can't remap phy registers\n");
-+ return -ENXIO;
-+ }
-+
-+ sp->dma_regs = ioremap_nocache(ar_eth_base + 0x1000,
-+ sizeof(*sp->dma_regs));
-+ if (!sp->dma_regs) {
-+ printk("Can't remap DMA registers\n");
-+ return -ENXIO;
-+ }
-+ dev->base_addr = ar_eth_base + 0x1000;
-+
-+ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
-+ sp->name[sizeof(sp->name) - 1] = '\0';
-+ memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
-+
-+ if (ar231x_init(dev)) {
-+ /* ar231x_init() calls ar231x_init_cleanup() on error */
-+ kfree(dev);
-+ return -ENODEV;
-+ }
-+
-+ if (register_netdev(dev)) {
-+ printk("%s: register_netdev failed\n", __func__);
-+ return -1;
-+ }
-+
-+ printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
-+ dev->irq);
-+
-+ sp->mii_bus = mdiobus_alloc();
-+ if (sp->mii_bus == NULL)
-+ return -1;
-+
-+ sp->mii_bus->priv = dev;
-+ sp->mii_bus->read = ar231x_mdiobus_read;
-+ sp->mii_bus->write = ar231x_mdiobus_write;
-+ sp->mii_bus->reset = ar231x_mdiobus_reset;
-+ sp->mii_bus->name = "ar231x_eth_mii";
-+ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
-+ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
-+ *sp->mii_bus->irq = PHY_POLL;
-+
-+ mdiobus_register(sp->mii_bus);
-+
-+ if (ar231x_mdiobus_probe(dev) != 0) {
-+ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
-+ rx_tasklet_cleanup(dev);
-+ ar231x_init_cleanup(dev);
-+ unregister_netdev(dev);
-+ kfree(dev);
-+ return -ENODEV;
-+ }
-+
-+ /* start link poll timer */
-+ ar231x_setup_timer(dev);
-+
-+ return 0;
-+}
-+
-+static void ar231x_multicast_list(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ unsigned int filter;
-+
-+ filter = sp->eth_regs->mac_control;
-+
-+ if (dev->flags & IFF_PROMISC)
-+ filter |= MAC_CONTROL_PR;
-+ else
-+ filter &= ~MAC_CONTROL_PR;
-+ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
-+ filter |= MAC_CONTROL_PM;
-+ else
-+ filter &= ~MAC_CONTROL_PM;
-+
-+ sp->eth_regs->mac_control = filter;
-+}
-+
-+static void rx_tasklet_cleanup(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+
-+ /**
-+ * Tasklet may be scheduled. Need to get it removed from the list
-+ * since we're about to free the struct.
-+ */
-+
-+ sp->unloading = 1;
-+ tasklet_enable(&sp->rx_tasklet);
-+ tasklet_kill(&sp->rx_tasklet);
-+}
-+
-+static int ar231x_remove(struct platform_device *pdev)
-+{
-+ struct net_device *dev = platform_get_drvdata(pdev);
-+ struct ar231x_private *sp = netdev_priv(dev);
-+
-+ rx_tasklet_cleanup(dev);
-+ ar231x_init_cleanup(dev);
-+ unregister_netdev(dev);
-+ mdiobus_unregister(sp->mii_bus);
-+ mdiobus_free(sp->mii_bus);
-+ kfree(dev);
-+ return 0;
-+}
-+
-+/**
-+ * Restart the AR2313 ethernet controller.
-+ */
-+static int ar231x_restart(struct net_device *dev)
-+{
-+ /* disable interrupts */
-+ disable_irq(dev->irq);
-+
-+ /* stop mac */
-+ ar231x_halt(dev);
-+
-+ /* initialize */
-+ ar231x_init(dev);
-+
-+ /* enable interrupts */
-+ enable_irq(dev->irq);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver ar231x_driver = {
-+ .driver.name = "ar231x-eth",
-+ .probe = ar231x_probe,
-+ .remove = ar231x_remove,
-+};
-+
-+module_platform_driver(ar231x_driver);
-+
-+static void ar231x_free_descriptors(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+
-+ if (sp->rx_ring != NULL) {
-+ kfree((void *)KSEG0ADDR(sp->rx_ring));
-+ sp->rx_ring = NULL;
-+ sp->tx_ring = NULL;
-+ }
-+}
-+
-+static int ar231x_allocate_descriptors(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ int size;
-+ int j;
-+ ar231x_descr_t *space;
-+
-+ if (sp->rx_ring != NULL) {
-+ printk("%s: already done.\n", __func__);
-+ return 0;
-+ }
-+
-+ size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
-+ space = kmalloc(size, GFP_KERNEL);
-+ if (space == NULL)
-+ return 1;
-+
-+ /* invalidate caches */
-+ dma_cache_inv((unsigned int)space, size);
-+
-+ /* now convert pointer to KSEG1 */
-+ space = (ar231x_descr_t *)KSEG1ADDR(space);
-+
-+ memset((void *)space, 0, size);
-+
-+ sp->rx_ring = space;
-+ space += AR2313_DESCR_ENTRIES;
-+
-+ sp->tx_ring = space;
-+ space += AR2313_DESCR_ENTRIES;
-+
-+ /* Initialize the transmit Descriptors */
-+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
-+ ar231x_descr_t *td = &sp->tx_ring[j];
-+
-+ td->status = 0;
-+ td->devcs = DMA_TX1_CHAINED;
-+ td->addr = 0;
-+ td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * Generic cleanup handling data allocated during init. Used when the
-+ * module is unloaded or if an error occurs during initialization
-+ */
-+static void ar231x_init_cleanup(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ struct sk_buff *skb;
-+ int j;
-+
-+ ar231x_free_descriptors(dev);
-+
-+ if (sp->eth_regs)
-+ iounmap((void *)sp->eth_regs);
-+ if (sp->dma_regs)
-+ iounmap((void *)sp->dma_regs);
-+ if (sp->phy_regs)
-+ iounmap((void *)sp->phy_regs);
-+
-+ if (sp->rx_skb) {
-+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
-+ skb = sp->rx_skb[j];
-+ if (skb) {
-+ sp->rx_skb[j] = NULL;
-+ dev_kfree_skb(skb);
-+ }
-+ }
-+ kfree(sp->rx_skb);
-+ sp->rx_skb = NULL;
-+ }
-+
-+ if (sp->tx_skb) {
-+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
-+ skb = sp->tx_skb[j];
-+ if (skb) {
-+ sp->tx_skb[j] = NULL;
-+ dev_kfree_skb(skb);
-+ }
-+ }
-+ kfree(sp->tx_skb);
-+ sp->tx_skb = NULL;
-+ }
-+}
-+
-+static int ar231x_setup_timer(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+
-+ init_timer(&sp->link_timer);
-+
-+ sp->link_timer.function = ar231x_link_timer_fn;
-+ sp->link_timer.data = (int)dev;
-+ sp->link_timer.expires = jiffies + HZ;
-+
-+ add_timer(&sp->link_timer);
-+ return 0;
-+}
-+
-+static void ar231x_link_timer_fn(unsigned long data)
-+{
-+ struct net_device *dev = (struct net_device *)data;
-+ struct ar231x_private *sp = netdev_priv(dev);
-+
-+ /**
-+ * See if the link status changed.
-+ * This was needed to make sure we set the PHY to the
-+ * autonegotiated value of half or full duplex.
-+ */
-+ ar231x_check_link(dev);
-+
-+ /**
-+ * Loop faster when we don't have link.
-+ * This was needed to speed up the AP bootstrap time.
-+ */
-+ if (sp->link == 0)
-+ mod_timer(&sp->link_timer, jiffies + HZ / 2);
-+ else
-+ mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
-+}
-+
-+static void ar231x_check_link(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ u16 phy_data;
-+
-+ phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
-+ if (sp->phy_data != phy_data) {
-+ if (phy_data & BMSR_LSTATUS) {
-+ /**
-+ * Link is present, ready link partner ability to
-+ * deterine duplexity.
-+ */
-+ int duplex = 0;
-+ u16 reg;
-+
-+ sp->link = 1;
-+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
-+ MII_BMCR);
-+ if (reg & BMCR_ANENABLE) {
-+ /* auto neg enabled */
-+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
-+ MII_LPA);
-+ duplex = reg & (LPA_100FULL | LPA_10FULL) ?
-+ 1 : 0;
-+ } else {
-+ /* no auto neg, just read duplex config */
-+ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
-+ }
-+
-+ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
-+ dev->name, (duplex) ? "full" : "half");
-+
-+ if (duplex) {
-+ /* full duplex */
-+ sp->eth_regs->mac_control =
-+ (sp->eth_regs->mac_control |
-+ MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
-+ } else {
-+ /* half duplex */
-+ sp->eth_regs->mac_control =
-+ (sp->eth_regs->mac_control |
-+ MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
-+ }
-+ } else {
-+ /* no link */
-+ sp->link = 0;
-+ }
-+ sp->phy_data = phy_data;
-+ }
-+}
-+
-+static int ar231x_reset_reg(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ unsigned int ethsal, ethsah;
-+ unsigned int flags;
-+
-+ sp->cfg->reset_set(sp->cfg->reset_mac);
-+ mdelay(10);
-+ sp->cfg->reset_clear(sp->cfg->reset_mac);
-+ mdelay(10);
-+ sp->cfg->reset_set(sp->cfg->reset_phy);
-+ mdelay(10);
-+ sp->cfg->reset_clear(sp->cfg->reset_phy);
-+ mdelay(10);
-+
-+ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
-+ mdelay(10);
-+ sp->dma_regs->bus_mode =
-+ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
-+
-+ /* enable interrupts */
-+ sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
-+ DMA_STATUS_RI | DMA_STATUS_TI |
-+ DMA_STATUS_FBE;
-+ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
-+ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
-+ sp->dma_regs->control =
-+ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
-+
-+ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
-+ sp->eth_regs->vlan_tag = (0x8100);
-+
-+ /* Enable Ethernet Interface */
-+ flags = (MAC_CONTROL_TE | /* transmit enable */
-+ MAC_CONTROL_PM | /* pass mcast */
-+ MAC_CONTROL_F | /* full duplex */
-+ MAC_CONTROL_HBD); /* heart beat disabled */
-+
-+ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
-+ flags |= MAC_CONTROL_PR;
-+ }
-+ sp->eth_regs->mac_control = flags;
-+
-+ /* Set all Ethernet station address registers to their initial values */
-+ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
-+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
-+
-+ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
-+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
-+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
-+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
-+
-+ sp->eth_regs->mac_addr[0] = ethsah;
-+ sp->eth_regs->mac_addr[1] = ethsal;
-+
-+ mdelay(10);
-+
-+ return 0;
-+}
-+
-+static int ar231x_init(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ int ecode = 0;
-+
-+ /* Allocate descriptors */
-+ if (ar231x_allocate_descriptors(dev)) {
-+ printk("%s: %s: ar231x_allocate_descriptors failed\n",
-+ dev->name, __func__);
-+ ecode = -EAGAIN;
-+ goto init_error;
-+ }
-+
-+ /* Get the memory for the skb rings */
-+ if (sp->rx_skb == NULL) {
-+ sp->rx_skb =
-+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
-+ GFP_KERNEL);
-+ if (!(sp->rx_skb)) {
-+ printk("%s: %s: rx_skb kmalloc failed\n",
-+ dev->name, __func__);
-+ ecode = -EAGAIN;
-+ goto init_error;
-+ }
-+ }
-+ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
-+
-+ if (sp->tx_skb == NULL) {
-+ sp->tx_skb =
-+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
-+ GFP_KERNEL);
-+ if (!(sp->tx_skb)) {
-+ printk("%s: %s: tx_skb kmalloc failed\n",
-+ dev->name, __func__);
-+ ecode = -EAGAIN;
-+ goto init_error;
-+ }
-+ }
-+ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
-+
-+ /**
-+ * Set tx_csm before we start receiving interrupts, otherwise
-+ * the interrupt handler might think it is supposed to process
-+ * tx ints before we are up and running, which may cause a null
-+ * pointer access in the int handler.
-+ */
-+ sp->rx_skbprd = 0;
-+ sp->cur_rx = 0;
-+ sp->tx_prd = 0;
-+ sp->tx_csm = 0;
-+
-+ /* Zero the stats before starting the interface */
-+ memset(&dev->stats, 0, sizeof(dev->stats));
-+
-+ /**
-+ * We load the ring here as there seem to be no way to tell the
-+ * firmware to wipe the ring without re-initializing it.
-+ */
-+ ar231x_load_rx_ring(dev, RX_RING_SIZE);
-+
-+ /* Init hardware */
-+ ar231x_reset_reg(dev);
-+
-+ /* Get the IRQ */
-+ ecode = request_irq(dev->irq, &ar231x_interrupt, IRQF_DISABLED,
-+ dev->name, dev);
-+ if (ecode) {
-+ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
-+ dev->name, __func__, dev->irq);
-+ goto init_error;
-+ }
-+
-+ tasklet_enable(&sp->rx_tasklet);
-+
-+ return 0;
-+
-+init_error:
-+ ar231x_init_cleanup(dev);
-+ return ecode;
-+}
-+
-+/**
-+ * Load the rx ring.
-+ *
-+ * Loading rings is safe without holding the spin lock since this is
-+ * done only before the device is enabled, thus no interrupts are
-+ * generated and by the interrupt handler/tasklet handler.
-+ */
-+static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ short i, idx;
-+
-+ idx = sp->rx_skbprd;
-+
-+ for (i = 0; i < nr_bufs; i++) {
-+ struct sk_buff *skb;
-+ ar231x_descr_t *rd;
-+
-+ if (sp->rx_skb[idx])
-+ break;
-+
-+ skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
-+ if (!skb) {
-+ printk("\n\n\n\n %s: No memory in system\n\n\n\n",
-+ __func__);
-+ break;
-+ }
-+
-+ /* Make sure IP header starts on a fresh cache line */
-+ skb->dev = dev;
-+ sp->rx_skb[idx] = skb;
-+
-+ rd = (ar231x_descr_t *)&sp->rx_ring[idx];
-+
-+ /* initialize dma descriptor */
-+ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
-+ DMA_RX1_CHAINED);
-+ rd->addr = virt_to_phys(skb->data);
-+ rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
-+ rd->status = DMA_RX_OWN;
-+
-+ idx = DSC_NEXT(idx);
-+ }
-+
-+ if (i)
-+ sp->rx_skbprd = idx;
-+}
-+
-+#define AR2313_MAX_PKTS_PER_CALL 64
-+
-+static int ar231x_rx_int(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ struct sk_buff *skb, *skb_new;
-+ ar231x_descr_t *rxdesc;
-+ unsigned int status;
-+ u32 idx;
-+ int pkts = 0;
-+ int rval;
-+
-+ idx = sp->cur_rx;
-+
-+ /* process at most the entire ring and then wait for another int */
-+ while (1) {
-+ rxdesc = &sp->rx_ring[idx];
-+ status = rxdesc->status;
-+
-+ if (status & DMA_RX_OWN) {
-+ /* SiByte owns descriptor or descr not yet filled in */
-+ rval = 0;
-+ break;
-+ }
-+
-+ if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
-+ rval = 1;
-+ break;
-+ }
-+
-+ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
-+ dev->stats.rx_errors++;
-+ dev->stats.rx_dropped++;
-+
-+ /* add statistics counters */
-+ if (status & DMA_RX_ERR_CRC)
-+ dev->stats.rx_crc_errors++;
-+ if (status & DMA_RX_ERR_COL)
-+ dev->stats.rx_over_errors++;
-+ if (status & DMA_RX_ERR_LENGTH)
-+ dev->stats.rx_length_errors++;
-+ if (status & DMA_RX_ERR_RUNT)
-+ dev->stats.rx_over_errors++;
-+ if (status & DMA_RX_ERR_DESC)
-+ dev->stats.rx_over_errors++;
-+
-+ } else {
-+ /* alloc new buffer. */
-+ skb_new = netdev_alloc_skb_ip_align(dev,
-+ AR2313_BUFSIZE);
-+ if (skb_new != NULL) {
-+ skb = sp->rx_skb[idx];
-+ /* set skb */
-+ skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
-+ 0x3fff) - CRC_LEN);
-+
-+ dev->stats.rx_bytes += skb->len;
-+ skb->protocol = eth_type_trans(skb, dev);
-+ /* pass the packet to upper layers */
-+ netif_rx(skb);
-+
-+ skb_new->dev = dev;
-+ /* reset descriptor's curr_addr */
-+ rxdesc->addr = virt_to_phys(skb_new->data);
-+
-+ dev->stats.rx_packets++;
-+ sp->rx_skb[idx] = skb_new;
-+ } else {
-+ dev->stats.rx_dropped++;
-+ }
-+ }
-+
-+ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
-+ DMA_RX1_CHAINED);
-+ rxdesc->status = DMA_RX_OWN;
-+
-+ idx = DSC_NEXT(idx);
-+ }
-+
-+ sp->cur_rx = idx;
-+
-+ return rval;
-+}
-+
-+static void ar231x_tx_int(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ u32 idx;
-+ struct sk_buff *skb;
-+ ar231x_descr_t *txdesc;
-+ unsigned int status = 0;
-+
-+ idx = sp->tx_csm;
-+
-+ while (idx != sp->tx_prd) {
-+ txdesc = &sp->tx_ring[idx];
-+ status = txdesc->status;
-+
-+ if (status & DMA_TX_OWN) {
-+ /* ar231x dma still owns descr */
-+ break;
-+ }
-+ /* done with this descriptor */
-+ dma_unmap_single(NULL, txdesc->addr,
-+ txdesc->devcs & DMA_TX1_BSIZE_MASK,
-+ DMA_TO_DEVICE);
-+ txdesc->status = 0;
-+
-+ if (status & DMA_TX_ERROR) {
-+ dev->stats.tx_errors++;
-+ dev->stats.tx_dropped++;
-+ if (status & DMA_TX_ERR_UNDER)
-+ dev->stats.tx_fifo_errors++;
-+ if (status & DMA_TX_ERR_HB)
-+ dev->stats.tx_heartbeat_errors++;
-+ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
-+ dev->stats.tx_carrier_errors++;
-+ if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
-+ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
-+ dev->stats.tx_aborted_errors++;
-+ } else {
-+ /* transmit OK */
-+ dev->stats.tx_packets++;
-+ }
-+
-+ skb = sp->tx_skb[idx];
-+ sp->tx_skb[idx] = NULL;
-+ idx = DSC_NEXT(idx);
-+ dev->stats.tx_bytes += skb->len;
-+ dev_kfree_skb_irq(skb);
-+ }
-+
-+ sp->tx_csm = idx;
-+}
-+
-+static void rx_tasklet_func(unsigned long data)
-+{
-+ struct net_device *dev = (struct net_device *)data;
-+ struct ar231x_private *sp = netdev_priv(dev);
-+
-+ if (sp->unloading)
-+ return;
-+
-+ if (ar231x_rx_int(dev)) {
-+ tasklet_hi_schedule(&sp->rx_tasklet);
-+ } else {
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&sp->lock, flags);
-+ sp->dma_regs->intr_ena |= DMA_STATUS_RI;
-+ spin_unlock_irqrestore(&sp->lock, flags);
-+ }
-+}
-+
-+static void rx_schedule(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+
-+ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
-+
-+ tasklet_hi_schedule(&sp->rx_tasklet);
-+}
-+
-+static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
-+{
-+ struct net_device *dev = (struct net_device *)dev_id;
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ unsigned int status, enabled;
-+
-+ /* clear interrupt */
-+ /* Don't clear RI bit if currently disabled */
-+ status = sp->dma_regs->status;
-+ enabled = sp->dma_regs->intr_ena;
-+ sp->dma_regs->status = status & enabled;
-+
-+ if (status & DMA_STATUS_NIS) {
-+ /* normal status */
-+ /**
-+ * Don't schedule rx processing if interrupt
-+ * is already disabled.
-+ */
-+ if (status & enabled & DMA_STATUS_RI) {
-+ /* receive interrupt */
-+ rx_schedule(dev);
-+ }
-+ if (status & DMA_STATUS_TI) {
-+ /* transmit interrupt */
-+ ar231x_tx_int(dev);
-+ }
-+ }
-+
-+ /* abnormal status */
-+ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
-+ ar231x_restart(dev);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int ar231x_open(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ unsigned int ethsal, ethsah;
-+
-+ /* reset the hardware, in case the MAC address changed */
-+ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
-+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
-+
-+ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
-+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
-+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
-+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
-+
-+ sp->eth_regs->mac_addr[0] = ethsah;
-+ sp->eth_regs->mac_addr[1] = ethsal;
-+
-+ mdelay(10);
-+
-+ dev->mtu = 1500;
-+ netif_start_queue(dev);
-+
-+ sp->eth_regs->mac_control |= MAC_CONTROL_RE;
-+
-+ return 0;
-+}
-+
-+static void ar231x_tx_timeout(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&sp->lock, flags);
-+ ar231x_restart(dev);
-+ spin_unlock_irqrestore(&sp->lock, flags);
-+}
-+
-+static void ar231x_halt(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ int j;
-+
-+ tasklet_disable(&sp->rx_tasklet);
-+
-+ /* kill the MAC */
-+ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
-+ MAC_CONTROL_TE); /* disable Transmits */
-+ /* stop dma */
-+ sp->dma_regs->control = 0;
-+ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
-+
-+ /* place phy and MAC in reset */
-+ sp->cfg->reset_set(sp->cfg->reset_mac);
-+ sp->cfg->reset_set(sp->cfg->reset_phy);
-+
-+ /* free buffers on tx ring */
-+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
-+ struct sk_buff *skb;
-+ ar231x_descr_t *txdesc;
-+
-+ txdesc = &sp->tx_ring[j];
-+ txdesc->descr = 0;
-+
-+ skb = sp->tx_skb[j];
-+ if (skb) {
-+ dev_kfree_skb(skb);
-+ sp->tx_skb[j] = NULL;
-+ }
-+ }
-+}
-+
-+/**
-+ * close should do nothing. Here's why. It's called when
-+ * 'ifconfig bond0 down' is run. If it calls free_irq then
-+ * the irq is gone forever ! When bond0 is made 'up' again,
-+ * the ar231x_open () does not call request_irq (). Worse,
-+ * the call to ar231x_halt() generates a WDOG reset due to
-+ * the write to reset register and the box reboots.
-+ * Commenting this out is good since it allows the
-+ * system to resume when bond0 is made up again.
-+ */
-+static int ar231x_close(struct net_device *dev)
-+{
-+#if 0
-+ /* Disable interrupts */
-+ disable_irq(dev->irq);
-+
-+ /**
-+ * Without (or before) releasing irq and stopping hardware, this
-+ * is an absolute non-sense, by the way. It will be reset instantly
-+ * by the first irq.
-+ */
-+ netif_stop_queue(dev);
-+
-+ /* stop the MAC and DMA engines */
-+ ar231x_halt(dev);
-+
-+ /* release the interrupt */
-+ free_irq(dev->irq, dev);
-+
-+#endif
-+ return 0;
-+}
-+
-+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ ar231x_descr_t *td;
-+ u32 idx;
-+
-+ idx = sp->tx_prd;
-+ td = &sp->tx_ring[idx];
-+
-+ if (td->status & DMA_TX_OWN) {
-+ /* free skbuf and lie to the caller that we sent it out */
-+ dev->stats.tx_dropped++;
-+ dev_kfree_skb(skb);
-+
-+ /* restart transmitter in case locked */
-+ sp->dma_regs->xmt_poll = 0;
-+ return 0;
-+ }
-+
-+ /* Setup the transmit descriptor. */
-+ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
-+ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
-+ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
-+ td->status = DMA_TX_OWN;
-+
-+ /* kick transmitter last */
-+ sp->dma_regs->xmt_poll = 0;
-+
-+ sp->tx_skb[idx] = skb;
-+ idx = DSC_NEXT(idx);
-+ sp->tx_prd = idx;
-+
-+ return 0;
-+}
-+
-+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+
-+ switch (cmd) {
-+ case SIOCGMIIPHY:
-+ case SIOCGMIIREG:
-+ case SIOCSMIIREG:
-+ return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
-+
-+ default:
-+ break;
-+ }
-+
-+ return -EOPNOTSUPP;
-+}
-+
-+static void ar231x_adjust_link(struct net_device *dev)
-+{
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ unsigned int mc;
-+
-+ if (!sp->phy_dev->link)
-+ return;
-+
-+ if (sp->phy_dev->duplex != sp->oldduplex) {
-+ mc = readl(&sp->eth_regs->mac_control);
-+ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
-+ if (sp->phy_dev->duplex)
-+ mc |= MAC_CONTROL_F;
-+ else
-+ mc |= MAC_CONTROL_DRO;
-+ writel(mc, &sp->eth_regs->mac_control);
-+ sp->oldduplex = sp->phy_dev->duplex;
-+ }
-+}
-+
-+#define MII_ADDR(phy, reg) \
-+ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
-+
-+static int
-+ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
-+{
-+ struct net_device *const dev = bus->priv;
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ volatile MII *ethernet = sp->phy_regs;
-+
-+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
-+ while (ethernet->mii_addr & MII_ADDR_BUSY)
-+ ;
-+ return ethernet->mii_data >> MII_DATA_SHIFT;
-+}
-+
-+static int
-+ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
-+{
-+ struct net_device *const dev = bus->priv;
-+ struct ar231x_private *sp = netdev_priv(dev);
-+ volatile MII *ethernet = sp->phy_regs;
-+
-+ while (ethernet->mii_addr & MII_ADDR_BUSY)
-+ ;
-+ ethernet->mii_data = value << MII_DATA_SHIFT;
-+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
-+
-+ return 0;
-+}
-+
-+static int ar231x_mdiobus_reset(struct mii_bus *bus)
-+{
-+ struct net_device *const dev = bus->priv;
-+
-+ ar231x_reset_reg(dev);
-+
-+ return 0;
-+}
-+
-+static int ar231x_mdiobus_probe(struct net_device *dev)
-+{
-+ struct ar231x_private *const sp = netdev_priv(dev);
-+ struct phy_device *phydev = NULL;
-+ int phy_addr;
-+
-+ /* find the first (lowest address) PHY on the current MAC's MII bus */
-+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
-+ if (sp->mii_bus->phy_map[phy_addr]) {
-+ phydev = sp->mii_bus->phy_map[phy_addr];
-+ sp->phy = phy_addr;
-+ break; /* break out with first one found */
-+ }
-+
-+ if (!phydev) {
-+ printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
-+ return -1;
-+ }
-+
-+ /* now we are supposed to have a proper phydev, to attach to... */
-+ BUG_ON(!phydev);
-+ BUG_ON(phydev->attached_dev);
-+
-+ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link,
-+ PHY_INTERFACE_MODE_MII);
-+
-+ if (IS_ERR(phydev)) {
-+ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
-+ return PTR_ERR(phydev);
-+ }
-+
-+ /* mask with MAC supported features */
-+ phydev->supported &= (SUPPORTED_10baseT_Half
-+ | SUPPORTED_10baseT_Full
-+ | SUPPORTED_100baseT_Half
-+ | SUPPORTED_100baseT_Full
-+ | SUPPORTED_Autoneg
-+ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
-+ | SUPPORTED_MII
-+ | SUPPORTED_TP);
-+
-+ phydev->advertising = phydev->supported;
-+
-+ sp->oldduplex = -1;
-+ sp->phy_dev = phydev;
-+
-+ printk(KERN_INFO "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
-+ dev->name, phydev->drv->name, dev_name(&phydev->dev));
-+
-+ return 0;
-+}
-+
---- /dev/null
-+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h
-@@ -0,0 +1,288 @@
-+/*
-+ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
-+ *
-+ * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
-+ *
-+ * Thanks to Atheros for providing hardware and documentation
-+ * enabling me to write this driver.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#ifndef _AR2313_H_
-+#define _AR2313_H_
-+
-+#include <linux/interrupt.h>
-+#include <generated/autoconf.h>
-+#include <linux/bitops.h>
-+#include <ath25_platform.h>
-+
-+/* probe link timer - 5 secs */
-+#define LINK_TIMER (5*HZ)
-+
-+#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
-+#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
-+#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
-+
-+#define AR2313_TX_TIMEOUT (HZ/4)
-+
-+/* Rings */
-+#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
-+#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
-+
-+#define AR2313_MBGET 2
-+#define AR2313_MBSET 3
-+#define AR2313_PCI_RECONFIG 4
-+#define AR2313_PCI_DUMP 5
-+#define AR2313_TEST_PANIC 6
-+#define AR2313_TEST_NULLPTR 7
-+#define AR2313_READ_DATA 8
-+#define AR2313_WRITE_DATA 9
-+#define AR2313_GET_VERSION 10
-+#define AR2313_TEST_HANG 11
-+#define AR2313_SYNC 12
-+
-+#define DMA_RX_ERR_CRC BIT(1)
-+#define DMA_RX_ERR_DRIB BIT(2)
-+#define DMA_RX_ERR_MII BIT(3)
-+#define DMA_RX_EV2 BIT(5)
-+#define DMA_RX_ERR_COL BIT(6)
-+#define DMA_RX_LONG BIT(7)
-+#define DMA_RX_LS BIT(8) /* last descriptor */
-+#define DMA_RX_FS BIT(9) /* first descriptor */
-+#define DMA_RX_MF BIT(10) /* multicast frame */
-+#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
-+#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
-+#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
-+#define DMA_RX_ERROR BIT(15) /* error summary */
-+#define DMA_RX_LEN_MASK 0x3fff0000
-+#define DMA_RX_LEN_SHIFT 16
-+#define DMA_RX_FILT BIT(30)
-+#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
-+
-+#define DMA_RX1_BSIZE_MASK 0x000007ff
-+#define DMA_RX1_BSIZE_SHIFT 0
-+#define DMA_RX1_CHAINED BIT(24)
-+#define DMA_RX1_RER BIT(25)
-+
-+#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
-+#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
-+#define DMA_TX_COL_MASK 0x78
-+#define DMA_TX_COL_SHIFT 3
-+#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
-+#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
-+#define DMA_TX_ERR_LATE BIT(9) /* late collision */
-+#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
-+#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
-+#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
-+#define DMA_TX_ERROR BIT(15) /* frame aborted */
-+#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
-+
-+#define DMA_TX1_BSIZE_MASK 0x000007ff
-+#define DMA_TX1_BSIZE_SHIFT 0
-+#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
-+#define DMA_TX1_TER BIT(25) /* transmit end of ring */
-+#define DMA_TX1_FS BIT(29) /* first segment */
-+#define DMA_TX1_LS BIT(30) /* last segment */
-+#define DMA_TX1_IC BIT(31) /* interrupt on completion */
-+
-+#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
-+
-+#define MAC_CONTROL_RE BIT(2) /* receive enable */
-+#define MAC_CONTROL_TE BIT(3) /* transmit enable */
-+#define MAC_CONTROL_DC BIT(5) /* Deferral check */
-+#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
-+#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
-+#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
-+#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
-+#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
-+#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
-+#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
-+#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
-+#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
-+#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
-+#define MAC_CONTROL_PM BIT(19) /* pass multicast */
-+#define MAC_CONTROL_F BIT(20) /* full-duplex */
-+#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
-+#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
-+#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
-+#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
-+
-+#define MII_ADDR_BUSY BIT(0)
-+#define MII_ADDR_WRITE BIT(1)
-+#define MII_ADDR_REG_SHIFT 6
-+#define MII_ADDR_PHY_SHIFT 11
-+#define MII_DATA_SHIFT 0
-+
-+#define FLOW_CONTROL_FCE BIT(1)
-+
-+#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
-+#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
-+#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
-+#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
-+
-+#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
-+#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
-+#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
-+#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
-+#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
-+#define DMA_STATUS_RI BIT(6) /* receive interrupt */
-+#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
-+#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
-+#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
-+#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
-+#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
-+#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
-+#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
-+#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
-+#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
-+#define DMA_STATUS_EB_SHIFT 23 /* error bits */
-+
-+#define DMA_CONTROL_SR BIT(1) /* start receive */
-+#define DMA_CONTROL_ST BIT(13) /* start transmit */
-+#define DMA_CONTROL_SF BIT(21) /* store and forward */
-+
-+typedef struct {
-+ volatile unsigned int status; /* OWN, Device control and status. */
-+ volatile unsigned int devcs; /* pkt Control bits + Length */
-+ volatile unsigned int addr; /* Current Address. */
-+ volatile unsigned int descr; /* Next descriptor in chain. */
-+} ar231x_descr_t;
-+
-+/**
-+ * New Combo structure for Both Eth0 AND eth1
-+ *
-+ * Don't directly access MII related regs since phy chip could be actually
-+ * connected to another ethernet block.
-+ */
-+typedef struct {
-+ volatile unsigned int mac_control; /* 0x00 */
-+ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
-+ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
-+ volatile unsigned int __mii_addr; /* 0x14 */
-+ volatile unsigned int __mii_data; /* 0x18 */
-+ volatile unsigned int flow_control; /* 0x1c */
-+ volatile unsigned int vlan_tag; /* 0x20 */
-+ volatile unsigned int pad[7]; /* 0x24 - 0x3c */
-+ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
-+} ETHERNET_STRUCT;
-+
-+typedef struct {
-+ volatile unsigned int mii_addr;
-+ volatile unsigned int mii_data;
-+} MII;
-+
-+/********************************************************************
-+ * Interrupt controller
-+ ********************************************************************/
-+
-+typedef struct {
-+ volatile unsigned int wdog_control; /* 0x08 */
-+ volatile unsigned int wdog_timer; /* 0x0c */
-+ volatile unsigned int misc_status; /* 0x10 */
-+ volatile unsigned int misc_mask; /* 0x14 */
-+ volatile unsigned int global_status; /* 0x18 */
-+ volatile unsigned int reserved; /* 0x1c */
-+ volatile unsigned int reset_control; /* 0x20 */
-+} INTERRUPT;
-+
-+/********************************************************************
-+ * DMA controller
-+ ********************************************************************/
-+typedef struct {
-+ volatile unsigned int bus_mode; /* 0x00 (CSR0) */
-+ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
-+ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
-+ volatile unsigned int rcv_base; /* 0x0c (CSR3) */
-+ volatile unsigned int xmt_base; /* 0x10 (CSR4) */
-+ volatile unsigned int status; /* 0x14 (CSR5) */
-+ volatile unsigned int control; /* 0x18 (CSR6) */
-+ volatile unsigned int intr_ena; /* 0x1c (CSR7) */
-+ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
-+ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
-+ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
-+ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
-+} DMA;
-+
-+/**
-+ * Struct private for the Sibyte.
-+ *
-+ * Elements are grouped so variables used by the tx handling goes
-+ * together, and will go into the same cache lines etc. in order to
-+ * avoid cache line contention between the rx and tx handling on SMP.
-+ *
-+ * Frequently accessed variables are put at the beginning of the
-+ * struct to help the compiler generate better/shorter code.
-+ */
-+struct ar231x_private {
-+ struct net_device *dev;
-+ int version;
-+ u32 mb[2];
-+
-+ volatile MII *phy_regs;
-+ volatile ETHERNET_STRUCT *eth_regs;
-+ volatile DMA *dma_regs;
-+ struct ar231x_eth *cfg;
-+
-+ spinlock_t lock; /* Serialise access to device */
-+
-+ /* RX and TX descriptors, must be adjacent */
-+ ar231x_descr_t *rx_ring;
-+ ar231x_descr_t *tx_ring;
-+
-+ struct sk_buff **rx_skb;
-+ struct sk_buff **tx_skb;
-+
-+ /* RX elements */
-+ u32 rx_skbprd;
-+ u32 cur_rx;
-+
-+ /* TX elements */
-+ u32 tx_prd;
-+ u32 tx_csm;
-+
-+ /* Misc elements */
-+ char name[48];
-+ struct {
-+ u32 address;
-+ u32 length;
-+ char *mapping;
-+ } desc;
-+
-+ struct timer_list link_timer;
-+ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
-+ unsigned short mac;
-+ unsigned short link; /* 0 - link down, 1 - link up */
-+ u16 phy_data;
-+
-+ struct tasklet_struct rx_tasklet;
-+ int unloading;
-+
-+ struct phy_device *phy_dev;
-+ struct mii_bus *mii_bus;
-+ int oldduplex;
-+};
-+
-+/* Prototypes */
-+static int ar231x_init(struct net_device *dev);
-+#ifdef TX_TIMEOUT
-+static void ar231x_tx_timeout(struct net_device *dev);
-+#endif
-+static int ar231x_restart(struct net_device *dev);
-+static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
-+static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
-+static int ar231x_open(struct net_device *dev);
-+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
-+static int ar231x_close(struct net_device *dev);
-+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
-+static void ar231x_init_cleanup(struct net_device *dev);
-+static int ar231x_setup_timer(struct net_device *dev);
-+static void ar231x_link_timer_fn(unsigned long data);
-+static void ar231x_check_link(struct net_device *dev);
-+
-+#endif /* _AR2313_H_ */
---- a/arch/mips/ath25/ar2315_regs.h
-+++ b/arch/mips/ath25/ar2315_regs.h
-@@ -57,6 +57,9 @@
- #define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
- #define AR2315_PCI_EXT_SIZE 0x40000000
-
-+/* MII registers offset inside Ethernet MMR region */
-+#define AR2315_ENET0_MII_BASE (AR2315_ENET0_BASE + 0x14)
-+
- /*
- * Configuration registers
- */
---- a/arch/mips/ath25/ar5312_regs.h
-+++ b/arch/mips/ath25/ar5312_regs.h
-@@ -64,6 +64,10 @@
- #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
- #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
-
-+/* MII registers offset inside Ethernet MMR region */
-+#define AR5312_ENET0_MII_BASE (AR5312_ENET0_BASE + 0x14)
-+#define AR5312_ENET1_MII_BASE (AR5312_ENET1_BASE + 0x14)
-+
- /* Reset/Timer Block Address Map */
- #define AR5312_TIMER 0x0000 /* countdown timer */
- #define AR5312_RELOAD 0x0004 /* timer reload value */
---- a/arch/mips/ath25/ar2315.c
-+++ b/arch/mips/ath25/ar2315.c
-@@ -136,6 +136,8 @@ static void ar2315_irq_dispatch(void)
-
- if (pending & CAUSEF_IP3)
- do_IRQ(AR2315_IRQ_WLAN0);
-+ else if (pending & CAUSEF_IP4)
-+ do_IRQ(AR2315_IRQ_ENET0);
- #ifdef CONFIG_PCI_AR2315
- else if (pending & CAUSEF_IP5)
- do_IRQ(AR2315_IRQ_LCBUS_PCI);
-@@ -169,6 +171,29 @@ void __init ar2315_arch_init_irq(void)
- ar2315_misc_irq_domain = domain;
- }
-
-+static void ar2315_device_reset_set(u32 mask)
-+{
-+ u32 val;
-+
-+ val = ar2315_rst_reg_read(AR2315_RESET);
-+ ar2315_rst_reg_write(AR2315_RESET, val | mask);
-+}
-+
-+static void ar2315_device_reset_clear(u32 mask)
-+{
-+ u32 val;
-+
-+ val = ar2315_rst_reg_read(AR2315_RESET);
-+ ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
-+}
-+
-+static struct ar231x_eth ar2315_eth_data = {
-+ .reset_set = ar2315_device_reset_set,
-+ .reset_clear = ar2315_device_reset_clear,
-+ .reset_mac = AR2315_RESET_ENET0,
-+ .reset_phy = AR2315_RESET_EPHY0,
-+};
-+
- static struct resource ar2315_gpio_res[] = {
- {
- .name = "ar2315-gpio",
-@@ -205,6 +230,11 @@ void __init ar2315_init_devices(void)
- ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
- platform_device_register(&ar2315_gpio);
-
-+ ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
-+ ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
-+ AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
-+ &ar2315_eth_data);
-+
- ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
- }
-
---- a/arch/mips/ath25/ar5312.c
-+++ b/arch/mips/ath25/ar5312.c
-@@ -132,6 +132,10 @@ static void ar5312_irq_dispatch(void)
-
- if (pending & CAUSEF_IP2)
- do_IRQ(AR5312_IRQ_WLAN0);
-+ else if (pending & CAUSEF_IP3)
-+ do_IRQ(AR5312_IRQ_ENET0);
-+ else if (pending & CAUSEF_IP4)
-+ do_IRQ(AR5312_IRQ_ENET1);
- else if (pending & CAUSEF_IP5)
- do_IRQ(AR5312_IRQ_WLAN1);
- else if (pending & CAUSEF_IP6)
-@@ -163,6 +167,36 @@ void __init ar5312_arch_init_irq(void)
- ar5312_misc_irq_domain = domain;
- }
-
-+static void ar5312_device_reset_set(u32 mask)
-+{
-+ u32 val;
-+
-+ val = ar5312_rst_reg_read(AR5312_RESET);
-+ ar5312_rst_reg_write(AR5312_RESET, val | mask);
-+}
-+
-+static void ar5312_device_reset_clear(u32 mask)
-+{
-+ u32 val;
-+
-+ val = ar5312_rst_reg_read(AR5312_RESET);
-+ ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
-+}
-+
-+static struct ar231x_eth ar5312_eth0_data = {
-+ .reset_set = ar5312_device_reset_set,
-+ .reset_clear = ar5312_device_reset_clear,
-+ .reset_mac = AR5312_RESET_ENET0,
-+ .reset_phy = AR5312_RESET_EPHY0,
-+};
-+
-+static struct ar231x_eth ar5312_eth1_data = {
-+ .reset_set = ar5312_device_reset_set,
-+ .reset_clear = ar5312_device_reset_clear,
-+ .reset_mac = AR5312_RESET_ENET1,
-+ .reset_phy = AR5312_RESET_EPHY1,
-+};
-+
- static struct physmap_flash_data ar5312_flash_data = {
- .width = 2,
- };
-@@ -243,6 +277,7 @@ static void __init ar5312_flash_init(voi
- void __init ar5312_init_devices(void)
- {
- struct ath25_boarddata *config;
-+ u8 *c;
-
- ar5312_flash_init();
-
-@@ -266,8 +301,30 @@ void __init ar5312_init_devices(void)
-
- platform_device_register(&ar5312_gpio);
-
-+ /* Fix up MAC addresses if necessary */
-+ if (is_broadcast_ether_addr(config->enet0_mac))
-+ ether_addr_copy(config->enet0_mac, config->enet1_mac);
-+
-+ /* If ENET0 and ENET1 have the same mac address,
-+ * increment the one from ENET1 */
-+ if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
-+ c = config->enet1_mac + 5;
-+ while ((c >= config->enet1_mac) && !(++(*c)))
-+ c--;
-+ }
-+
- switch (ath25_soc) {
- case ATH25_SOC_AR5312:
-+ ar5312_eth0_data.macaddr = config->enet0_mac;
-+ ath25_add_ethernet(0, AR5312_ENET0_BASE, "eth0_mii",
-+ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0,
-+ &ar5312_eth0_data);
-+
-+ ar5312_eth1_data.macaddr = config->enet1_mac;
-+ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth1_mii",
-+ AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1,
-+ &ar5312_eth1_data);
-+
- if (!ath25_board.radio)
- return;
-
-@@ -276,8 +333,18 @@ void __init ar5312_init_devices(void)
-
- ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
- break;
-+ /*
-+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
-+ * of ENET1. Atheros calls it 'twisted' for a reason :)
-+ */
- case ATH25_SOC_AR2312:
- case ATH25_SOC_AR2313:
-+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
-+ ar5312_eth1_data.macaddr = config->enet0_mac;
-+ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth0_mii",
-+ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1,
-+ &ar5312_eth1_data);
-+
- if (!ath25_board.radio)
- return;
- break;
---- a/arch/mips/ath25/devices.h
-+++ b/arch/mips/ath25/devices.h
-@@ -32,6 +32,8 @@ extern struct ar231x_board_config ath25_
- extern void (*ath25_irq_dispatch)(void);
-
- int ath25_find_config(phys_addr_t offset, unsigned long size);
-+int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
-+ int irq, void *pdata);
- void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
- int ath25_add_wmac(int nr, u32 base, int irq);
-
---- a/arch/mips/ath25/devices.c
-+++ b/arch/mips/ath25/devices.c
-@@ -12,6 +12,51 @@
- struct ar231x_board_config ath25_board;
- enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
-
-+static struct resource ath25_eth0_res[] = {
-+ {
-+ .name = "eth0_membase",
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "eth0_mii",
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "eth0_irq",
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct resource ath25_eth1_res[] = {
-+ {
-+ .name = "eth1_membase",
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "eth1_mii",
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "eth1_irq",
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device ath25_eth[] = {
-+ {
-+ .id = 0,
-+ .name = "ar231x-eth",
-+ .resource = ath25_eth0_res,
-+ .num_resources = ARRAY_SIZE(ath25_eth0_res)
-+ },
-+ {
-+ .id = 1,
-+ .name = "ar231x-eth",
-+ .resource = ath25_eth1_res,
-+ .num_resources = ARRAY_SIZE(ath25_eth1_res)
-+ }
-+};
-+
- static struct resource ath25_wmac0_res[] = {
- {
- .name = "wmac0_membase",
-@@ -70,6 +115,25 @@ const char *get_system_type(void)
- return soc_type_strings[ath25_soc];
- }
-
-+int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
-+ u32 mii_base, int irq, void *pdata)
-+{
-+ struct resource *res;
-+
-+ ath25_eth[nr].dev.platform_data = pdata;
-+ res = &ath25_eth[nr].resource[0];
-+ res->start = base;
-+ res->end = base + 0x2000 - 1;
-+ res++;
-+ res->name = mii_name;
-+ res->start = mii_base;
-+ res->end = mii_base + 8 - 1;
-+ res++;
-+ res->start = irq;
-+ res->end = irq;
-+ return platform_device_register(&ath25_eth[nr]);
-+}
-+
- void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
- {
- struct uart_port s;
---- a/arch/mips/include/asm/mach-ath25/ath25_platform.h
-+++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
-@@ -70,4 +70,15 @@ struct ar231x_board_config {
- const char *radio;
- };
-
-+/*
-+ * Platform device information for the Ethernet MAC
-+ */
-+struct ar231x_eth {
-+ void (*reset_set)(u32);
-+ void (*reset_clear)(u32);
-+ u32 reset_mac;
-+ u32 reset_phy;
-+ char *macaddr;
-+};
-+
- #endif /* __ASM_MACH_ATH25_PLATFORM_H */
+++ /dev/null
---- a/drivers/mtd/devices/Kconfig
-+++ b/drivers/mtd/devices/Kconfig
-@@ -120,6 +120,10 @@ config MTD_BCM47XXSFLASH
- registered by bcma as platform devices. This enables driver for
- serial flash memories (only read-only mode is implemented).
-
-+config MTD_AR2315
-+ tristate "Atheros AR2315+ SPI Flash support"
-+ depends on SOC_AR2315
-+
- config MTD_SLRAM
- tristate "Uncached system RAM"
- help
---- a/drivers/mtd/devices/Makefile
-+++ b/drivers/mtd/devices/Makefile
-@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataf
- obj-$(CONFIG_MTD_M25P80) += m25p80.o
- obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o
- obj-$(CONFIG_MTD_SST25L) += sst25l.o
-+obj-$(CONFIG_MTD_AR2315) += ar2315.o
- obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
- obj-$(CONFIG_MTD_ST_SPI_FSM) += st_spi_fsm.o
-
---- /dev/null
-+++ b/drivers/mtd/devices/ar2315.c
-@@ -0,0 +1,459 @@
-+
-+/*
-+ * MTD driver for the SPI Flash Memory support on Atheros AR2315
-+ *
-+ * Copyright (c) 2005-2006 Atheros Communications Inc.
-+ * Copyright (C) 2006-2007 FON Technology, SL.
-+ * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
-+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
-+ *
-+ * This code is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/slab.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/platform_device.h>
-+#include <linux/sched.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/mutex.h>
-+
-+#include "ar2315_spiflash.h"
-+
-+#define DRIVER_NAME "ar2315-spiflash"
-+
-+#define busy_wait(_priv, _condition, _wait) do { \
-+ while (_condition) { \
-+ if (_wait > 1) \
-+ msleep(_wait); \
-+ else if ((_wait == 1) && need_resched()) \
-+ schedule(); \
-+ else \
-+ udelay(1); \
-+ } \
-+} while (0)
-+
-+enum {
-+ FLASH_NONE,
-+ FLASH_1MB,
-+ FLASH_2MB,
-+ FLASH_4MB,
-+ FLASH_8MB,
-+ FLASH_16MB,
-+};
-+
-+/* Flash configuration table */
-+struct flashconfig {
-+ u32 byte_cnt;
-+ u32 sector_cnt;
-+ u32 sector_size;
-+};
-+
-+static const struct flashconfig flashconfig_tbl[] = {
-+ [FLASH_NONE] = { 0, 0, 0},
-+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,
-+ STM_1MB_SECTOR_SIZE},
-+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,
-+ STM_2MB_SECTOR_SIZE},
-+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,
-+ STM_4MB_SECTOR_SIZE},
-+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,
-+ STM_8MB_SECTOR_SIZE},
-+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,
-+ STM_16MB_SECTOR_SIZE}
-+};
-+
-+/* Mapping of generic opcodes to STM serial flash opcodes */
-+enum {
-+ SPI_WRITE_ENABLE,
-+ SPI_WRITE_DISABLE,
-+ SPI_RD_STATUS,
-+ SPI_WR_STATUS,
-+ SPI_RD_DATA,
-+ SPI_FAST_RD_DATA,
-+ SPI_PAGE_PROGRAM,
-+ SPI_SECTOR_ERASE,
-+ SPI_BULK_ERASE,
-+ SPI_DEEP_PWRDOWN,
-+ SPI_RD_SIG,
-+};
-+
-+struct opcodes {
-+ __u16 code;
-+ __s8 tx_cnt;
-+ __s8 rx_cnt;
-+};
-+
-+static const struct opcodes stm_opcodes[] = {
-+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
-+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
-+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
-+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
-+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
-+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
-+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
-+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
-+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
-+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
-+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
-+};
-+
-+/* Driver private data structure */
-+struct spiflash_priv {
-+ struct mtd_info mtd;
-+ void __iomem *readaddr; /* memory mapped data for read */
-+ void __iomem *mmraddr; /* memory mapped register space */
-+ struct mutex lock; /* serialize registers access */
-+};
-+
-+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
-+
-+enum {
-+ FL_READY,
-+ FL_READING,
-+ FL_ERASING,
-+ FL_WRITING
-+};
-+
-+/*****************************************************************************/
-+
-+static u32
-+spiflash_read_reg(struct spiflash_priv *priv, int reg)
-+{
-+ return ioread32(priv->mmraddr + reg);
-+}
-+
-+static void
-+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
-+{
-+ iowrite32(data, priv->mmraddr + reg);
-+}
-+
-+static u32
-+spiflash_wait_busy(struct spiflash_priv *priv)
-+{
-+ u32 reg;
-+
-+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
-+ SPI_CTL_BUSY, 0);
-+ return reg;
-+}
-+
-+static u32
-+spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
-+{
-+ const struct opcodes *op;
-+ u32 reg, mask;
-+
-+ op = &stm_opcodes[opcode];
-+ reg = spiflash_wait_busy(priv);
-+ spiflash_write_reg(priv, SPI_FLASH_OPCODE,
-+ ((u32)op->code) | (addr << 8));
-+
-+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
-+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
-+
-+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
-+ spiflash_wait_busy(priv);
-+
-+ if (!op->rx_cnt)
-+ return 0;
-+
-+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
-+
-+ switch (op->rx_cnt) {
-+ case 1:
-+ mask = 0x000000ff;
-+ break;
-+ case 2:
-+ mask = 0x0000ffff;
-+ break;
-+ case 3:
-+ mask = 0x00ffffff;
-+ break;
-+ default:
-+ mask = 0xffffffff;
-+ break;
-+ }
-+ reg &= mask;
-+
-+ return reg;
-+}
-+
-+/*
-+ * Probe SPI flash device
-+ * Function returns 0 for failure.
-+ * and flashconfig_tbl array index for success.
-+ */
-+static int
-+spiflash_probe_chip(struct platform_device *pdev, struct spiflash_priv *priv)
-+{
-+ u32 sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
-+ int flash_size;
-+
-+ switch (sig) {
-+ case STM_8MBIT_SIGNATURE:
-+ flash_size = FLASH_1MB;
-+ break;
-+ case STM_16MBIT_SIGNATURE:
-+ flash_size = FLASH_2MB;
-+ break;
-+ case STM_32MBIT_SIGNATURE:
-+ flash_size = FLASH_4MB;
-+ break;
-+ case STM_64MBIT_SIGNATURE:
-+ flash_size = FLASH_8MB;
-+ break;
-+ case STM_128MBIT_SIGNATURE:
-+ flash_size = FLASH_16MB;
-+ break;
-+ default:
-+ dev_warn(&pdev->dev, "read of flash device signature failed!\n");
-+ return 0;
-+ }
-+
-+ return flash_size;
-+}
-+
-+static void
-+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
-+{
-+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
-+ SPI_STATUS_WIP, timeout);
-+}
-+
-+static int
-+spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
-+{
-+ struct spiflash_priv *priv = to_spiflash(mtd);
-+ const struct opcodes *op;
-+ u32 temp, reg;
-+
-+ if (instr->addr + instr->len > mtd->size)
-+ return -EINVAL;
-+
-+ mutex_lock(&priv->lock);
-+
-+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
-+ reg = spiflash_wait_busy(priv);
-+
-+ op = &stm_opcodes[SPI_SECTOR_ERASE];
-+ temp = ((u32)instr->addr << 8) | (u32)(op->code);
-+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
-+
-+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
-+ reg |= op->tx_cnt | SPI_CTL_START;
-+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
-+
-+ spiflash_wait_complete(priv, 20);
-+
-+ mutex_unlock(&priv->lock);
-+
-+ instr->state = MTD_ERASE_DONE;
-+ mtd_erase_callback(instr);
-+
-+ return 0;
-+}
-+
-+static int
-+spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
-+ u_char *buf)
-+{
-+ struct spiflash_priv *priv = to_spiflash(mtd);
-+
-+ if (!len)
-+ return 0;
-+
-+ if (from + len > mtd->size)
-+ return -EINVAL;
-+
-+ *retlen = len;
-+
-+ mutex_lock(&priv->lock);
-+
-+ memcpy_fromio(buf, priv->readaddr + from, len);
-+
-+ mutex_unlock(&priv->lock);
-+
-+ return 0;
-+}
-+
-+static int
-+spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
-+ const u8 *buf)
-+{
-+ struct spiflash_priv *priv = to_spiflash(mtd);
-+ u32 opcode, bytes_left;
-+
-+ *retlen = 0;
-+
-+ if (!len)
-+ return 0;
-+
-+ if (to + len > mtd->size)
-+ return -EINVAL;
-+
-+ bytes_left = len;
-+
-+ do {
-+ u32 read_len, reg, page_offset, spi_data = 0;
-+
-+ read_len = min(bytes_left, sizeof(u32));
-+
-+ /* 32-bit writes cannot span across a page boundary
-+ * (256 bytes). This types of writes require two page
-+ * program operations to handle it correctly. The STM part
-+ * will write the overflow data to the beginning of the
-+ * current page as opposed to the subsequent page.
-+ */
-+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
-+
-+ if (page_offset > STM_PAGE_SIZE)
-+ read_len -= (page_offset - STM_PAGE_SIZE);
-+
-+ mutex_lock(&priv->lock);
-+
-+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
-+ spi_data = 0;
-+ switch (read_len) {
-+ case 4:
-+ spi_data |= buf[3] << 24;
-+ /* fall through */
-+ case 3:
-+ spi_data |= buf[2] << 16;
-+ /* fall through */
-+ case 2:
-+ spi_data |= buf[1] << 8;
-+ /* fall through */
-+ case 1:
-+ spi_data |= buf[0] & 0xff;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
-+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
-+ (to & 0x00ffffff) << 8;
-+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
-+
-+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
-+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
-+ reg |= (read_len + 4) | SPI_CTL_START;
-+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
-+
-+ spiflash_wait_complete(priv, 1);
-+
-+ mutex_unlock(&priv->lock);
-+
-+ bytes_left -= read_len;
-+ to += read_len;
-+ buf += read_len;
-+
-+ *retlen += read_len;
-+ } while (bytes_left != 0);
-+
-+ return 0;
-+}
-+
-+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
-+static const char * const part_probe_types[] = {
-+ "cmdlinepart", "RedBoot", "MyLoader", NULL
-+};
-+#endif
-+
-+static int
-+spiflash_probe(struct platform_device *pdev)
-+{
-+ struct spiflash_priv *priv;
-+ struct mtd_info *mtd;
-+ struct resource *res;
-+ int index;
-+ int result = 0;
-+
-+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ mutex_init(&priv->lock);
-+ mtd = &priv->mtd;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+ priv->mmraddr = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(priv->mmraddr)) {
-+ dev_warn(&pdev->dev, "failed to map flash MMR\n");
-+ return PTR_ERR(priv->mmraddr);
-+ }
-+
-+ index = spiflash_probe_chip(pdev, priv);
-+ if (!index) {
-+ dev_warn(&pdev->dev, "found no flash device\n");
-+ return -ENODEV;
-+ }
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ priv->readaddr = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(priv->readaddr)) {
-+ dev_warn(&pdev->dev, "failed to map flash read mem\n");
-+ return PTR_ERR(priv->readaddr);
-+ }
-+
-+ platform_set_drvdata(pdev, priv);
-+ mtd->name = "spiflash";
-+ mtd->type = MTD_NORFLASH;
-+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
-+ mtd->size = flashconfig_tbl[index].byte_cnt;
-+ mtd->erasesize = flashconfig_tbl[index].sector_size;
-+ mtd->writesize = 1;
-+ mtd->numeraseregions = 0;
-+ mtd->eraseregions = NULL;
-+ mtd->_erase = spiflash_erase;
-+ mtd->_read = spiflash_read;
-+ mtd->_write = spiflash_write;
-+ mtd->owner = THIS_MODULE;
-+
-+ dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10);
-+
-+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
-+ /* parse redboot partitions */
-+
-+ result = mtd_device_parse_register(mtd, part_probe_types,
-+ NULL, NULL, 0);
-+#endif
-+
-+ return result;
-+}
-+
-+static int
-+spiflash_remove(struct platform_device *pdev)
-+{
-+ struct spiflash_priv *priv = platform_get_drvdata(pdev);
-+
-+ mtd_device_unregister(&priv->mtd);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver spiflash_driver = {
-+ .driver.name = DRIVER_NAME,
-+ .probe = spiflash_probe,
-+ .remove = spiflash_remove,
-+};
-+
-+module_platform_driver(spiflash_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("OpenWrt.org");
-+MODULE_AUTHOR("Atheros Communications Inc");
-+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros AR2315+ SOC");
-+MODULE_ALIAS("platform:" DRIVER_NAME);
-+
---- /dev/null
-+++ b/drivers/mtd/devices/ar2315_spiflash.h
-@@ -0,0 +1,106 @@
-+/*
-+ * Atheros AR2315 SPI Flash Memory support header file.
-+ *
-+ * Copyright (c) 2005, Atheros Communications Inc.
-+ * Copyright (C) 2006 FON Technology, SL.
-+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
-+ *
-+ * This code is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+#ifndef __AR2315_SPIFLASH_H
-+#define __AR2315_SPIFLASH_H
-+
-+#define STM_PAGE_SIZE 256
-+
-+#define SFI_WRITE_BUFFER_SIZE 4
-+#define SFI_FLASH_ADDR_MASK 0x00ffffff
-+
-+#define STM_8MBIT_SIGNATURE 0x13
-+#define STM_M25P80_BYTE_COUNT 1048576
-+#define STM_M25P80_SECTOR_COUNT 16
-+#define STM_M25P80_SECTOR_SIZE 0x10000
-+
-+#define STM_16MBIT_SIGNATURE 0x14
-+#define STM_M25P16_BYTE_COUNT 2097152
-+#define STM_M25P16_SECTOR_COUNT 32
-+#define STM_M25P16_SECTOR_SIZE 0x10000
-+
-+#define STM_32MBIT_SIGNATURE 0x15
-+#define STM_M25P32_BYTE_COUNT 4194304
-+#define STM_M25P32_SECTOR_COUNT 64
-+#define STM_M25P32_SECTOR_SIZE 0x10000
-+
-+#define STM_64MBIT_SIGNATURE 0x16
-+#define STM_M25P64_BYTE_COUNT 8388608
-+#define STM_M25P64_SECTOR_COUNT 128
-+#define STM_M25P64_SECTOR_SIZE 0x10000
-+
-+#define STM_128MBIT_SIGNATURE 0x17
-+#define STM_M25P128_BYTE_COUNT 16777216
-+#define STM_M25P128_SECTOR_COUNT 256
-+#define STM_M25P128_SECTOR_SIZE 0x10000
-+
-+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
-+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
-+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
-+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
-+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
-+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
-+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
-+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
-+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
-+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
-+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
-+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
-+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
-+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
-+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
-+
-+/*
-+ * ST Microelectronics Opcodes for Serial Flash
-+ */
-+
-+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
-+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
-+#define STM_OP_RD_STATUS 0x05 /* Read Status */
-+#define STM_OP_WR_STATUS 0x01 /* Write Status */
-+#define STM_OP_RD_DATA 0x03 /* Read Data */
-+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
-+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
-+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
-+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
-+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
-+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
-+
-+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
-+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
-+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
-+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
-+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
-+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
-+
-+/*
-+ * SPI Flash Interface Registers
-+ */
-+
-+#define SPI_FLASH_CTL 0x00
-+#define SPI_FLASH_OPCODE 0x04
-+#define SPI_FLASH_DATA 0x08
-+
-+#define SPI_CTL_START 0x00000100
-+#define SPI_CTL_BUSY 0x00010000
-+#define SPI_CTL_TXCNT_MASK 0x0000000f
-+#define SPI_CTL_RXCNT_MASK 0x000000f0
-+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
-+#define SPI_CTL_SIZE_MASK 0x00060000
-+
-+#define SPI_CTL_CLK_SEL_MASK 0x03000000
-+#define SPI_OPCODE_MASK 0x000000ff
-+
-+#define SPI_STATUS_WIP STM_STATUS_WIP
-+
-+#endif
---- a/arch/mips/ath25/ar2315.c
-+++ b/arch/mips/ath25/ar2315.c
-@@ -220,6 +220,28 @@ static struct platform_device ar2315_gpi
- .num_resources = ARRAY_SIZE(ar2315_gpio_res)
- };
-
-+static struct resource ar2315_spiflash_res[] = {
-+ {
-+ .name = "spiflash_read",
-+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_SPI_READ_BASE,
-+ .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1,
-+ },
-+ {
-+ .name = "spiflash_mmr",
-+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_SPI_MMR_BASE,
-+ .end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1,
-+ },
-+};
-+
-+static struct platform_device ar2315_spiflash = {
-+ .id = 0,
-+ .name = "ar2315-spiflash",
-+ .resource = ar2315_spiflash_res,
-+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
-+};
-+
- void __init ar2315_init_devices(void)
- {
- /* Find board configuration */
-@@ -230,6 +252,8 @@ void __init ar2315_init_devices(void)
- ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
- platform_device_register(&ar2315_gpio);
-
-+ platform_device_register(&ar2315_spiflash);
-+
- ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
- ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
- AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
+++ /dev/null
---- /dev/null
-+++ b/drivers/watchdog/ar2315-wtd.c
-@@ -0,0 +1,209 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
-+ *
-+ * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
-+ * Based on EP93xx and ifxmips wdt driver
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/types.h>
-+#include <linux/miscdevice.h>
-+#include <linux/watchdog.h>
-+#include <linux/fs.h>
-+#include <linux/ioport.h>
-+#include <linux/notifier.h>
-+#include <linux/reboot.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/uaccess.h>
-+
-+#define DRIVER_NAME "ar2315-wdt"
-+
-+#define CLOCK_RATE 40000000
-+#define HEARTBEAT(x) (x < 1 || x > 90 ? 20 : x)
-+
-+#define WDT_REG_TIMER 0x00
-+#define WDT_REG_CTRL 0x04
-+
-+#define WDT_CTRL_ACT_NONE 0x00000000 /* No action */
-+#define WDT_CTRL_ACT_NMI 0x00000001 /* NMI on watchdog */
-+#define WDT_CTRL_ACT_RESET 0x00000002 /* reset on watchdog */
-+
-+static int wdt_timeout = 20;
-+static int started;
-+static int in_use;
-+static void __iomem *wdt_base;
-+
-+static inline void ar2315_wdt_wr(unsigned reg, u32 val)
-+{
-+ iowrite32(val, wdt_base + reg);
-+}
-+
-+static void
-+ar2315_wdt_enable(void)
-+{
-+ ar2315_wdt_wr(WDT_REG_TIMER, wdt_timeout * CLOCK_RATE);
-+}
-+
-+static ssize_t
-+ar2315_wdt_write(struct file *file, const char __user *data, size_t len,
-+ loff_t *ppos)
-+{
-+ if (len)
-+ ar2315_wdt_enable();
-+ return len;
-+}
-+
-+static int
-+ar2315_wdt_open(struct inode *inode, struct file *file)
-+{
-+ if (in_use)
-+ return -EBUSY;
-+ ar2315_wdt_enable();
-+ in_use = 1;
-+ started = 1;
-+ return nonseekable_open(inode, file);
-+}
-+
-+static int
-+ar2315_wdt_release(struct inode *inode, struct file *file)
-+{
-+ in_use = 0;
-+ return 0;
-+}
-+
-+static irqreturn_t
-+ar2315_wdt_interrupt(int irq, void *dev)
-+{
-+ struct platform_device *pdev = (struct platform_device *)dev;
-+
-+ if (started) {
-+ dev_crit(&pdev->dev, "watchdog expired, rebooting system\n");
-+ emergency_restart();
-+ } else {
-+ ar2315_wdt_wr(WDT_REG_CTRL, 0);
-+ ar2315_wdt_wr(WDT_REG_TIMER, 0);
-+ }
-+ return IRQ_HANDLED;
-+}
-+
-+static struct watchdog_info ident = {
-+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
-+ .identity = "ar2315 Watchdog",
-+};
-+
-+static long
-+ar2315_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ int new_wdt_timeout;
-+ int ret = -ENOIOCTLCMD;
-+
-+ switch (cmd) {
-+ case WDIOC_GETSUPPORT:
-+ ret = copy_to_user((void __user *)arg, &ident, sizeof(ident)) ?
-+ -EFAULT : 0;
-+ break;
-+ case WDIOC_KEEPALIVE:
-+ ar2315_wdt_enable();
-+ ret = 0;
-+ break;
-+ case WDIOC_SETTIMEOUT:
-+ ret = get_user(new_wdt_timeout, (int __user *)arg);
-+ if (ret)
-+ break;
-+ wdt_timeout = HEARTBEAT(new_wdt_timeout);
-+ ar2315_wdt_enable();
-+ break;
-+ case WDIOC_GETTIMEOUT:
-+ ret = put_user(wdt_timeout, (int __user *)arg);
-+ break;
-+ }
-+ return ret;
-+}
-+
-+static const struct file_operations ar2315_wdt_fops = {
-+ .owner = THIS_MODULE,
-+ .llseek = no_llseek,
-+ .write = ar2315_wdt_write,
-+ .unlocked_ioctl = ar2315_wdt_ioctl,
-+ .open = ar2315_wdt_open,
-+ .release = ar2315_wdt_release,
-+};
-+
-+static struct miscdevice ar2315_wdt_miscdev = {
-+ .minor = WATCHDOG_MINOR,
-+ .name = "watchdog",
-+ .fops = &ar2315_wdt_fops,
-+};
-+
-+static int
-+ar2315_wdt_probe(struct platform_device *dev)
-+{
-+ struct resource *mem_res, *irq_res;
-+ int ret = 0;
-+
-+ if (wdt_base)
-+ return -EBUSY;
-+
-+ irq_res = platform_get_resource(dev, IORESOURCE_IRQ, 0);
-+ if (!irq_res) {
-+ dev_err(&dev->dev, "no IRQ resource\n");
-+ return -ENOENT;
-+ }
-+
-+ mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-+ wdt_base = devm_ioremap_resource(&dev->dev, mem_res);
-+ if (IS_ERR(wdt_base))
-+ return PTR_ERR(wdt_base);
-+
-+ ret = devm_request_irq(&dev->dev, irq_res->start, ar2315_wdt_interrupt,
-+ IRQF_DISABLED, DRIVER_NAME, dev);
-+ if (ret) {
-+ dev_err(&dev->dev, "failed to register inetrrupt\n");
-+ goto out;
-+ }
-+
-+ ret = misc_register(&ar2315_wdt_miscdev);
-+ if (ret)
-+ dev_err(&dev->dev, "failed to register miscdev\n");
-+
-+out:
-+ return ret;
-+}
-+
-+static int
-+ar2315_wdt_remove(struct platform_device *dev)
-+{
-+ misc_deregister(&ar2315_wdt_miscdev);
-+ return 0;
-+}
-+
-+static struct platform_driver ar2315_wdt_driver = {
-+ .probe = ar2315_wdt_probe,
-+ .remove = ar2315_wdt_remove,
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+module_platform_driver(ar2315_wdt_driver);
-+
-+MODULE_DESCRIPTION("Atheros AR2315 hardware watchdog driver");
-+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:" DRIVER_NAME);
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1257,6 +1257,13 @@ config RALINK_WDT
- help
- Hardware driver for the Ralink SoC Watchdog Timer.
-
-+config AR2315_WDT
-+ tristate "Atheros AR2315+ WiSoCs Watchdog Timer"
-+ depends on ATH25
-+ help
-+ Hardware driver for the built-in watchdog timer on the Atheros
-+ AR2315/AR2316 WiSoCs.
-+
- # PARISC Architecture
-
- # POWERPC Architecture
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -138,6 +138,7 @@ obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o
- obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o
- obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
- obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
-+obj-$(CONFIG_AR2315_WDT) += ar2315-wtd.o
- obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
- obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
- octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
---- a/arch/mips/ath25/ar2315.c
-+++ b/arch/mips/ath25/ar2315.c
-@@ -220,6 +220,24 @@ static struct platform_device ar2315_gpi
- .num_resources = ARRAY_SIZE(ar2315_gpio_res)
- };
-
-+static struct resource ar2315_wdt_res[] = {
-+ {
-+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_RST_BASE + AR2315_WDT_TIMER,
-+ .end = AR2315_RST_BASE + AR2315_WDT_TIMER + 8 - 1,
-+ },
-+ {
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device ar2315_wdt = {
-+ .id = 0,
-+ .name = "ar2315-wdt",
-+ .resource = ar2315_wdt_res,
-+ .num_resources = ARRAY_SIZE(ar2315_wdt_res)
-+};
-+
- static struct resource ar2315_spiflash_res[] = {
- {
- .name = "spiflash_read",
-@@ -252,6 +270,11 @@ void __init ar2315_init_devices(void)
- ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
- platform_device_register(&ar2315_gpio);
-
-+ ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
-+ AR2315_MISC_IRQ_WATCHDOG);
-+ ar2315_wdt_res[1].end = ar2315_wdt_res[1].start;
-+ platform_device_register(&ar2315_wdt);
-+
- platform_device_register(&ar2315_spiflash);
-
- ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
+++ /dev/null
---- a/drivers/mtd/redboot.c
-+++ b/drivers/mtd/redboot.c
-@@ -30,6 +30,8 @@
- #include <linux/mtd/partitions.h>
- #include <linux/module.h>
-
-+#define BOARD_CONFIG_PART "boardconfig"
-+
- struct fis_image_desc {
- unsigned char name[16]; // Null terminated name
- uint32_t flash_base; // Address within FLASH of image
-@@ -60,6 +62,7 @@ static int parse_redboot_partitions(stru
- struct mtd_partition **pparts,
- struct mtd_part_parser_data *data)
- {
-+ unsigned long max_offset = 0;
- int nrparts = 0;
- struct fis_image_desc *buf;
- struct mtd_partition *parts;
-@@ -225,14 +228,15 @@ static int parse_redboot_partitions(stru
- }
- }
- #endif
-- parts = kzalloc(sizeof(*parts)*nrparts + nulllen + namelen, GFP_KERNEL);
-+ parts = kzalloc(sizeof(*parts) * (nrparts + 1) + nulllen + namelen +
-+ sizeof(BOARD_CONFIG_PART), GFP_KERNEL);
-
- if (!parts) {
- ret = -ENOMEM;
- goto out;
- }
-
-- nullname = (char *)&parts[nrparts];
-+ nullname = (char *)&parts[nrparts + 1];
- #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
- if (nulllen > 0) {
- strcpy(nullname, nullstring);
-@@ -251,6 +255,8 @@ static int parse_redboot_partitions(stru
- }
- #endif
- for ( ; i<nrparts; i++) {
-+ if (max_offset < buf[i].flash_base + buf[i].size)
-+ max_offset = buf[i].flash_base + buf[i].size;
- parts[i].size = fl->img->size;
- parts[i].offset = fl->img->flash_base;
- parts[i].name = names;
-@@ -284,6 +290,13 @@ static int parse_redboot_partitions(stru
- fl = fl->next;
- kfree(tmp_fl);
- }
-+ if (master->size - max_offset >= master->erasesize) {
-+ parts[nrparts].size = master->size - max_offset;
-+ parts[nrparts].offset = max_offset;
-+ parts[nrparts].name = names;
-+ strcpy(names, BOARD_CONFIG_PART);
-+ nrparts++;
-+ }
- ret = nrparts;
- *pparts = parts;
- out:
+++ /dev/null
---- a/drivers/mtd/redboot.c
-+++ b/drivers/mtd/redboot.c
-@@ -79,12 +79,18 @@ static int parse_redboot_partitions(stru
- static char nullstring[] = "unallocated";
- #endif
-
-+ buf = vmalloc(master->erasesize);
-+ if (!buf)
-+ return -ENOMEM;
-+
-+ restart:
- if ( directory < 0 ) {
- offset = master->size + directory * master->erasesize;
- while (mtd_block_isbad(master, offset)) {
- if (!offset) {
- nogood:
- printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
-+ vfree(buf);
- return -EIO;
- }
- offset -= master->erasesize;
-@@ -97,10 +103,6 @@ static int parse_redboot_partitions(stru
- goto nogood;
- }
- }
-- buf = vmalloc(master->erasesize);
--
-- if (!buf)
-- return -ENOMEM;
-
- printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
- master->name, offset);
-@@ -173,6 +175,11 @@ static int parse_redboot_partitions(stru
- }
- if (i == numslots) {
- /* Didn't find it */
-+ if (offset + master->erasesize < master->size) {
-+ /* not at the end of the flash yet, maybe next block */
-+ directory++;
-+ goto restart;
-+ }
- printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
- master->name);
- ret = 0;
+++ /dev/null
---- a/drivers/mtd/redboot.c
-+++ b/drivers/mtd/redboot.c
-@@ -58,6 +58,22 @@ static inline int redboot_checksum(struc
- return 1;
- }
-
-+static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset)
-+{
-+ struct mtd_erase_region_info *regions = mtd->eraseregions;
-+ int i;
-+
-+ for (i = 0; i < mtd->numeraseregions; i++) {
-+ if (regions[i].offset +
-+ regions[i].numblocks * regions[i].erasesize <= offset)
-+ continue;
-+
-+ return regions[i].erasesize;
-+ }
-+
-+ return mtd->erasesize;
-+}
-+
- static int parse_redboot_partitions(struct mtd_info *master,
- struct mtd_partition **pparts,
- struct mtd_part_parser_data *data)
-@@ -74,6 +90,7 @@ static int parse_redboot_partitions(stru
- int namelen = 0;
- int nulllen = 0;
- int numslots;
-+ int first_slot;
- unsigned long offset;
- #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
- static char nullstring[] = "unallocated";
-@@ -186,7 +203,10 @@ static int parse_redboot_partitions(stru
- goto out;
- }
-
-- for (i = 0; i < numslots; i++) {
-+ first_slot = (buf[i].flash_base & (master->erasesize - 1)) /
-+ sizeof(struct fis_image_desc);
-+
-+ for (i = first_slot; i < first_slot + numslots; i++) {
- struct fis_list *new_fl, **prev;
-
- if (buf[i].name[0] == 0xff) {
-@@ -262,12 +282,13 @@ static int parse_redboot_partitions(stru
- }
- #endif
- for ( ; i<nrparts; i++) {
-- if (max_offset < buf[i].flash_base + buf[i].size)
-- max_offset = buf[i].flash_base + buf[i].size;
- parts[i].size = fl->img->size;
- parts[i].offset = fl->img->flash_base;
- parts[i].name = names;
-
-+ if (max_offset < parts[i].offset + parts[i].size)
-+ max_offset = parts[i].offset + parts[i].size;
-+
- strcpy(names, fl->img->name);
- #ifdef CONFIG_MTD_REDBOOT_PARTS_READONLY
- if (!memcmp(names, "RedBoot", 8) ||
-@@ -297,7 +318,9 @@ static int parse_redboot_partitions(stru
- fl = fl->next;
- kfree(tmp_fl);
- }
-- if (master->size - max_offset >= master->erasesize) {
-+
-+ if (master->size - max_offset >=
-+ mtd_get_offset_erasesize(master, max_offset)) {
- parts[nrparts].size = master->size - max_offset;
- parts[nrparts].offset = max_offset;
- parts[nrparts].name = names;
+++ /dev/null
---- a/arch/mips/ath25/Makefile
-+++ b/arch/mips/ath25/Makefile
-@@ -8,7 +8,7 @@
- # Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
- #
-
--obj-y += board.o prom.o devices.o
-+obj-y += board.o prom.o devices.o reset.o
-
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-
---- /dev/null
-+++ b/arch/mips/ath25/reset.c
-@@ -0,0 +1,57 @@
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/platform_device.h>
-+#include <linux/gpio_keys.h>
-+#include <linux/input.h>
-+#include <ath25_platform.h>
-+#include "devices.h"
-+
-+static int __init
-+ar231x_init_reset(void)
-+{
-+ struct platform_device *pdev;
-+ struct gpio_keys_platform_data pdata;
-+ struct gpio_keys_button *p;
-+ int err;
-+
-+ if (ath25_board.config->reset_config_gpio == 0xffff)
-+ return -ENODEV;
-+
-+ p = kzalloc(sizeof(*p), GFP_KERNEL);
-+ if (!p)
-+ goto err;
-+
-+ p->desc = "reset";
-+ p->type = EV_KEY;
-+ p->code = KEY_RESTART;
-+ p->debounce_interval = 60;
-+ p->gpio = ath25_board.config->reset_config_gpio;
-+
-+ memset(&pdata, 0, sizeof(pdata));
-+ pdata.poll_interval = 20;
-+ pdata.buttons = p;
-+ pdata.nbuttons = 1;
-+
-+ pdev = platform_device_alloc("gpio-keys-polled", 0);
-+ if (!pdev)
-+ goto err_free;
-+
-+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
-+ if (err)
-+ goto err_put_pdev;
-+
-+ err = platform_device_add(pdev);
-+ if (err)
-+ goto err_put_pdev;
-+
-+ return 0;
-+
-+err_put_pdev:
-+ platform_device_put(pdev);
-+err_free:
-+ kfree(p);
-+err:
-+ return -ENOMEM;
-+}
-+
-+module_init(ar231x_init_reset);
+++ /dev/null
---- a/drivers/net/ethernet/atheros/ar231x/ar231x.c
-+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
-@@ -135,6 +135,7 @@ static int ar231x_mdiobus_write(struct m
- static int ar231x_mdiobus_reset(struct mii_bus *bus);
- static int ar231x_mdiobus_probe(struct net_device *dev);
- static void ar231x_adjust_link(struct net_device *dev);
-+static bool no_phy;
-
- #ifndef ERR
- #define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
-@@ -167,6 +168,32 @@ static const struct net_device_ops ar231
- #endif
- };
-
-+static int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id)
-+{
-+ int phy_reg;
-+
-+ /**
-+ * Grab the bits from PHYIR1, and put them
-+ * in the upper half.
-+ */
-+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
-+
-+ if (phy_reg < 0)
-+ return -EIO;
-+
-+ *phy_id = (phy_reg & 0xffff) << 16;
-+
-+ /* Grab the bits from PHYIR2, and put them in the lower half */
-+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
-+
-+ if (phy_reg < 0)
-+ return -EIO;
-+
-+ *phy_id |= (phy_reg & 0xffff);
-+
-+ return 0;
-+}
-+
- static int ar231x_probe(struct platform_device *pdev)
- {
- struct net_device *dev;
-@@ -273,6 +300,24 @@ static int ar231x_probe(struct platform_
-
- mdiobus_register(sp->mii_bus);
-
-+ /**
-+ * Workaround for Micrel switch, which is only available on
-+ * one PHY and cannot be configured through MDIO.
-+ */
-+ if (!no_phy) {
-+ u32 phy_id = 0;
-+
-+ get_phy_id(sp->mii_bus, 1, &phy_id);
-+ if (phy_id == 0x00221450)
-+ no_phy = true;
-+ }
-+ if (no_phy) {
-+ sp->link = 1;
-+ netif_carrier_on(dev);
-+ return 0;
-+ }
-+ no_phy = true;
-+
- if (ar231x_mdiobus_probe(dev) != 0) {
- printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
- rx_tasklet_cleanup(dev);
-@@ -329,8 +374,10 @@ static int ar231x_remove(struct platform
- rx_tasklet_cleanup(dev);
- ar231x_init_cleanup(dev);
- unregister_netdev(dev);
-- mdiobus_unregister(sp->mii_bus);
-- mdiobus_free(sp->mii_bus);
-+ if (sp->mii_bus) {
-+ mdiobus_unregister(sp->mii_bus);
-+ mdiobus_free(sp->mii_bus);
-+ }
- kfree(dev);
- return 0;
- }
-@@ -1079,6 +1126,9 @@ static int ar231x_ioctl(struct net_devic
- {
- struct ar231x_private *sp = netdev_priv(dev);
-
-+ if (!sp->phy_dev)
-+ return -ENODEV;
-+
- switch (cmd) {
- case SIOCGMIIPHY:
- case SIOCGMIIREG:
+++ /dev/null
---- a/arch/mips/ath25/ar2315.c
-+++ b/arch/mips/ath25/ar2315.c
-@@ -23,6 +23,7 @@
- #include <linux/reboot.h>
- #include <linux/delay.h>
- #include <linux/gpio.h>
-+#include <linux/leds.h>
- #include <asm/bootinfo.h>
- #include <asm/reboot.h>
- #include <asm/time.h>
-@@ -260,6 +261,50 @@ static struct platform_device ar2315_spi
- .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
- };
-
-+#ifdef CONFIG_LEDS_GPIO
-+static struct gpio_led ar2315_leds[6];
-+static struct gpio_led_platform_data ar2315_led_data = {
-+ .leds = (void *)ar2315_leds,
-+};
-+
-+static struct platform_device ar2315_gpio_leds = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = (void *)&ar2315_led_data,
-+ }
-+};
-+
-+static void __init ar2315_init_gpio_leds(void)
-+{
-+ static char led_names[6][6];
-+ int i, led = 0;
-+
-+ ar2315_led_data.num_leds = 0;
-+ for (i = 1; i < 8; i++) {
-+ if ((i == AR2315_RESET_GPIO) ||
-+ (i == ath25_board.config->reset_config_gpio))
-+ continue;
-+
-+ if (i == ath25_board.config->sys_led_gpio)
-+ strcpy(led_names[led], "wlan");
-+ else
-+ sprintf(led_names[led], "gpio%d", i);
-+
-+ ar2315_leds[led].name = led_names[led];
-+ ar2315_leds[led].gpio = i;
-+ ar2315_leds[led].active_low = 0;
-+ led++;
-+ }
-+ ar2315_led_data.num_leds = led;
-+ platform_device_register(&ar2315_gpio_leds);
-+}
-+#else
-+static inline void ar2315_init_gpio_leds(void)
-+{
-+}
-+#endif
-+
- void __init ar2315_init_devices(void)
- {
- /* Find board configuration */
-@@ -270,6 +315,8 @@ void __init ar2315_init_devices(void)
- ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
- platform_device_register(&ar2315_gpio);
-
-+ ar2315_init_gpio_leds();
-+
- ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
- AR2315_MISC_IRQ_WATCHDOG);
- ar2315_wdt_res[1].end = ar2315_wdt_res[1].start;
---- a/arch/mips/ath25/ar5312.c
-+++ b/arch/mips/ath25/ar5312.c
-@@ -23,6 +23,7 @@
- #include <linux/mtd/physmap.h>
- #include <linux/reboot.h>
- #include <linux/gpio.h>
-+#include <linux/leds.h>
- #include <asm/bootinfo.h>
- #include <asm/reboot.h>
- #include <asm/time.h>
-@@ -231,6 +232,23 @@ static struct platform_device ar5312_gpi
- .num_resources = ARRAY_SIZE(ar5312_gpio_res),
- };
-
-+#ifdef CONFIG_LEDS_GPIO
-+static struct gpio_led ar5312_leds[] = {
-+ { .name = "wlan", .gpio = 0, .active_low = 1, },
-+};
-+
-+static const struct gpio_led_platform_data ar5312_led_data = {
-+ .num_leds = ARRAY_SIZE(ar5312_leds),
-+ .leds = (void *)ar5312_leds,
-+};
-+
-+static struct platform_device ar5312_gpio_leds = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev.platform_data = (void *)&ar5312_led_data,
-+};
-+#endif
-+
- static void __init ar5312_flash_init(void)
- {
- void __iomem *flashctl_base;
-@@ -301,6 +319,11 @@ void __init ar5312_init_devices(void)
-
- platform_device_register(&ar5312_gpio);
-
-+#ifdef CONFIG_LEDS_GPIO
-+ ar5312_leds[0].gpio = config->sys_led_gpio;
-+ platform_device_register(&ar5312_gpio_leds);
-+#endif
-+
- /* Fix up MAC addresses if necessary */
- if (is_broadcast_ether_addr(config->enet0_mac))
- ether_addr_copy(config->enet0_mac, config->enet1_mac);
projects / openwrt / staging / ynezz.git / commitdiff