OMAPDSS: APPLY: skip isr register and config for manual update displays
authorTomi Valkeinen <tomi.valkeinen@ti.com>
Fri, 4 Nov 2011 07:35:59 +0000 (09:35 +0200)
committerTomi Valkeinen <tomi.valkeinen@ti.com>
Fri, 2 Dec 2011 06:54:32 +0000 (08:54 +0200)
The mechanism to cache manager and overlay settings and configure them
into the HW registers in VSYNC is meant only for auto-update displays,
as it doesn't make sense (and doesn't work) for manual-update displays.

This patchs adds a check so that we skip the above for manual update
displays.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
drivers/video/omap2/dss/apply.c

index 46fdb63a4dbc1137fdd1352accf9ffd666c9ea74..0da8081fc7c439b9309ff5f09bf5fb41031d300c 100644 (file)
@@ -629,23 +629,26 @@ int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
        }
 
        r = 0;
-       if (!dss_cache.irq_enabled) {
-               u32 mask;
+       if (!mgr_manual_update(mgr)) {
+               if (!dss_cache.irq_enabled) {
+                       u32 mask;
 
-               mask = DISPC_IRQ_VSYNC  | DISPC_IRQ_EVSYNC_ODD |
-                       DISPC_IRQ_EVSYNC_EVEN;
-               if (dss_has_feature(FEAT_MGR_LCD2))
-                       mask |= DISPC_IRQ_VSYNC2;
+                       mask = DISPC_IRQ_VSYNC  | DISPC_IRQ_EVSYNC_ODD |
+                               DISPC_IRQ_EVSYNC_EVEN;
+                       if (dss_has_feature(FEAT_MGR_LCD2))
+                               mask |= DISPC_IRQ_VSYNC2;
 
-               r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask);
+                       r = omap_dispc_register_isr(dss_apply_irq_handler,
+                                       NULL, mask);
 
-               if (r)
-                       DSSERR("failed to register apply isr\n");
+                       if (r)
+                               DSSERR("failed to register apply isr\n");
 
-               dss_cache.irq_enabled = true;
-       }
+                       dss_cache.irq_enabled = true;
+               }
 
-       configure_dispc();
+               configure_dispc();
+       }
 
        spin_unlock_irqrestore(&dss_cache.lock, flags);