ipq40xx: add PSGMII PHY mode define

PSGMII is a Qualcomm specific mode similar to QSGMII but it has 5 SGMII
lines instead of 4 in QSGMII.

This just adds the support for the PHY layer to be able to identify the
mode for further use.
It is required for the DSA driver.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>

diff --git a/target/linux/ipq40xx/patches-5.10/704-net-phy-define-PSGMII-PHY-interface-mode.patch b/target/linux/ipq40xx/patches-5.10/704-net-phy-define-PSGMII-PHY-interface-mode.patch
new file mode 100644 (file)
index 0000000..b98201e
--- /dev/null
+++ b/target/linux/ipq40xx/patches-5.10/704-net-phy-define-PSGMII-PHY-interface-mode.patch
@@ -0,0 +1,61 @@
+From 3e1825e00dafb68eec25df389b63f3ab3d905b59 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <j4g8y7@gmail.com>
+Date: Fri, 25 Dec 2020 08:02:47 +0100
+Subject: [PATCH] net: phy: define PSGMII PHY interface mode
+
+The PSGMII interface is similar to QSGMII. The main difference
+is that the PSGMII interface combines five SGMII lines into a
+single link while in QSGMII only four lines are combined.
+
+Similarly to the QSGMII, this interface mode might also needs
+special handling within the MAC driver.
+
+Add definitions for the PHY layer to allow to express this type
+of connection between the MAC and PHY.
+
+Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
+---
+ Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
+ drivers/net/phy/phylink.c                                      | 1 +
+ include/linux/phy.h                                            | 3 +++
+ 3 files changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
++++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+@@ -64,6 +64,7 @@ properties:
+       - mii
+       - gmii
+       - sgmii
++      - psgmii
+       - qsgmii
+       - tbi
+       - rev-mii
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -289,6 +289,7 @@ static int phylink_parse_mode(struct phy
+ 
+               switch (pl->link_config.interface) {
+               case PHY_INTERFACE_MODE_SGMII:
++              case PHY_INTERFACE_MODE_PSGMII:
+               case PHY_INTERFACE_MODE_QSGMII:
+                       phylink_set(pl->supported, 10baseT_Half);
+                       phylink_set(pl->supported, 10baseT_Full);
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -134,6 +134,7 @@ typedef enum {
+       PHY_INTERFACE_MODE_XGMII,
+       PHY_INTERFACE_MODE_XLGMII,
+       PHY_INTERFACE_MODE_MOCA,
++      PHY_INTERFACE_MODE_PSGMII,
+       PHY_INTERFACE_MODE_QSGMII,
+       PHY_INTERFACE_MODE_TRGMII,
+       PHY_INTERFACE_MODE_100BASEX,
+@@ -201,6 +202,8 @@ static inline const char *phy_modes(phy_
+               return "xlgmii";
+       case PHY_INTERFACE_MODE_MOCA:
+               return "moca";
++      case PHY_INTERFACE_MODE_PSGMII:
++              return "psgmii";
+       case PHY_INTERFACE_MODE_QSGMII:
+               return "qsgmii";
+       case PHY_INTERFACE_MODE_TRGMII:

diff --git a/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch b/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch
new file mode 100644 (file)
index 0000000..9791652
--- /dev/null
+++ b/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch
@@ -0,0 +1,61 @@
+From 3e1825e00dafb68eec25df389b63f3ab3d905b59 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <j4g8y7@gmail.com>
+Date: Fri, 25 Dec 2020 08:02:47 +0100
+Subject: [PATCH] net: phy: define PSGMII PHY interface mode
+
+The PSGMII interface is similar to QSGMII. The main difference
+is that the PSGMII interface combines five SGMII lines into a
+single link while in QSGMII only four lines are combined.
+
+Similarly to the QSGMII, this interface mode might also needs
+special handling within the MAC driver.
+
+Add definitions for the PHY layer to allow to express this type
+of connection between the MAC and PHY.
+
+Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
+---
+ Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
+ drivers/net/phy/phylink.c                                      | 1 +
+ include/linux/phy.h                                            | 3 +++
+ 3 files changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
++++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+@@ -64,6 +64,7 @@ properties:
+       - mii
+       - gmii
+       - sgmii
++      - psgmii
+       - qsgmii
+       - tbi
+       - rev-mii
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -293,6 +293,7 @@ static int phylink_parse_mode(struct phy
+ 
+               switch (pl->link_config.interface) {
+               case PHY_INTERFACE_MODE_SGMII:
++              case PHY_INTERFACE_MODE_PSGMII:
+               case PHY_INTERFACE_MODE_QSGMII:
+                       phylink_set(pl->supported, 10baseT_Half);
+                       phylink_set(pl->supported, 10baseT_Full);
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -138,6 +138,7 @@ typedef enum {
+       PHY_INTERFACE_MODE_XGMII,
+       PHY_INTERFACE_MODE_XLGMII,
+       PHY_INTERFACE_MODE_MOCA,
++      PHY_INTERFACE_MODE_PSGMII,
+       PHY_INTERFACE_MODE_QSGMII,
+       PHY_INTERFACE_MODE_TRGMII,
+       PHY_INTERFACE_MODE_100BASEX,
+@@ -209,6 +210,8 @@ static inline const char *phy_modes(phy_
+               return "xlgmii";
+       case PHY_INTERFACE_MODE_MOCA:
+               return "moca";
++      case PHY_INTERFACE_MODE_PSGMII:
++              return "psgmii";
+       case PHY_INTERFACE_MODE_QSGMII:
+               return "qsgmii";
+       case PHY_INTERFACE_MODE_TRGMII: