static void ni_e_series_enable_second_irq(struct comedi_device *dev,
unsigned gpct_index, short enable)
{
- const struct ni_board_struct *board = comedi_board(dev);
struct ni_private *devpriv = dev->private;
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
return;
switch (gpct_index) {
case 0:
unsigned offset;
unsigned int dither;
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
ni_m_series_load_channelgain_list(dev, n_chan, list);
return;
}
("ni_mio_common: timeout in ni_ai_insn_read\n");
return -ETIME;
}
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
dl = devpriv->readl(dev, M_Offset_AI_FIFO_Data);
dl &= mask;
data[n] = dl;
case INSN_CONFIG_ANALOG_TRIG:
return ni_ai_config_analog_trig(dev, s, insn, data);
case INSN_CONFIG_ALT_SOURCE:
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
MSeries_AI_Bypass_Mode_Mux_Mask |
unsigned int chanspec[], unsigned int n_chans,
int timed)
{
- const struct ni_board_struct *board = comedi_board(dev);
+ struct ni_private *devpriv = dev->private;
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
timed);
else
struct comedi_subdevice *s,
struct comedi_insn *insn, unsigned int *data)
{
- const struct ni_board_struct *board = comedi_board(dev);
struct ni_private *devpriv = dev->private;
unsigned int chan = CR_CHAN(insn->chanspec);
unsigned int invert;
devpriv->ao[chan] = data[0];
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
devpriv->writew(dev, data[0], M_Offset_DAC_Direct_Data(chan));
} else
devpriv->writew(dev, data[0] ^ invert,
devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
switch (cmd->stop_src) {
case TRIG_COUNT:
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
/* this is how the NI example code does it for m-series boards, verified correct with 6259 */
devpriv->stc_writel(dev, cmd->stop_arg - 1,
AO_UC_Load_A_Register);
unsigned bits;
devpriv->ao_mode1 &= ~AO_Multiple_Channels;
bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
- if (board->reg_type &
- (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
+ if (devpriv->is_m_series ||
+ board->reg_type & ni_reg_6xxx_mask) {
bits |= AO_Number_Of_Channels(0);
} else {
bits |=
#if 0
/* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
verified with bus analyzer. */
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
bits |= AO_Number_Of_DAC_Packages;
#endif
devpriv->stc_writew(dev, bits, AO_Personal_Register);
devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
devpriv->ao_mode2 = 0;
devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
devpriv->ao_mode3 = AO_Last_Gate_Disable;
else
devpriv->ao_mode3 = 0;
static void handle_cdio_interrupt(struct comedi_device *dev)
{
- const struct ni_board_struct *board = comedi_board(dev);
struct ni_private *devpriv = dev->private;
unsigned cdio_status;
struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
unsigned long flags;
#endif
- if ((board->reg_type & ni_reg_m_series_mask) == 0)
+ if (!devpriv->is_m_series)
return;
#ifdef PCIDMA
spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
{
- const struct ni_board_struct *board = comedi_board(dev);
+ struct ni_private *devpriv = dev->private;
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
return ni_m_series_get_pfi_routing(dev, chan);
else
return ni_old_get_pfi_routing(dev, chan);
static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
unsigned source)
{
- const struct ni_board_struct *board = comedi_board(dev);
+ struct ni_private *devpriv = dev->private;
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
return ni_m_series_set_pfi_routing(dev, chan, source);
else
return ni_old_set_pfi_routing(dev, chan, source);
unsigned pfi_channel,
enum ni_pfi_filter_select filter)
{
- const struct ni_board_struct *board = comedi_board(dev);
struct ni_private *devpriv = dev->private;
unsigned bits;
- if ((board->reg_type & ni_reg_m_series_mask) == 0)
+ if (!devpriv->is_m_series)
return -ENOTSUPP;
+
bits = devpriv->readl(dev, M_Offset_PFI_Filter);
bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
struct comedi_insn *insn,
unsigned int *data)
{
- const struct ni_board_struct *board = comedi_board(dev);
struct ni_private *devpriv = dev->private;
- if (!(board->reg_type & ni_reg_m_series_mask))
+ if (!devpriv->is_m_series)
return -ENOTSUPP;
if (comedi_dio_update_state(s, data))
static int ni_set_master_clock(struct comedi_device *dev,
unsigned source, unsigned period_ns)
{
- const struct ni_board_struct *board = comedi_board(dev);
struct ni_private *devpriv = dev->private;
if (source == NI_MIO_INTERNAL_CLOCK) {
devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
RTSI_Trig_Direction_Register);
devpriv->clock_ns = TIMEBASE_1_NS;
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
devpriv->clock_and_fout2 &=
~(MSeries_Timebase1_Select_Bit |
MSeries_Timebase3_Select_Bit);
}
devpriv->clock_source = source;
} else {
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
return ni_mseries_set_pll_master_clock(dev, source,
period_ns);
} else {
static unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
{
- const struct ni_board_struct *board = comedi_board(dev);
+ struct ni_private *devpriv = dev->private;
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
return 8;
else
return 7;
static int ni_valid_rtsi_output_source(struct comedi_device *dev,
unsigned chan, unsigned source)
{
- const struct ni_board_struct *board = comedi_board(dev);
+ struct ni_private *devpriv = dev->private;
if (chan >= num_configurable_rtsi_channels(dev)) {
if (chan == old_RTSI_clock_channel) {
return 1;
break;
case NI_RTSI_OUTPUT_RTSI_OSC:
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
return 1;
else
return 0;
struct comedi_insn *insn,
unsigned int *data)
{
- const struct ni_board_struct *board = comedi_board(dev);
struct ni_private *devpriv = dev->private;
unsigned int chan = CR_CHAN(insn->chanspec);
case INSN_CONFIG_DIO_OUTPUT:
if (chan < num_configurable_rtsi_channels(dev)) {
devpriv->rtsi_trig_direction_reg |=
- RTSI_Output_Bit(chan,
- (board->reg_type & ni_reg_m_series_mask) != 0);
+ RTSI_Output_Bit(chan, devpriv->is_m_series);
} else if (chan == old_RTSI_clock_channel) {
devpriv->rtsi_trig_direction_reg |=
Drive_RTSI_Clock_Bit;
case INSN_CONFIG_DIO_INPUT:
if (chan < num_configurable_rtsi_channels(dev)) {
devpriv->rtsi_trig_direction_reg &=
- ~RTSI_Output_Bit(chan,
- (board->reg_type & ni_reg_m_series_mask) != 0);
+ ~RTSI_Output_Bit(chan, devpriv->is_m_series);
} else if (chan == old_RTSI_clock_channel) {
devpriv->rtsi_trig_direction_reg &=
~Drive_RTSI_Clock_Bit;
if (chan < num_configurable_rtsi_channels(dev)) {
data[1] =
(devpriv->rtsi_trig_direction_reg &
- RTSI_Output_Bit(chan,
- (board->reg_type & ni_reg_m_series_mask) != 0))
+ RTSI_Output_Bit(chan, devpriv->is_m_series))
? INSN_CONFIG_DIO_OUTPUT
: INSN_CONFIG_DIO_INPUT;
} else if (chan == old_RTSI_clock_channel) {
static void ni_rtsi_init(struct comedi_device *dev)
{
- const struct ni_board_struct *board = comedi_board(dev);
struct ni_private *devpriv = dev->private;
/* Initialises the RTSI bus signal switch to a default state */
RTSI_Trig_Output_Bits(5,
NI_RTSI_OUTPUT_G_SRC0) |
RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
devpriv->rtsi_trig_b_output_reg |=
RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
if (board->adbits > 16)
s->subdev_flags |= SDF_LSAMPL;
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
s->subdev_flags |= SDF_SOFT_CALIBRATED;
s->n_chan = board->n_adchan;
s->len_chanlist = 512;
if (board->n_aochan) {
s->type = COMEDI_SUBD_AO;
s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
s->subdev_flags |= SDF_SOFT_CALIBRATED;
s->n_chan = board->n_aochan;
s->maxdata = (1 << board->aobits) - 1;
s->do_cmd = &ni_ao_cmd;
s->do_cmdtest = &ni_ao_cmdtest;
s->len_chanlist = board->n_aochan;
- if ((board->reg_type & ni_reg_m_series_mask) == 0)
+ if (!devpriv->is_m_series)
s->munge = ni_ao_munge;
}
s->cancel = &ni_ao_reset;
s->io_bits = 0; /* all bits input */
s->range_table = &range_digital;
s->n_chan = board->num_p0_dio_channels;
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
s->subdev_flags |=
SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */;
s->insn_bits = &ni_m_series_dio_insn_bits;
/* calibration subdevice -- ai and ao */
s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
s->type = COMEDI_SUBD_CALIB;
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
/* internal PWM analog output used for AI nonlinearity calibration */
s->subdev_flags = SDF_INTERNAL;
s->insn_config = &ni_m_series_pwm_config;
s->type = COMEDI_SUBD_MEMORY;
s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
s->maxdata = 0xff;
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
s->n_chan = M_SERIES_EEPROM_SIZE;
s->insn_read = &ni_m_series_eeprom_insn_read;
} else {
s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
s->type = COMEDI_SUBD_DIO;
s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
- if (board->reg_type & ni_reg_m_series_mask) {
+ if (devpriv->is_m_series) {
unsigned i;
s->n_chan = 16;
devpriv->writew(dev, s->state, M_Offset_PFI_DO);
s->n_chan = 10;
}
s->maxdata = 1;
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
s->insn_bits = &ni_pfi_insn_bits;
s->insn_config = &ni_pfi_insn_config;
ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
s->insn_config = ni_rtsi_insn_config;
ni_rtsi_init(dev);
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
counter_variant = ni_gpct_variant_m_series;
else
counter_variant = ni_gpct_variant_e_series;
s->type = COMEDI_SUBD_COUNTER;
s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
s->n_chan = 3;
- if (board->reg_type & ni_reg_m_series_mask)
+ if (devpriv->is_m_series)
s->maxdata = 0xffffffff;
else
s->maxdata = 0xffffff;
if (board->reg_type & ni_reg_6xxx_mask) {
devpriv->writeb(dev, 0, Magic_611x);
- } else if (board->reg_type & ni_reg_m_series_mask) {
+ } else if (devpriv->is_m_series) {
int channel;
for (channel = 0; channel < board->n_aochan; ++channel) {
devpriv->writeb(dev, 0xf,