};
struct ni_670x_private {
- void __iomem *mmio;
int boardtype;
int dio;
unsigned int ao_readback[32];
for (i = 0; i < insn->n; i++) {
/* First write in channel register which channel to use */
writel(((chan & 15) << 1) | ((chan & 16) >> 4),
- devpriv->mmio + AO_CHAN_OFFSET);
+ dev->mmio + AO_CHAN_OFFSET);
/* write channel value */
- writel(data[i], devpriv->mmio + AO_VALUE_OFFSET);
+ writel(data[i], dev->mmio + AO_VALUE_OFFSET);
devpriv->ao_readback[chan] = data[i];
}
struct comedi_insn *insn,
unsigned int *data)
{
- struct ni_670x_private *devpriv = dev->private;
- void __iomem *io_addr = devpriv->mmio + DIO_PORT0_DATA_OFFSET;
-
if (comedi_dio_update_state(s, data))
- writel(s->state, io_addr);
+ writel(s->state, dev->mmio + DIO_PORT0_DATA_OFFSET);
- data[1] = readl(io_addr);
+ data[1] = readl(dev->mmio + DIO_PORT0_DATA_OFFSET);
return insn->n;
}
struct comedi_insn *insn,
unsigned int *data)
{
- struct ni_670x_private *devpriv = dev->private;
int ret;
ret = comedi_dio_insn_config(dev, s, insn, data, 0);
if (ret)
return ret;
- writel(s->io_bits, devpriv->mmio + DIO_PORT0_DIR_OFFSET);
+ writel(s->io_bits, dev->mmio + DIO_PORT0_DIR_OFFSET);
return insn->n;
}
if (ret)
return ret;
- devpriv->mmio = pci_ioremap_bar(pcidev, 1);
- if (!devpriv->mmio)
+ dev->mmio = pci_ioremap_bar(pcidev, 1);
+ if (!dev->mmio)
return -ENOMEM;
ret = comedi_alloc_subdevices(dev, 2);
s->insn_config = ni_670x_dio_insn_config;
/* Config of misc registers */
- writel(0x10, devpriv->mmio + MISC_CONTROL_OFFSET);
+ writel(0x10, dev->mmio + MISC_CONTROL_OFFSET);
/* Config of ao registers */
- writel(0x00, devpriv->mmio + AO_CONTROL_OFFSET);
+ writel(0x00, dev->mmio + AO_CONTROL_OFFSET);
return 0;
}
static void ni_670x_detach(struct comedi_device *dev)
{
- struct ni_670x_private *devpriv = dev->private;
struct comedi_subdevice *s;
if (dev->n_subdevices) {
if (s)
kfree(s->range_table_list);
}
- if (devpriv && devpriv->mmio)
- iounmap(devpriv->mmio);
+ if (dev->mmio)
+ iounmap(dev->mmio);
comedi_pci_disable(dev);
}