FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init

We found that the DUT will be hanged if we don't set the bit_1 of the
PMUCRU_GATEDIS_CON0. But, from the TRM, there is weird that the bit_1
is set the clk_center1_gating_dis, not clk_pmum0_gating_dis. Is the
TRM incorrect? We need to check it with the IC team and re-clean the
commit message and explain it tomorrow.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
index 11bc0eaefb18638cd302ba88fff58181a6ac90a6..66f3a19c864883fa552f0379b3a693ab9ea5b73d 100644 (file)
--- a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
+++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
@@ -53,7 +53,8 @@ void m0_init(void)
                                      0xf, 0));
 
        /* gating disable for M0 */
-       mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(0));
+       mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0,
+                     BITS_WITH_WMASK(0x3, 0x3, 0));
 
        /*
         * To switch the parent to xin24M and div == 1,