Add multi-chip NAND support for the TQM8548 modules

This patches configures the NAND UPM-FSL driver with multi-chip
support for the Micron MT29F8G08FAB NAND flash memory on the
TQM8548 modules.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
index 8133fdc40eef8f902fec646c697d4846438ffb90..3da689a9e46ffb3105f1129735032c8c2c785d32 100644 (file)
--- a/board/tqc/tqm85xx/nand.c
+++ b/board/tqc/tqm85xx/nand.c
@@ -385,7 +385,7 @@ static void upmb_write (u_char addr, ulong val)
                        MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
 
        /* dummy access to perform write */
-       out_8 ((void __iomem *)CONFIG_SYS_NAND0_BASE, 0);
+       out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0);
 
        clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
 }
@@ -446,7 +446,10 @@ static struct fsl_upm_nand fun = {
        .width = 8,
        .upm_cmd_offset = 0x08,
        .upm_addr_offset = 0x10,
+       .upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST,
+       .chip_offset = CONFIG_SYS_NAND_CS_DIST,
        .chip_delay = NAND_BIG_DELAY_US,
+       .wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER,
 };
 
 void board_nand_select_device (struct nand_chip *nand, int chip)

diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 72db26c7b13c3dce27901bc99f6c206869af2412..2ef24cd7e506603e5b0fd825c1d5fe5d135c0ee6 100644 (file)
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -371,35 +371,17 @@
 #define        CONFIG_SYS_NAND_CS_DIST 0x200
 
 #define CONFIG_SYS_NAND_SIZE           0x8000
-#define CONFIG_SYS_NAND0_BASE          (CONFIG_SYS_CCSRBAR + 0x03010000)
-#define CONFIG_SYS_NAND1_BASE          (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND2_BASE          (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND3_BASE          (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE     2       /* Max number of NAND devices   */
-
-#if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
-#elif (CONFIG_SYS_MAX_NAND_DEVICE == 2)
-#define        CONFIG_SYS_NAND_QUIET_TEST      1
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
-                            CONFIG_SYS_NAND1_BASE, \
-}
-#elif (CONFIG_SYS_MAX_NAND_DEVICE == 4)
-#define        CONFIG_SYS_NAND_QUIET_TEST      1
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
-                            CONFIG_SYS_NAND1_BASE, \
-                            CONFIG_SYS_NAND2_BASE, \
-                            CONFIG_SYS_NAND3_BASE, \
-}
-#endif
+#define CONFIG_SYS_NAND_BASE           (CONFIG_SYS_CCSRBAR + 0x03010000)
+
+#define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND devices   */
+#define CONFIG_SYS_NAND_MAX_CHIPS      2       /* Number of chips per device   */
 
 /* CS3 for NAND Flash */
-#define CONFIG_SYS_BR3_PRELIM          ((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \
-                                BR_MS_UPMB | BR_V)
+#define CONFIG_SYS_BR3_PRELIM          ((CONFIG_SYS_NAND_BASE & BR_BA) | \
+                                        BR_PS_8 | BR_MS_UPMB | BR_V)
 #define CONFIG_SYS_OR3_PRELIM          (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
 
-#define NAND_BIG_DELAY_US       25     /* max tR for Samsung devices   */
+#define NAND_BIG_DELAY_US              25      /* max tR for Samsung devices   */
 
 #endif /* CONFIG_NAND */