wl18xx: FW/PHY arguments added for PG2
authorIdo Reis <idor@ti.com>
Mon, 23 Apr 2012 13:49:19 +0000 (16:49 +0300)
committerLuciano Coelho <coelho@ti.com>
Thu, 7 Jun 2012 15:10:57 +0000 (18:10 +0300)
PG2 requires 4 new parameters that to be passed to the PHY.

Use the actual PHY initialization struct size for the mem size of the
PHY_INIT section, to account for additions in params.

[Make sure PG1 still gets the original struct - Arik]

Signed-off-by: Ido Reis <idor@ti.com>
Signed-off-by: Arik Nemtsov <arik@wizery.com>
Signed-off-by: Luciano Coelho <coelho@ti.com>
drivers/net/wireless/ti/wl18xx/conf.h
drivers/net/wireless/ti/wl18xx/main.c
drivers/net/wireless/ti/wl18xx/reg.h

index ffad302b6cb760fedac756edbdd19d1f2483ecae..4e0f189b2539800b5c74e33f3f6d5e4de29d0103 100644 (file)
@@ -44,6 +44,10 @@ struct wl18xx_conf_phy {
        u8 clock_valid_on_wake_up;
        u8 secondary_clock_setting_time;
        u8 pwr_limit_reference_11_abg;
+       u8 psat;
+       s8 low_power_val;
+       s8 med_power_val;
+       s8 high_power_val;
 };
 
 struct wl18xx_priv_conf {
index 57b4a1089d0da704d158439931c8f119f37a30b2..bdf4ee12914d6e4c8a4d42ca33194446823cd942 100644 (file)
@@ -511,6 +511,10 @@ static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
                .enable_tx_low_pwr_on_siso_rdl  = 0x00,
                .rx_profile                     = 0x00,
                .pwr_limit_reference_11_abg     = 0xc8,
+               .psat                           = 0,
+               .low_power_val                  = 0x00,
+               .med_power_val                  = 0x0a,
+               .high_power_val                 = 0x1e,
        },
 };
 
@@ -713,6 +717,7 @@ static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
        struct wl18xx_priv *priv = wl->priv;
        struct wl18xx_conf_phy *phy = &priv->conf.phy;
        struct wl18xx_mac_and_phy_params params;
+       size_t len;
 
        memset(&params, 0, sizeof(params));
 
@@ -752,9 +757,21 @@ static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
 
        params.board_type = priv->board_type;
 
+       /* for PG2 only */
+       params.psat = phy->psat;
+       params.low_power_val = phy->low_power_val;
+       params.med_power_val = phy->med_power_val;
+       params.high_power_val = phy->high_power_val;
+
+       /* the parameters struct is smaller for PG1 */
+       if (wl->chip.id == CHIP_ID_185x_PG10)
+               len = offsetof(struct wl18xx_mac_and_phy_params, psat) + 1;
+       else
+               len = sizeof(params);
+
        wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
        wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&params,
-                    sizeof(params), false);
+                    len, false);
 }
 
 static void wl18xx_enable_interrupts(struct wl1271 *wl)
index e81f60913e88ad65c57c85a46aa7b07dbc246e89..a824b26702a89fab63a75f2c2351777a2cc076c8 100644 (file)
@@ -236,6 +236,12 @@ struct wl18xx_mac_and_phy_params {
        u8 clock_valid_on_wake_up;
        u8 secondary_clock_setting_time;
        u8 board_type;
+       /* enable point saturation */
+       u8 psat;
+       /* low/medium/high Tx power in dBm */
+       s8 low_power_val;
+       s8 med_power_val;
+       s8 high_power_val;
        u8 padding[1];
 } __packed;