drm/i915/psr: Update PSR2 SU corruption workaround comment

Turn out it is not a DMC bug it is actually a HW one, so this
workaround will be needed for current gens, lets update the comment
and remove the FIXME.

BSpec: 7723
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190406005112.27205-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index aacf5c6f6d954d3969d8105713adc3be9fb51317..361d231c888bdad2337c56b825f209b2ee1c9b13 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -534,10 +534,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
                val |= EDP_PSR2_TP2_TIME_2500us;
 
        /*
-        * FIXME: There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin
-        * and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after
-        * exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now
-        * lets workaround the issue by cleaning PSR_CTL before enable PSR2.
+        * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
+        * recommending keep this bit unset while PSR2 is enabled.
         */
        I915_WRITE(EDP_PSR_CTL, 0);