octeontx2-af: Add L3 and L4 packet verification mailbox
authorVidhya Raman <vraman@marvell.com>
Sun, 2 Dec 2018 12:47:47 +0000 (18:17 +0530)
committerDavid S. Miller <davem@davemloft.net>
Tue, 4 Dec 2018 00:23:08 +0000 (16:23 -0800)
Adds mailbox support for L4 checksum verification
and L3 and L4 length verification configuration.

Signed-off-by: Vidhya Raman <vraman@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

index 146f8f9656baecb28855c1a960b417369051d859..0707a5aa6b1f28f6a31abeb903034dc0f136367b 100644 (file)
@@ -203,6 +203,7 @@ M(NIX_LF_STOP_RX,   0x800e, nix_lf_stop_rx, msg_req, msg_rsp)       \
 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg,                    \
                                 nix_mark_format_cfg,                   \
                                 nix_mark_format_cfg_rsp)               \
+M(NIX_SET_RX_CFG,      0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp)    \
 M(NIX_RXVLAN_ALLOC,    0x8012, nix_rxvlan_alloc, msg_req, msg_rsp)
 
 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
@@ -609,6 +610,15 @@ struct nix_rx_mode {
        u16     mode;
 };
 
+struct nix_rx_cfg {
+       struct mbox_msghdr hdr;
+#define NIX_RX_OL3_VERIFY   BIT(0)
+#define NIX_RX_OL4_VERIFY   BIT(1)
+       u8 len_verify; /* Outer L3/L4 len check */
+#define NIX_RX_CSUM_OL4_VERIFY  BIT(0)
+       u8 csum_verify; /* Outer L4 checksum verification */
+};
+
 struct nix_frs_cfg {
        struct mbox_msghdr hdr;
        u8      update_smq;    /* Update SMQ's min/max lens */
index 563e3bfb89a54435663e0a26f852098b5bc720d7..c6d61a3a57299f3600d473540eadda7b743fe6a7 100644 (file)
@@ -433,6 +433,9 @@ int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req,
 int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu,
                                         struct nix_mark_format_cfg  *req,
                                         struct nix_mark_format_cfg_rsp *rsp);
+int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req,
+                                   struct msg_rsp *rsp);
+
 
 /* NPC APIs */
 int rvu_npc_init(struct rvu *rvu);
index 88875ebbe10a9e4ab1f078129a105a76c6b86810..f1bd9de54cb7caf42befae7e9e344b7abf1209c7 100644 (file)
@@ -2504,6 +2504,48 @@ free_entry:
        return err;
 }
 
+int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req,
+                                   struct msg_rsp *rsp)
+{
+       struct rvu_hwinfo *hw = rvu->hw;
+       u16 pcifunc = req->hdr.pcifunc;
+       struct rvu_block *block;
+       struct rvu_pfvf *pfvf;
+       int nixlf, blkaddr;
+       u64 cfg;
+
+       pfvf = rvu_get_pfvf(rvu, pcifunc);
+       blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
+       if (!pfvf->nixlf || blkaddr < 0)
+               return NIX_AF_ERR_AF_LF_INVALID;
+
+       block = &hw->block[blkaddr];
+       nixlf = rvu_get_lf(rvu, block, pcifunc, 0);
+       if (nixlf < 0)
+               return NIX_AF_ERR_AF_LF_INVALID;
+
+       cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf));
+       /* Set the interface configuration */
+       if (req->len_verify & BIT(0))
+               cfg |= BIT_ULL(41);
+       else
+               cfg &= ~BIT_ULL(41);
+
+       if (req->len_verify & BIT(1))
+               cfg |= BIT_ULL(40);
+       else
+               cfg &= ~BIT_ULL(40);
+
+       if (req->csum_verify & BIT(0))
+               cfg |= BIT_ULL(37);
+       else
+               cfg &= ~BIT_ULL(37);
+
+       rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), cfg);
+
+       return 0;
+}
+
 static void nix_link_config(struct rvu *rvu, int blkaddr)
 {
        struct rvu_hwinfo *hw = rvu->hw;