NAND: AMD Au1550 driver reads write-only register

     During the last cleanup of the AMD Au1550 NAND driver the old buglet was
reintroduced: as the MEM_STNDCTL register is write-only and seem to always
read as 0x31, read-modify-write to it done in au1xxx_nand_init() will have the
side effect of enabling -RCS0/1 pin override (via bits 4/5 of this reg.), thus
possibly causing a contention on the static bus when the NOR flash (using
-RCS0) or board control status registers (using -RCS2) are read. Luckily, this
goes away with a first NAND access, since au1550_hwcontrol() doesn't try to
read this register before writing anymore.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>

diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index 861fb961d9425e6eb7f90ee5a4f61ba506c25b7f..839b35a386b6f8fe60021391716c52ec4f6c1768 100644 (file)
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -347,11 +347,9 @@ static int __init au1xxx_nand_init(void)
        au1550_mtd->priv = this;
        au1550_mtd->owner = THIS_MODULE;
 
-       /* disable interrupts */
-       au_writel(au_readl(MEM_STNDCTL) & ~(1 << 8), MEM_STNDCTL);
 
-       /* disable NAND boot */
-       au_writel(au_readl(MEM_STNDCTL) & ~(1 << 0), MEM_STNDCTL);
+       /* MEM_STNDCTL: disable ints, disable nand boot */
+       au_writel(0, MEM_STNDCTL);
 
 #ifdef CONFIG_MIPS_PB1550
        /* set gpio206 high */