MIPS: start{, 64}.S: fill branch delay slots with NOP instructions

The romReserved and romExcHandle handlers are
accessed by a branch instruction however the
delay slots of those instructions are not filled.

Because the start.S uses the 'noreorder' directive,
the assembler will not fill the delay slots either,
and leads to the following assembly code:

  0000056c <romReserved>:
   56c:   1000ffff        b       56c <romReserved>

  00000570 <romExcHandle>:
   570:   1000ffff        b       570 <romExcHandle>

In the resulting code, the second branch instruction
is placed into the delay slot of the first branch
instruction, which is not allowed on the MIPS
architecture.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 9c1b2f76d09bcff61c4d617da0795b7f35b9085c..22a9c1bff5e181dfb0ab0bc31c802494a237a911 100644 (file)
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -380,6 +380,8 @@ in_ram:
        /* Exception handlers */
 romReserved:
        b       romReserved
+        nop
 
 romExcHandle:
        b       romExcHandle
+        nop

diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index 2b8d531e73b84ef9d2e0280165ed1668dad9d318..bc7e41eed52a650f6bdf24be927611243b2ba20b 100644 (file)
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -259,3 +259,4 @@ in_ram:
        /* Exception handlers */
 romReserved:
        b       romReserved
+        nop