drm/i915/gvt: use array to avoid potential buffer overflow

Array 'pdp_pair' of size 1 may use index value(s) 1..7.
Changed to pdps[8] to avoid confusion.

Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/execlist.h b/drivers/gpu/drm/i915/gvt/execlist.h
index 427e40e64d41e882c114fda05478fb6e60bb8379..714d709829a2a11ab4a83c45c1a3e6a3ecaca976 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/execlist.h
+++ b/drivers/gpu/drm/i915/gvt/execlist.h
@@ -146,14 +146,11 @@ struct execlist_ring_context {
        u32 nop4;
        u32 lri_cmd_2;
        struct execlist_mmio_pair ctx_timestamp;
-       struct execlist_mmio_pair pdp3_UDW;
-       struct execlist_mmio_pair pdp3_LDW;
-       struct execlist_mmio_pair pdp2_UDW;
-       struct execlist_mmio_pair pdp2_LDW;
-       struct execlist_mmio_pair pdp1_UDW;
-       struct execlist_mmio_pair pdp1_LDW;
-       struct execlist_mmio_pair pdp0_UDW;
-       struct execlist_mmio_pair pdp0_LDW;
+       /*
+        * pdps[8]={ pdp3_UDW, pdp3_LDW, pdp2_UDW, pdp2_LDW,
+        *           pdp1_UDW, pdp1_LDW, pdp0_UDW, pdp0_LDW}
+        */
+       struct execlist_mmio_pair pdps[8];
 };
 
 struct intel_vgpu_elsp_dwords {

diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index cf5a22cb6e06e1c878ffea581580341b876aba60..462cf560492e3453a41d3ad3274e3fe60fc33e57 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -45,11 +45,10 @@ static void set_context_pdp_root_pointer(
                struct execlist_ring_context *ring_context,
                u32 pdp[8])
 {
-       struct execlist_mmio_pair *pdp_pair = &ring_context->pdp3_UDW;
        int i;
 
        for (i = 0; i < 8; i++)
-               pdp_pair[i].val = pdp[7 - i];
+               ring_context->pdps[i].val = pdp[7 - i];
 }
 
 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
@@ -1230,7 +1229,7 @@ static void read_guest_pdps(struct intel_vgpu *vgpu,
        u64 gpa;
        int i;
 
-       gpa = ring_context_gpa + RING_CTX_OFF(pdp3_UDW.val);
+       gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
 
        for (i = 0; i < 8; i++)
                intel_gvt_hypervisor_read_gpa(vgpu,