drm/imx: ipuv3-plane: fix atomic update status query for non-plus i.MX6Q

The current buffer check halves the frame rate on non-plus i.MX6Q,
as the IDMAC current buffer pointer is not yet updated when
ipu_plane_atomic_update_pending is called from the EOF irq handler.

Fixes: 70e8a0c71e9 ("drm/imx: ipuv3-plane: add function to query atomic update status")
Tested-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
index d7a727a6e3d72c15aa37539bcbda1b051b944d86..91edfe2498a601048d66b5ea7e03fedae36c0a5c 100644 (file)
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -605,7 +605,6 @@ static void ipu_plane_atomic_update(struct drm_plane *plane,
                active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
                ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
                ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
-               ipu_plane->next_buf = !active;
                if (ipu_plane_separate_alpha(ipu_plane)) {
                        active = ipu_idmac_get_current_buffer(ipu_plane->alpha_ch);
                        ipu_cpmem_set_buffer(ipu_plane->alpha_ch, !active,
@@ -710,7 +709,6 @@ static void ipu_plane_atomic_update(struct drm_plane *plane,
        ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
        ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts);
        ipu_plane_enable(ipu_plane);
-       ipu_plane->next_buf = -1;
 }
 
 static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
@@ -732,10 +730,15 @@ bool ipu_plane_atomic_update_pending(struct drm_plane *plane)
 
        if (ipu_state->use_pre)
                return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch);
-       else if (ipu_plane->next_buf >= 0)
-               return ipu_idmac_get_current_buffer(ipu_plane->ipu_ch) !=
-                      ipu_plane->next_buf;
 
+       /*
+        * Pretend no update is pending in the non-PRE/PRG case. For this to
+        * happen, an atomic update would have to be deferred until after the
+        * start of the next frame and simultaneously interrupt latency would
+        * have to be high enough to let the atomic update finish and issue an
+        * event before the previous end of frame interrupt handler can be
+        * executed.
+        */
        return false;
 }
 int ipu_planes_assign_pre(struct drm_device *dev,

diff --git a/drivers/gpu/drm/imx/ipuv3-plane.h b/drivers/gpu/drm/imx/ipuv3-plane.h
index 15e85e15d35c50205d3926880fce393910be2f94..ffacbcdd2f98e59ba47ab3a4c3b064e7065440f6 100644 (file)
--- a/drivers/gpu/drm/imx/ipuv3-plane.h
+++ b/drivers/gpu/drm/imx/ipuv3-plane.h
@@ -27,7 +27,6 @@ struct ipu_plane {
        int                     dp_flow;
 
        bool                    disabling;
-       int                     next_buf;
 };
 
 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,