int (*notify_smc_dispaly_config)(struct smu_context *smu);
int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
int (*unforce_dpm_levels)(struct smu_context *smu);
- int (*upload_dpm_level)(struct smu_context *smu, bool max,
- uint32_t feature_mask);
int (*get_profiling_clk_mask)(struct smu_context *smu,
enum amd_dpm_forced_level level,
uint32_t *sclk_mask,
((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
#define smu_unforce_dpm_levels(smu) \
((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
-#define smu_upload_dpm_level(smu, max, feature_mask) \
- ((smu)->ppt_funcs->upload_dpm_level ? (smu)->ppt_funcs->upload_dpm_level((smu), (max), (feature_mask)) : 0)
#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
#define smu_set_cpu_power_state(smu) \
dpm_table->soc_table.dpm_state.soft_max_level =
dpm_table->soc_table.dpm_levels[soft_max_level].value;
- ret = smu_upload_dpm_level(smu, false, 0xFFFFFFFF);
+ ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
if (ret) {
pr_err("Failed to upload DPM Bootup Levels!");
return ret;
}
- ret = smu_upload_dpm_level(smu, true, 0xFFFFFFFF);
+ ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
if (ret) {
pr_err("Failed to upload DPM Max Levels!");
return ret;
.notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
.force_dpm_limit_value = vega20_force_dpm_limit_value,
.unforce_dpm_levels = vega20_unforce_dpm_levels,
- .upload_dpm_level = vega20_upload_dpm_level,
.get_profiling_clk_mask = vega20_get_profiling_clk_mask,
.set_ppfeature_status = vega20_set_ppfeature_status,
.get_ppfeature_status = vega20_get_ppfeature_status,