Rationalize UART usage among different BL stages
authorSoby Mathew <soby.mathew@arm.com>
Thu, 21 Aug 2014 14:20:27 +0000 (15:20 +0100)
committerSoby Mathew <soby.mathew@arm.com>
Thu, 21 Aug 2014 15:30:25 +0000 (16:30 +0100)
This patch changes the UART port assignment for various BL stages
so as to make it consistent on the platform ports. The BL1, BL2 and
BL3-1 now uses UART0 on the FVP port and SoC UART0 on the Juno port.
The BL3-2 uses UART2 on the FVP port and FPGA UART0 on the Juno
port.

This provides an interim fix to ARM-software/tf-issues#220 until
support is added for changing the UART port for a BL image between
cold boot and runtime.

Change-Id: Iae5faea90be3d59e41e597b34a902f93e737505a

plat/fvp/tsp/tsp_fvp_setup.c
plat/juno/bl1_plat_setup.c
plat/juno/bl2_plat_setup.c
plat/juno/bl31_plat_setup.c
plat/juno/juno_def.h
plat/juno/tsp/tsp_plat_setup.c

index ae63a7d3774d0317b439d92c2271e86ec8135008..301f6693be8d52b5ccfa1e727bd4e58634c531a1 100644 (file)
@@ -72,7 +72,7 @@ void tsp_early_platform_setup(void)
         * Initialize a different console than already in use to display
         * messages from TSP
         */
-       console_init(PL011_UART1_BASE, PL011_UART1_CLK_IN_HZ, PL011_BAUDRATE);
+       console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
 
        /* Initialize the platform config for future decision making */
        fvp_config_setup();
index d2f2ab493266499b42eff826bb188864cd0f78b7..5804682c42c0db48c831517df4738d6ee23273f7 100644 (file)
@@ -75,7 +75,7 @@ void bl1_early_platform_setup(void)
        const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
 
        /* Initialize the console to provide early debug support */
-       console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
+       console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
 
        /*
         * Enable CCI-400 for this cluster. No need for locks as no other cpu is
index 5dec2d7a1e46f31842d0d50ebe0ec88668c282e2..717cfbb2f9664d0a2595135fbce4594fadd0f86b 100644 (file)
@@ -158,7 +158,7 @@ struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
 void bl2_early_platform_setup(meminfo_t *mem_layout)
 {
        /* Initialize the console to provide early debug support */
-       console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
+       console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
 
        /* Setup the BL2 memory layout */
        bl2_tzram_layout = *mem_layout;
index 131a1b1dd32bea28373924b6c1fa6baadc423e91..4a92d44a8e3e977049d4fff16a15bdd3d765f756 100644 (file)
@@ -108,7 +108,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
                               void *plat_params_from_bl2)
 {
        /* Initialize the console to provide early debug support */
-       console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
+       console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
 
        /*
         * Initialise the CCI-400 driver for BL31 so that it is accessible after
index 1eae65d6c6a2375cbab3cd285d622b3ad256b12f..15296ed8fa11a5fbdb18ba569519c58239a6b05c 100644 (file)
 
 #define PL011_UART0_CLK_IN_HZ          24000000
 #define PL011_UART1_CLK_IN_HZ          24000000
+#define PL011_UART2_CLK_IN_HZ          7273800
+#define PL011_UART3_CLK_IN_HZ          7273800
 
 /*******************************************************************************
  * NIC-400 related constants
index b999df1f876d2760b0c659a91eae95a465df6e53..2d4ab81d6094f9bb3e621eff1c668c2943f57fd2 100644 (file)
@@ -72,7 +72,7 @@ void tsp_early_platform_setup(void)
         * Initialize a different console than already in use to display
         * messages from TSP
         */
-       console_init(PL011_UART1_BASE, PL011_UART1_CLK_IN_HZ, PL011_BAUDRATE);
+       console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
 }
 
 /*******************************************************************************