MIPS: Separate XPA CPU feature into LPA and MVH

XPA (eXtended Physical Addressing) should be detected as a combination
of two architectural features:
- Large Physical Address (as per Config3.LPA). With XPA this will be set
  on MIPS32r5 cores, but it may also be set for MIPS64r2 cores too.
- MTHC0/MFHC0 instructions (as per Config5.MVH). With XPA this will be
  set, but it may also be set in VZ guest context even when Config3.LPA
  in the guest context has been cleared by the hypervisor.

As such, XPA is only usable if both bits are set. Update CPU features to
separate these two features, with cpu_has_xpa requiring both to be set.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13112/
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index da92d513a3956aabf51897fdd7f1288d6d479da7..bff73c52b273befce673219475a82085d9250d28 100644 (file)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -145,8 +145,14 @@
 # endif
 #endif
 
+#ifndef cpu_has_lpa
+#define cpu_has_lpa            (cpu_data[0].options & MIPS_CPU_LPA)
+#endif
+#ifndef cpu_has_mvh
+#define cpu_has_mvh            (cpu_data[0].options & MIPS_CPU_MVH)
+#endif
 #ifndef cpu_has_xpa
-#define cpu_has_xpa            (cpu_data[0].options & MIPS_CPU_XPA)
+#define cpu_has_xpa            (cpu_has_lpa && cpu_has_mvh)
 #endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache    (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index d9150a210df6a98fa28bfe6578b82fe295281bd2..f6cecc52a8c658a103a203157827684bae2b6ae6 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -394,7 +394,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_MAAR          MBIT_ULL(30)    /* MAAR(I) registers are present */
 #define MIPS_CPU_FRE           MBIT_ULL(31)    /* FRE & UFE bits implemented */
 #define MIPS_CPU_RW_LLB                MBIT_ULL(32)    /* LLADDR/LLB writes are allowed */
-#define MIPS_CPU_XPA           MBIT_ULL(33)    /* CPU supports Extended Physical Addressing */
+#define MIPS_CPU_LPA           MBIT_ULL(33)    /* CPU supports Large Physical Addressing */
 #define MIPS_CPU_CDMM          MBIT_ULL(34)    /* CPU has Common Device Memory Map */
 #define MIPS_CPU_BP_GHIST      MBIT_ULL(35)    /* R12K+ Branch Prediction Global History */
 #define MIPS_CPU_SP            MBIT_ULL(36)    /* Small (1KB) page support */
@@ -403,6 +403,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_NAN_2008      MBIT_ULL(39)    /* 2008 NaN implemented */
 #define MIPS_CPU_VP            MBIT_ULL(40)    /* MIPSr6 Virtual Processors (multi-threading) */
 #define MIPS_CPU_LDPTE         MBIT_ULL(41)    /* CPU has ldpte/lddir instructions */
+#define MIPS_CPU_MVH           MBIT_ULL(42)    /* CPU supports MFHC0/MTHC0 */
 
 /*
  * CPU ASE encodings

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5ca4fefb13447f49e68032927e64cbd1e02e0de8..8eda42a9ca596ba90ca84279c96cbba87df74dba 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -702,6 +702,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
                c->options |= MIPS_CPU_VINT;
        if (config3 & MIPS_CONF3_VEIC)
                c->options |= MIPS_CPU_VEIC;
+       if (config3 & MIPS_CONF3_LPA)
+               c->options |= MIPS_CPU_LPA;
        if (config3 & MIPS_CONF3_MT)
                c->ases |= MIPS_ASE_MIPSMT;
        if (config3 & MIPS_CONF3_ULRI)