drm/amd/display: Allow DP register double buffer

Remove setting DP_DB_DISABLE to avoid issues when changing
bit depth after vbios take over.
Refactor code to perform single register update for both
pixel encoding and component depth fields.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index c0e813c7ddd41db3a372218e564f0f1d70882b2e..91642e6848587b54e2d6f7b33a9ea460c133926a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -289,11 +289,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
 
        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-       if (REG(DP_DB_CNTL))
-               REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
-#endif
-
        /* set pixel encoding */
        switch (crtc_timing->pixel_encoding) {
        case PIXEL_ENCODING_YCBCR422:

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index c6a13d0486bb2a29156dab7416b6e30acb4f6ae4..6f9078f3c4d39a353686ec9b5380cc27c63ba922 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -257,20 +257,18 @@ void enc1_stream_encoder_dp_set_stream_attribute(
        uint8_t colorimetry_bpc;
        uint8_t dynamic_range_rgb = 0; /*full range*/
        uint8_t dynamic_range_ycbcr = 1; /*bt709*/
+       uint8_t dp_pixel_encoding = 0;
+       uint8_t dp_component_depth = 0;
 
        struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 
-       REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
-
        /* set pixel encoding */
        switch (crtc_timing->pixel_encoding) {
        case PIXEL_ENCODING_YCBCR422:
-               REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-                               DP_PIXEL_ENCODING_TYPE_YCBCR422);
+               dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
                break;
        case PIXEL_ENCODING_YCBCR444:
-               REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-                               DP_PIXEL_ENCODING_TYPE_YCBCR444);
+               dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
 
                if (crtc_timing->flags.Y_ONLY)
                        if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
@@ -278,8 +276,8 @@ void enc1_stream_encoder_dp_set_stream_attribute(
                                 * Color depth of Y-only could be
                                 * 8, 10, 12, 16 bits
                                 */
-                               REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-                                               DP_PIXEL_ENCODING_TYPE_Y_ONLY);
+                               dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
+
                /* Note: DP_MSA_MISC1 bit 7 is the indicator
                 * of Y-only mode.
                 * This bit is set in HW if register
@@ -287,13 +285,11 @@ void enc1_stream_encoder_dp_set_stream_attribute(
                 */
                break;
        case PIXEL_ENCODING_YCBCR420:
-               REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-                               DP_PIXEL_ENCODING_TYPE_YCBCR420);
+               dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
                REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
                break;
        default:
-               REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-                               DP_PIXEL_ENCODING_TYPE_RGB444);
+               dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
                break;
        }
 
@@ -314,32 +310,30 @@ void enc1_stream_encoder_dp_set_stream_attribute(
        /* set color depth */
        switch (crtc_timing->display_color_depth) {
        case COLOR_DEPTH_666:
-               REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-                               0);
+               dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
                break;
        case COLOR_DEPTH_888:
-               REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-                               DP_COMPONENT_PIXEL_DEPTH_8BPC);
+               dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
                break;
        case COLOR_DEPTH_101010:
-               REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-                               DP_COMPONENT_PIXEL_DEPTH_10BPC);
-
+               dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
                break;
        case COLOR_DEPTH_121212:
-               REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-                               DP_COMPONENT_PIXEL_DEPTH_12BPC);
+               dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
                break;
        case COLOR_DEPTH_161616:
-               REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-                               DP_COMPONENT_PIXEL_DEPTH_16BPC);
+               dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
                break;
        default:
-               REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-                               DP_COMPONENT_PIXEL_DEPTH_6BPC);
+               dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
                break;
        }
 
+       /* Set DP pixel encoding and component depth */
+       REG_UPDATE_2(DP_PIXEL_FORMAT,
+                       DP_PIXEL_ENCODING, dp_pixel_encoding,
+                       DP_COMPONENT_DEPTH, dp_component_depth);
+
        /* set dynamic range and YCbCr range */
 
        switch (crtc_timing->display_color_depth) {