drm/i915/execlists: Try rearranging breadcrumb flush

The addition of the DC_FLUSH failed to ensure sanctity of the post-sync
write as CI immediately got a completion CS-event before the breadcrumb
was coherent. So let's try the other idea of moving the post-sync write
into the CS_STALL.

References: https://bugs.freedesktop.org/show_bug.cgi?id=111514
References: e8f6b4952ec5 ("drm/i915/execlists: Flush the post-sync breadcrumb write harder")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190829081150.10271-2-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 171d5205962c00fd727456e41df98dddba173f97..7d460b1842dddc01a2e566eb58e2d70e1ca899eb 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2915,20 +2915,18 @@ static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
 
 static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
 {
+       cs = gen8_emit_pipe_control(cs,
+                                   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+                                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+                                   PIPE_CONTROL_DC_FLUSH_ENABLE,
+                                   0);
+
+       /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
        cs = gen8_emit_ggtt_write_rcs(cs,
                                      request->fence.seqno,
                                      request->timeline->hwsp_offset,
-                                     PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
-                                     PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-                                     PIPE_CONTROL_DC_FLUSH_ENABLE);
-
-       /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
-       /* XXX DC_FLUSH for post-sync write? (cf early context-switch bug) */
-       cs = gen8_emit_pipe_control(cs,
-                                   PIPE_CONTROL_FLUSH_ENABLE |
-                                   PIPE_CONTROL_DC_FLUSH_ENABLE |
-                                   PIPE_CONTROL_CS_STALL,
-                                   0);
+                                     PIPE_CONTROL_FLUSH_ENABLE |
+                                     PIPE_CONTROL_CS_STALL);
 
        return gen8_emit_fini_breadcrumb_footer(request, cs);
 }