drm/amdgpu: remove mmhub ip
authorHuang Rui <ray.huang@amd.com>
Wed, 31 May 2017 15:49:46 +0000 (23:49 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 6 Jun 2017 20:59:09 +0000 (16:59 -0400)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/include/amd_shared.h

index 85dc4640b19363162d51dd0e658a2f53607f5155..383a943dc83a21faf81c1d747c67e70837a23dd3 100644 (file)
@@ -1862,7 +1862,6 @@ static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
        static enum amd_ip_block_type ip_order[] = {
                AMD_IP_BLOCK_TYPE_GMC,
                AMD_IP_BLOCK_TYPE_COMMON,
-               AMD_IP_BLOCK_TYPE_MMHUB,
                AMD_IP_BLOCK_TYPE_IH,
        };
 
index d95380efcf8cfc7a32eafaba9eab2633fa3055ee..8995dad81c18cf0016a901a8820d0bc98a815c98 100644 (file)
@@ -371,61 +371,6 @@ void mmhub_v1_0_init(struct amdgpu_device *adev)
 
 }
 
-static int mmhub_v1_0_early_init(void *handle)
-{
-       return 0;
-}
-
-static int mmhub_v1_0_late_init(void *handle)
-{
-       return 0;
-}
-
-static int mmhub_v1_0_sw_init(void *handle)
-{
-       return 0;
-}
-
-static int mmhub_v1_0_sw_fini(void *handle)
-{
-       return 0;
-}
-
-static int mmhub_v1_0_hw_init(void *handle)
-{
-       return 0;
-}
-
-static int mmhub_v1_0_hw_fini(void *handle)
-{
-       return 0;
-}
-
-static int mmhub_v1_0_suspend(void *handle)
-{
-       return 0;
-}
-
-static int mmhub_v1_0_resume(void *handle)
-{
-       return 0;
-}
-
-static bool mmhub_v1_0_is_idle(void *handle)
-{
-       return true;
-}
-
-static int mmhub_v1_0_wait_for_idle(void *handle)
-{
-       return 0;
-}
-
-static int mmhub_v1_0_soft_reset(void *handle)
-{
-       return 0;
-}
-
 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
                                                        bool enable)
 {
@@ -563,12 +508,6 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
        return 0;
 }
 
-static int mmhub_v1_0_set_clockgating_state(void *handle,
-                                           enum amd_clockgating_state state)
-{
-       return 0;
-}
-
 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 {
        int data;
@@ -586,35 +525,3 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
        if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
                *flags |= AMD_CG_SUPPORT_MC_LS;
 }
-
-static int mmhub_v1_0_set_powergating_state(void *handle,
-                                       enum amd_powergating_state state)
-{
-       return 0;
-}
-
-const struct amd_ip_funcs mmhub_v1_0_ip_funcs = {
-       .name = "mmhub_v1_0",
-       .early_init = mmhub_v1_0_early_init,
-       .late_init = mmhub_v1_0_late_init,
-       .sw_init = mmhub_v1_0_sw_init,
-       .sw_fini = mmhub_v1_0_sw_fini,
-       .hw_init = mmhub_v1_0_hw_init,
-       .hw_fini = mmhub_v1_0_hw_fini,
-       .suspend = mmhub_v1_0_suspend,
-       .resume = mmhub_v1_0_resume,
-       .is_idle = mmhub_v1_0_is_idle,
-       .wait_for_idle = mmhub_v1_0_wait_for_idle,
-       .soft_reset = mmhub_v1_0_soft_reset,
-       .set_clockgating_state = mmhub_v1_0_set_clockgating_state,
-       .set_powergating_state = mmhub_v1_0_set_powergating_state,
-};
-
-const struct amdgpu_ip_block_version mmhub_v1_0_ip_block =
-{
-       .type = AMD_IP_BLOCK_TYPE_MMHUB,
-       .major = 1,
-       .minor = 0,
-       .rev = 0,
-       .funcs = &mmhub_v1_0_ip_funcs,
-};
index baaa160c0d1cf33579bdc25b2bc37c4f739ec819..22b222b514dcc6ecc5d6cc797030f9ef5dc88568 100644 (file)
@@ -484,7 +484,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_VEGA10:
                amdgpu_ip_block_add(adev, &vega10_common_ip_block);
-               amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
                amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
                amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
                if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
@@ -500,7 +499,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
                break;
        case CHIP_RAVEN:
                amdgpu_ip_block_add(adev, &vega10_common_ip_block);
-               amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
                amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
                amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
                amdgpu_ip_block_add(adev, &psp_v10_0_ip_block);
index 06990316e329860a36f949ca9445f44cbb2864ab..beb2a81ab7daacae86bc171e5bebf50779c9fff0 100644 (file)
@@ -76,7 +76,6 @@ enum amd_ip_block_type {
        AMD_IP_BLOCK_TYPE_UVD,
        AMD_IP_BLOCK_TYPE_VCE,
        AMD_IP_BLOCK_TYPE_ACP,
-       AMD_IP_BLOCK_TYPE_MMHUB,
        AMD_IP_BLOCK_TYPE_VCN
 };