clk: meson: poke pll CNTL last

Poking CNTL first may take the PLL out of reset while we are still
applying the initial settings, including the filter values
initialization. This is the case for the axg and gxl gp0 pll.

Doing this poke last ensures the pll stays in reset while the initial
settings are applied.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index acb63c8e0fd8316f6f40f006a61f6bba91f83083..8226b82c67fd5c8126b5b74de440a40dc306fcbc 100644 (file)
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -193,12 +193,12 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
 };
 
 const struct reg_sequence axg_gp0_init_regs[] = {
-       { .reg = HHI_GP0_PLL_CNTL,      .def = 0x40010250 },
        { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084a000 },
        { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
        { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
        { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
        { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
+       { .reg = HHI_GP0_PLL_CNTL,      .def = 0x40010250 },
 };
 
 static struct clk_regmap axg_gp0_pll = {

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index bb0b0529ca8178fce0b7bfac397a955966c74e63..3cd07f9604890f18a05ff895f673fa476e88d70f 100644 (file)
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -390,10 +390,10 @@ static struct clk_regmap gxbb_sys_pll = {
 };
 
 const struct reg_sequence gxbb_gp0_init_regs[] = {
-       { .reg = HHI_GP0_PLL_CNTL,      .def = 0x6a000228 },
        { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x69c80000 },
        { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a5590c4 },
        { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x0000500d },
+       { .reg = HHI_GP0_PLL_CNTL,      .def = 0x4a000228 },
 };
 
 static struct clk_regmap gxbb_gp0_pll = {
@@ -437,12 +437,12 @@ static struct clk_regmap gxbb_gp0_pll = {
 };
 
 const struct reg_sequence gxl_gp0_init_regs[] = {
-       { .reg = HHI_GP0_PLL_CNTL,      .def = 0x40010250 },
        { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084a000 },
        { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
        { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
        { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
        { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
+       { .reg = HHI_GP0_PLL_CNTL,      .def = 0x40010250 },
 };
 
 static struct clk_regmap gxl_gp0_pll = {